SN74HC163 (ACTIVE)

4-Bit Synchronous Binary Counters

4-Bit Synchronous Binary Counters - SN74HC163
Datasheet
 

Description

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Internal Look-Ahead for Fast Counting
  • Carry Output for n-Bit Cascading
  • Synchronous Counting
  • Synchronously Programmable

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Parametrics Compare all products in Counter/Arithmetic/Parity Function

 
Technology Family
VCC (Min) (V)
VCC (Max) (V)
Bits (#)
Voltage (Nom) (V)
F @ Nom Voltage (Max) (Mhz)
ICC @ Nom Voltage (Max) (mA)
tpd @ Nom Voltage (Max) (ns)
Output Drive (IOL/IOH) (Max) (mA)
Function
Type
Rating
Operating Temperature Range (C)
Pin/Package
SN74HC163 SN54HC163 SN74HC163-Q1
HC    HC    HC   
2    2    2   
6    6    6   
4    4    4   
3.3
5   
3.3
5   
3.3
5   
28    28    28   
0.08    0.08    0.08   
46    46    46   
5.2/-5.2    5.2/-5.2    5.2/-5.2   
Counter    Counter    Counter   
Binary    Binary    Binary   
Catalog    Military    Automotive   
-40 to 85    -55 to 125    -40 to 85   
16PDIP
16SO
16SOIC
16TSSOP   
16CDIP
20LCCC   
16TSSOP   

Other qualified versions of SN74HC163

Version Part Number Definition
Military SN54HC163 QML certified for Military and Defense Applications
Automotive SN74HC163-Q1 Q100 devices qualified for high-reliability automotive applications targeting zero defects