SN74LVCHR16245A

ACTIVE

Product details

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVC Rating Catalog Operating temperature range (°C) -40 to 125
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVC Rating Catalog Operating temperature range (°C) -40 to 125
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments
    Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on
    All Ports (5-V Input/Output Voltage
    With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need
    for External Pullup or Pulldown Resistors
  • All Outputs Have Equivalent 26-Ω Series
    Resistors,So No External Resistors Are
    Required
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
  • Member of the Texas Instruments
    Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on
    All Ports (5-V Input/Output Voltage
    With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need
    for External Pullup or Pulldown Resistors
  • All Outputs Have Equivalent 26-Ω Series
    Resistors,So No External Resistors Are
    Required
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model

This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCHR16245A device is designed for asynchronous communication between data buses. The control-function implementation minimizes external-timing requirements.

This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCHR16245A device is designed for asynchronous communication between data buses. The control-function implementation minimizes external-timing requirements.

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Technical documentation

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Type Title Date
* Data sheet SN74LVCHR16245A 16-Bit Bus Transceiver With 3-State Outputs datasheet (Rev. Q) PDF | HTML 12 Oct 2014
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17 Sep 2018
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 23 Feb 2005
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

HSPICE MODEL OF SN74LVCHR16245A

SCEJ215.ZIP (101 KB) - HSpice Model
Simulation model

SN74LVCHR16245A IBIS Model (Rev. A)

SCAM012A.ZIP (41 KB) - IBIS Model
Package Pins CAD symbols, footprints & 3D models
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian

Ordering & quality

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Information included:
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