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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12D500RF

現行

12 位元、雙 500-MSPS 或單 1.0-GSPS、RF 取樣類比轉數位轉換器 (ADC)

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產品規格表

ADC12D500RF

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2020 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (bit) 9.7 SFDR (dB) 74.3 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2020 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (bit) 9.7 SFDR (dB) 74.3 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² 27 x 27
  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

All trademarks are the property of their respective owners.

  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

All trademarks are the property of their respective owners.

The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
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類型 標題 日期
* Data sheet ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC datasheet (Rev. E) 2013年 3月 25日
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017年 2月 3日
Application note Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 2014年 8月 6日
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 2013年 12月 9日
User guide Schematic and Layout Recommendations for the GSPS ADC 2013年 4月 29日
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 2013年 4月 26日
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 2012年 12月 18日
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 2012年 5月 16日

設計與開發

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支援軟體

WAVEVISION5 — WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

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產品
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硬體開發
開發板
ADC08D1520RB — ADC08D1520RB：低功耗、8 位元、雙 1.5 GSPS 或單 3.0 GSPS A/D 轉換器參考基板 ADC12D1600RB — 12 位元、雙路 1.6/1.8 GSPS 或單路 3.2/3.6 GSPS ADC 參考基板 ADC16DV160HFEB — ADC16DV160HFEB 評估板 LM98640CVAL — 具有 LVDS 輸出的雙通道、14 位元、40 MSPS 類比前端 WAVEVSN-BRD-5.1 — WaveVision 5 資料擷取板 5.1 版
軟體
應用軟體及架構
WAVEVISION5 — 資料採集和分析軟體
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模擬型號

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
參考設計

TIDA-00113 — 以單通道或雙通道模式驅動 GSPS ADC，適用於高頻寬應用

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00479 — 適用於 GSPS ADC 的最佳時鐘來源參考設計

The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00071 — 每秒千兆次取樣 (GSPS) ADC 的電路圖和佈線圖建議

This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)
使用指南: PDF
電路圖: PDF
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