支援軟體
CDCE18005
- Universal Input Buffers That Accept LVPECL, LVDS, or LVCMOS Level Signaling
- Fully Configurable Outputs Including Frequency, Output Format, and Output Skew
- Output Multiplexer That Serves as a Clock Switch Between the Three Reference Inputs
and the Outputs - Clock Generation Via AT-Cut Crystal
- Integrated EEPROM Determines Device Configuration at Power-up
- Low Additive Jitter Performance
- Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or
Combinations of Differential or Single-ended:- Low Additive Jitter
- Output Frequency up to 1.5 GHz
- LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
- Independent Output Dividers Support Divide Ratios from 1–80
- Independent limited Coarse Skew Control on all Outputs
- Flexible Inputs:
- Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL),
800 MHz (LVDS), or 250 MHz (LVCMOS). - One Auxiliary Input Accepts Crystal. Auxiliary Input Accepts Crystals in the Range of
2 MHz–42 MHz - Clock Generator Mode Using Crystal Input.
- Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL),
- Typical Power Consumption 1W at 3.3V
- Offered in QFN-48 Package
- ESD Protection Exceeds 2kV HBM
- Industrial Temperature Range –40°C to 85°C
The CDCE18005 is a high performance clock distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the CDCE18005 achieves low additive jitter in the 50 fs RMS(1) range. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz(2)
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Five/Ten Output Clock Programmable Buffer datasheet (Rev. B) | 2012年 11月 21日 | |
| User guide | Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz | 2008年 11月 11日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
CDCE18005EVM — CDCE18005EVM 評估模組
The CDCE18005 is a high performance clock generator and distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-board EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the (...)
使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 引腳 | 下載 |
|---|---|---|
| VQFN (RGZ) | 48 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。