CDCEL925
- Member of Programmable Clock Generator Family
- CDCEx913: 1-PLL, 3 Outputs
- CDCEx925: 2-PLL, 5 Outputs
- CDCEx925: 3-PLL, 7 Outputs
- CDCEx949: 4-PLL, 9 Outputs
- In-System Programmability and EEPROM
- Serial Programmable Volatile Register
- Nonvolatile EEPROM to Store Customer Settings
- Flexible Input Clocking Concept
- External Crystal: 8 MHz to 32 MHz
- On-Chip VCXO: Pull Range ±150 ppm
- Single-Ended LVCMOS Up to 160 MHz
- Free Selectable Output Frequency Up to 230 MHz
- Low-Noise PLL Core
- PLL Loop Filter Components Integrated
- Low Period Jitter (Typical 60 ps)
- Separate Output Supply Pins
- CDCE925: 3.3 V and 2.5 V
- CDCEL925: 1.8 V
- Flexible Clock Driver
- Three User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable, or Power Down
- Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPS
- Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
- Programmable SSC Modulation
- Enables 0-PPM Clock Generation
- 1.8-V Device Power Supply
- Wide Temperature Range: –40°C to 85°C
- Packaged in TSSOP
- Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
- APPLICATIONS
- D-TVs, STBs, IP-STBs, DVD Players, DVD Recorders, and Printers
All other trademarks are the property of their respective owners
The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to two independent configurable PLLs.
The CDCEx925 has a separate output supply pin, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for CDCE925.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS), or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for example.
All PLLs support SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change the SSC setting for lowering EMI, or other control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so forth.
The CDCx925 operates in a 1.8-V environment and in a temperature range of –40°C to 85°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE(L)925: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. I) | PDF | HTML | 2016年 10月 27日 |
| Application note | VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) | 2012年 4月 23日 | ||
| User guide | CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) | 2010年 11月 22日 | ||
| User guide | CDCE(L)9xx Performance Evaluation Module (Rev. A) | 2010年 7月 7日 | ||
| Application note | Troubleshooting I2C Bus Protocol | 2009年 10月 19日 | ||
| Application note | Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 | 2009年 9月 23日 | ||
| User guide | CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual | 2008年 12月 9日 | ||
| Application note | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 2008年 3月 31日 | ||
| Application note | Practical consideration on choosing a crystal for CDCE(L)9xx family | 2008年 3月 24日 | ||
| Application note | Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A) | 2007年 8月 8日 |
設計與開發
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- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
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