SN65LVDS4
- Designed for Signaling Rates(1) up to:
- 500-Mbps Receiver
- Operates From a 1.8-V or 2.5-V Core Supply
- Available in 1.5-mm × 2-mm UQFN Package
- Bus-Terminal ESD Exceeds 2 kV (HBM)
- Low-Voltage Differential Signaling With Typical
Output Voltages of 350 mV Into a 100-Ω Load - Propagation Delay Times
- 2.1 ns Typical Receiver
- Power Dissipation at 250 MHz
- 40 mW Typical
- Requires External Failsafe
- Differential Input Voltage Threshold Less Than 50
mV - Can Provide Output Voltage Logic Level (3.3-V
LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
on External VDD Pin, Thus Eliminating External
LevelTranslation
The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.
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檢視所有 9 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN65LVDS4 1.8-V High-Speed Differential Line Receiver datasheet (Rev. A) | PDF | HTML | 2015年 11月 30日 |
| Application brief | How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver | 2019年 1月 9日 | ||
| Application brief | How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter | 2018年 12月 28日 | ||
| Application brief | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| Application note | TMDS Clock Detection Solution in HDMI Sink Applications | 2017年 8月 23日 | ||
| Technical article | Get Connected: High-speed LVDS comparator | PDF | HTML | 2015年 6月 3日 | |
| EVM User's guide | SN65LVDS4 Evaluation Module | 2011年 7月 15日 |
設計與開發
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開發板
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模擬工具
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參考設計
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| UQFN (RSE) | 10 | 檢視選項 |
訂購與品質
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- 材料內容
- 資格摘要
- 進行中可靠性監測
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