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The ARM CorePac is added in the 66AK2Hxx to enable the ability for layer 2 and layer 3 processing on-chip. Operations such as traffic control, local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor core.
The ARM CorePac of the 66AK2Hxx integrates one or more Cortex-A15 processor clusters with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order superscalar execution engine with integrated L1 caches. The implementation also supports advanced SIMDv2 (NEON technology) and VFPv4 (vector floating point) architecture extensions, security, virtualization, LPAE (large physical address extension), and multiprocessing extensions. The ARM CorePac includes a 4MB L2 cache and support for AMBA4 AXI and AXI coherence extension (ACE) protocols. An interrupt controller is included in the ARM CorePac to handle host interrupt requests in the system. For more information, see the KeyStone II Architecture ARM CorePac User's Guide.
The ARM CorePac has three functional clock domains, including a high-frequency clock domain used by the Cortex-A15. The high-frequency domain is isolated from the rest of the device by asynchronous bridges.
The key features of the Quad Core ARM CorePac are as follows:
The ARM CorePac integrates the following group of submodules.
The ARM Cortex-A15 processor incorporates the technologies available in the ARM7™ architecture. These technologies include NEON for media and signal processing and Jazelle® RCT for acceleration of real-time compilers, Thumb®-2 technology for code density, and the VFPv4 floating point architecture. For details, see the ARM Cortex-A15 Processor Technical Reference Manual.
Table 7-1 shows the features supported by the Cortex-A15 processor core.
|ARM version 7-A ISA||Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and media extensions|
|Backward compatible with previous ARM ISA versions|
|Cortex-A15 processor version||R2P4|
|Integer core||Main core for processing integer instructions|
|NEON core||Gives greatly enhanced throughput for media workloads and VFP-Lite support|
|Architecture Extensions||Security, virtualization and LPAE (40-bit physical address) extensions|
|L1 Lcache and Dcache||32KB, 2-way, 16 word line, 128 bit interface|
|L2 cache||4096KB, 16-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported shared between cores|
|L2 valid bits cleared by software loop or by hardware|
|Cache Coherency||Support for coherent memory accesses between A15 cores and other noncore master peripherals (Ex: EDMA) in the DDR3A and MSMC SRAM space.|
|Branch target address cache||Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return stack, and an indirect predictor|
|Enhanced memory management unit||Mapping sizes are 4KB, 64KB, 1MB, and 16MB|
|Buses||128b AXI4 internal bus from Cortex-A15 converted to a 256b VBUSM to interface (through the MSMC) with MSMC SRAM, DDR EMIF, ROM, Interrupt controller and other system peripherals|
|Noninvasive Debug Support||Processor instruction trace using 4x Program Trace Macrocell (CoreSight PTM), Data trace (print-f style debug) using System Trace Macrocell (CoreSight STM) and Performance Monitoring Units (PMU)|
|Misc Debug Support||JTAG based debug and Cross triggering|
|Clocking||Dedicated ARM PLL for flexible clocking scenarios|
|Voltage||SmartReflex voltage domain for automatic voltage scaling|
|Power||Support for standby modes and separate core power domains for additional leakage power reduction|
The ARM CorePac interrupt controller (AINTC) is responsible for prioritizing all service requests from the system peripherals and the secondary interrupt controller CIC2 and then generating either nIRQ or nFIQ to the Cortex-A15 processor. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. The AINTC interfaces to the Cortex-A15 processor via the AXI port through an VBUS2AXI bridge and runs at half the processor speed. It has the capability to handle up to 480 requests, which can be steered/prioritized as A15 nFIQ or nIRQ interrupt requests.
The general features of the AINTC are:
On the chip level, there is a dedicated chip level interrupt controller to serve the ARM interrupt controller. See Section 8.3 for more details.
The ARM CorePac can operate in either little-endian or big-endian mode. When the ARM CorePac is in little-endian mode and the rest of the system is in big-endian mode, the bridges in the ARM CorePac are responsible for performing the endian conversion.
The ARM CorePac has two slave ports. The 66AK2Hxx masters cannot access the ARM CorePac internal memory space.
One master port comes out of the ARM CorePac. The master port is a 256-bit-wide port for the transactions going to the MSMC and DDR_EMIF data spaces.
The ARM CorePac includes a dedicated embedded DPLL (ARM PLL). The Cortex-A15 processor core clocks are sourced from this ARM PLL Controller. The Cortex-A15 processor core clock has a maximum frequency of 1.4 GHz. The ARM CorePac subsytem also uses the SYSCLK1 clock source from the main PLL which is locally divided (/1, /3 and /6) and provided to certain submodules inside the ARM CorePac. AINTC sub module runs at a frequency of SYSCLK1/6.
The ARM CorePac does not support local reset. It is reset whenever the device is under reset. In addition, the interrupt controller (AINTC) can only be reset during POR and RESETFULL. AINTC also resets whenever device is under reset.
For the complete programming model, refer to the KeyStone II Architecture ARM CorePac User's Guide.