12.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each family member has one of two prefixes: X or [blank]. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices/tools.
Device development evolutionary flow:
X: Experimental device that is not necessarily representative of the final device's electrical specifications
[Blank]: Fully qualified production device
Support tool development evolutionary flow:
X: Development-support product that has not yet completed Texas Instruments internal qualification testing.
[Blank]: Fully qualified development-support product
Experimental (X) and fully qualified [Blank] devices and development-support tools are shipped with the following disclaimer:
Developmental product is intended for internal evaluation purposes.
Fully qualified and production devices and development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that experimental devices (X) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, AAW), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).
For device part numbers and further ordering information for 66AK2Hxx in the AAW package type, see ti.com or contact your TI sales representative.
Figure 12-1 provides a legend for reading the complete device name for any C66x+ DSP generation member.
Figure 12-1 C66x DSP Device Nomenclature (Including the 66AK2Hxx Device)
12.2 Tools and Software
TI offers and extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.
Design Kits and Evaluation Modules
TCI6636K2H Evaluation Module Enables developers to immediately start evaluating TCI6636K2H processor and begin building application around it especially those demanding high-performance computation like telecom infrastructures, wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE,FDD-LTE, and WiMAX.
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors Integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
XDS200 USB Debug Probe Features a balance of low cost with good performance between the super low cost XDS100 and the high performance XDS560v2. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).
XDS560v2 System Trace USB & Ethernet Debug Probe Adds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).
XDS560v2 System Trace USB Debug Probe Connects to the target board via a MIPI HSPT 60-pin connector (with multiple adapters for TI 14-pin, TI 20-pin and ARM 20 pin) and to the host PC via USB2.0 High speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the host PC.
TI Design Network
Keystone II SoC Solution Provides a complete stack of operating system and communications software for the TI Keystone II architecture. It includes a Yocto based commercial Linux distribution, DSP operating system (OSEck®) and an optimized communication service between ARM cores, DSP cores, and external CPUs in the system (LINX).
OSEck Provides a full-featured, compact, real-time kernel for DSPs that is optimized to suit the specific requirements of high performance, memory constrained applications. OSEck is a compact kernel and has an extremely small memory footprint, but still combines rich functionality with high performance and true real-time behavior.
Wind River Linux Delivers a commercial-grade Linux platform, advanced features, fully integrated development tools and worldwide support.
Wind River Vxworks Delivers a proven combination of high-performance determinism with a flexible modular architecture to optimize footprint and deliver unparalleled scalability, advanced security, and comprehensive multicore options.
12.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com (66AK2H14, 66AK2H12, 66AK2H06). In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral is listed below.
ARM Optimizing C/C++ Compiler
Explains how to use these compiler tools: compiler, library build utility, and C++ name demangler.
ARM Assembly Language Tools
Explains how to use these object file tools: Assembler, archiver, linker, library information archiver, absolute lister, cross-reference lister, disassembler, object file display utility, name utility, strip utility, and hex conversion utility.
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
Describes the operation of the KeyStone software-programmable phase-locked loop (PLL) Controller. The PLL Controller offers flexibility and convenience by way of software-configurable multipliers and dividers to modify the input signal internally. The resulting clock outputs are passed to the CorePacs, peripherals, and other modules inside the device.
KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide
The SerDes performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. The SerDes includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide
Describes the Enhanced Direct Memory Access (EDMA3) controller. The primary purpose of the EDMA3 controller is to service data transfers that you program between two memory-mapped slave endpoints on the device.
KeyStone Architecture Multicore Navigator User's Guide
Describes the functionality, operational details, and programming information for the PKTDMA and the components of the QMSS in KeyStone architecture devices.
Keystone II Architecture DDR3 Memory Controller User's Guide
Describes how the DDR3 memory controller is used to interface with JESD79-3C standard compliant SDRAM devices. Memory types such as DDR1 SDRAM, DDR2 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR3 memory controller SDRAM can be used for program and data storage.
KeyStone Architecture Power Sleep Controller (PSC) User's Guide
Describes the functionality, operational details, and programming information for the Power Sleep Controller (PSC) module in KeyStone architecture devices.
KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide
Describes the features, architecture, and details of the Universal Serial Bus 3.0 (USB 3.0) peripheral.
KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User's Guide
Describes the features, architecture, and details of the Peripheral Component Interconnect Express (PCIe).
KeyStone II Architecture Debug and Trace User's Guide
Describes the capabilities of the trace features available through the debug architecture on KeyStone devices. Trace information can be gathered at the DSP core level or at the system level. The Debug Subsystem captures and exports trace data for both levels of trace. Trace is implemented as a nonintrusive debug tool within the KeyStone architecture, but can be selected to operate in both intrusive and nonintrusive mode depending on the amount of data the user wants to export.
KeyStone II Architecture ARM Bootloader User's Guide
Describes the features of the on-chip bootloader provided with the ARM Cortex-A15 processor.
KeyStone Architecture DSP Bootloader User's Guide
Describes the features of the on-chip bootloader provided with C66x_Digital Signal Processors (DSP).
KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User's Guide
Gives a functional description of the Ethernet Switch Subsystem and related portions of the Serializer/Deserializer (SerDes) module. The Ethernet Switch Subsystem consists of the Ethernet Media Access Controller (EMAC) module, Serial Gigabit Media Independent Interface (SGMII) modules, Physical Layer (PHY) device Management Data Input/Output (MDIO) module, Ethernet Switch module, and other associated submodules that are integrated on the device.
TMS320C66x DSP CorePac User's Guide
Provides an overview of the main components and features of the C66x CorePac.
KeyStone Architecture Memory Protection Unit (MPU) User's Guide
Describes the functionality, operational details, and programming information for the KeyStone Architecture Memory Protection Unit (MPU).
KeyStone Architecture HyperLink User's Guide
Provides a high-speed, low-latency, and low-pin-count communication interface that extends the internal CBA 3.x-based transactions between two KeyStone devices.
KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide
Gives a functional description of the 10 Gigabit Ethernet Switch Subsystem and related portions of the Serializer/Deserializer (SerDes) module. The Ethernet Switch Subsystem consists of the Ethernet Media Access Controller (EMAC) module, Serial Gigabit Media Independent Interface (SGMII) modules, Physical Layer (PHY) device Management Data Input/Output (MDIO) module, Ethernet Switch module, and other associated submodules that are integrated on the device.
KeyStone Architecture Security Accelerator (SA) User's Guide
Provides hardware engines to perform encryption, decryption, and authentication operations on packets for commonly supported protocols, including IPsec ESP and AH, SRTP, and Air Cipher. The SA also provides the hardware modules to assist the host in generating public keys and random numbers.
KeyStone II Architecture Multicore Shared Memory Controller (MSMC) User's Guide
The MSMC manages traffic among ARM CorePacs, multiple C66x CorePacs, DMA, other mastering peripherals, and the EMIF in a multicore device. MSMC also provides a shared on-chip SRAM that is accessible by all the CorePacs and the mastering peripherals on the device. MSMC provides memory protection for accesses to the MSMC SRAM and DDR3 memory from system masters.
KeyStone Architecture Serial Rapid IO (SRIO) User's Guide
Describes the general operation of SRIO, how this module is connected to the outside world, the features supported, SRIO registers, and examples of channel and queue operations.
KeyStone II Architecture ARM CorePac User's Guide
Describes the ARM CorePac in the KeyStone II Architecture, but it does not describe the details of the ARM core itself.
KeyStone Architecture Packet Accelerator (PA) User's Guide
One of the main components of the network coprocessor (NETCP) peripheral, the PA works together with the security accelerator (SA) and the gigabit Ethernet switch subsystem to form a network processing solution. The purpose of PA in the NETCP is to perform packet processing operations such as packet header classification, checksum generation, and multiqueue routing.
KeyStone Architecture Serial Peripheral Interface (SPI) User's Guide
Describes the features, architecture and registers associated with the serial peripheral interface (SPI) module.
KeyStone Architecture Chip Interrupt Controller (CIC) User's Guide
Describes the functionality, operational details, and programming information for the KeyStone Architecture Chip Interrupt Controller (CIC).
KeyStone Architecture Timer 64P User's Guide
Provides an overview of the 64-bit timer in the KeyStone Architecture devices. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other.
KeyStone Architecture Inter-IC control Bus (I2C) User's Guide
Describes the inter-integrated circuit (I2C) module in the KeyStone Architecture Digital Signal Processor (DSP). The I2C provides an interface between the KeyStone device and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. This document assumes the reader is familiar with the I2C-bus specification.
KeyStone Architecture External Memory Interface (EMIF16) User's Guide
Describes the operation of the External Memory Interface (EMIF16) module in the KeyStone DSP family (refer to the device data manual for applicability to a particular part). The EMIF16 module is accessible across all the cores and all system masters that are not cores.
TMS320C66x DSP Cache User's Guide
Describes how the cache-based memory system of the C66x DSP can be efficiently used in DSP applications. The internal memory architecture of these devices is organized in a two-level hierarchy consisting of a dedicated program memory (L1P) and a dedicated data memory (L1D) on the first level. Accesses by the core to the these first level memories can complete without core pipeline stalls.
KeyStone Architecture General-Purpose Input/Output (GPIO) User's Guide
Describes the general-purpose input/output (GPIO) peripheral in the KeyStone digital signal processors (DSPs).
KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User's Guide
Performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
TMS320C66x DSP CPU and Instruction Set Reference Guide
Describes the CPU architecture, pipeline, instruction set, and interrupts of the C66x DSP.
KeyStone Architecture Network Coprocessor (NETCP) User's Guide
Describes the network coprocessor (NETCP) hardware accelerator that processes data packets with a main focus on processing Ethernet packets. NETCP has two gigabit Ethernet (GbE) modules to send and receive packets from an IEEE 802.3 compliant network, a packet accelerator (PA) to perform packet classification operations such as header matching, and packet modification operations such as checksum generation, A and a security accelerator (SA) to encrypt and decrypt data packets.
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12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.