SPRS866G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14


  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Enhancements in KeyStone II
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
    7. 6.7 C66x CorePac Register Descriptions
  7. ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. MPU Register Map
        2. Device-Specific MPU Registers
          1. Configuration Register (CONFIG)
      2. 8.2.2 MPU Programmable Range Registers
        1. Programmable Range n Start Address Register (PROGn_MPSAR)
        2. Programmable Range n - End Address Register (PROGn_MPEAR)
        3. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. CIC0 Register Map
        2. CIC1 Register Map
        3. CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. Boot Device Field
        2. Device Configuration Field
          1. Sleep Boot Mode Configuration
          2. I2C Boot Device Configuration
            1. I2C Passive Mode
            2. I2C Master Mode
          3. SPI Boot Device Configuration
          4. EMIF Boot Device Configuration
          5. NAND Boot Device Configuration
        3. Serial Rapid I/O Boot Device Configuration
        4. Ethernet (SGMII) Boot Device Configuration
          1. PCIe Boot Device Configuration
          2. HyperLink Boot Device Configuration
          3. UART Boot Device Configuration
        5. Boot Parameter Table
          1.  EMIF16 Boot Parameter Table
          2.  SRIO Boot Parameter Table
          3.  Ethernet Boot Parameter Table
          4.  PCIe Boot Parameter Table
          5.  I2C Boot Parameter Table
          6.  SPI Boot Parameter Table
          7.  HyperLink Boot Parameter Table
          8.  UART Boot Parameter Table
          9.  NAND Boot Parameter Table
          10. DDR3 Configuration Table
        6. Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1.  Device Status (DEVSTAT) Register
        2.  Device Configuration Register
        3.  JTAG ID (JTAGID) Register Description
        4.  Kicker Mechanism (KICK0 and KICK1) Register
        5.  DSP Boot Address Register (DSP_BOOT_ADDRn)
        6.  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7.  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8.  Reset Status (RESET_STAT) Register
        9.  Reset Status Clear (RESET_STAT_CLR) Register
        10. Boot Complete (BOOTCOMPLETE) Register
        11. Power State Control (PWRSTATECTL) Register
        12. NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. IPC Generation (IPCGRx) Registers
        14. IPC Acknowledgment (IPCARx) Registers
        15. IPC Generation Host (IPCGRH) Register
        16. IPC Acknowledgment Host (IPCARH) Register
        17. Timer Input Selection Register (TINPSEL)
        18. Timer Output Selection Register (TOUTPSEL)
        19. Reset Mux (RSTMUXx) Register
        20. Device Speed (DEVSPEED) Register
        21. ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. System Endian Status Register (SYSENDSTAT)
        27. SYNECLK_PINCTL Register
        28. USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. Core-Before-IO Power Sequencing
        2. IO-Before-Core Power Sequencing
        3. Prolonged Resets
        4. Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. Internal Clocks and Maximum Operating Frequencies
        2. Local Clock Dividers
        3. Module Clock Input
        4. Main PLL Controller Operating Modes
        5. Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. PLL Secondary Control Register (SECCTL)
        2. PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. PLL Controller Clock Align Control Register (ALNCTL)
        4. PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. SYSCLK Status Register (SYSTAT)
        6. Reset Type Status Register (RSTYPE)
        7. Reset Control Register (RSTCTRL)
        8. Reset Configuration Register (RSTCFG)
        9. Reset Isolation Register (RSISO)
      3. 11.5.3 Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
    12. 11.12 HyperLink Peripheral
    13. 11.13 UART Peripheral
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. ARM Subsystem Features
        2. DSP Features
      2. 11.26.2 ICEPick Module
        1. ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. Trace Electrical Data and Timing
      7. 11.27.7 IEEE 1149.1 JTAG
        1. IEEE 1149.1 JTAG Compatibility Statement
        2. JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAW|1517
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device and Documentation Support

Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each family member has one of two prefixes: X or [blank]. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices/tools.

Device development evolutionary flow:

  • X: Experimental device that is not necessarily representative of the final device's electrical specifications
  • [Blank]: Fully qualified production device

Support tool development evolutionary flow:

  • X: Development-support product that has not yet completed Texas Instruments internal qualification testing.
  • [Blank]: Fully qualified development-support product

Experimental (X) and fully qualified [Blank] devices and development-support tools are shipped with the following disclaimer:

Developmental product is intended for internal evaluation purposes.

Fully qualified and production devices and development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that experimental devices (X) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, AAW), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).

For device part numbers and further ordering information for 66AK2Hxx in the AAW package type, see ti.com or contact your TI sales representative.

Figure 12-1 provides a legend for reading the complete device name for any C66x+ DSP generation member.

66AK2H14 66AK2H12 66AK2H06 Device_Nomenclature_66AK2H12.gif Figure 12-1 C66x DSP Device Nomenclature (Including the 66AK2Hxx Device)

Tools and Software

TI offers and extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.


Design Kits and Evaluation Modules

    TCI6636K2H Evaluation Module Enables developers to immediately start evaluating TCI6636K2H processor and begin building application around it especially those demanding high-performance computation like telecom infrastructures, wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE,FDD-LTE, and WiMAX.


    CODECS- Video, Speech - for C66x-based Devices Describes the free TI codecs that come with production licensing and are available for download now. All are production-tested for easy integration into video, and voice applications.
    TMS320C6000 DSP Library (DSPLIB) Describes the platform optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications.
    TMS320C6000 Image Library (IMGLIB) Provides an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications.

Development Tools

    Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors Integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
    XDS200 USB Debug Probe Features a balance of low cost with good performance between the super low cost XDS100 and the high performance XDS560v2. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).
    XDS560v2 System Trace USB & Ethernet Debug Probe Adds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).
    XDS560v2 System Trace USB Debug Probe Connects to the target board via a MIPI HSPT 60-pin connector (with multiple adapters for TI 14-pin, TI 20-pin and ARM 20 pin) and to the host PC via USB2.0 High speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the host PC.

TI Design Network

    Keystone II SoC Solution Provides a complete stack of operating system and communications software for the TI Keystone II architecture. It includes a Yocto based commercial Linux distribution, DSP operating system (OSEck®) and an optimized communication service between ARM cores, DSP cores, and external CPUs in the system (LINX).
    OSEck Provides a full-featured, compact, real-time kernel for DSPs that is optimized to suit the specific requirements of high performance, memory constrained applications. OSEck is a compact kernel and has an extremely small memory footprint, but still combines rich functionality with high performance and true real-time behavior.
    Wind River Linux Delivers a commercial-grade Linux platform, advanced features, fully integrated development tools and worldwide support.
    Wind River Vxworks Delivers a proven combination of high-performance determinism with a flexible modular architecture to optimize footprint and deliver unparalleled scalability, advanced security, and comprehensive multicore options.

Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com (66AK2H14, 66AK2H12, 66AK2H06). In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral is listed below.


Application Reports

    TI DSP Benchmarking Provides benchmarks for the C674x DSP core, the C66x DSP core and the ARM Cortex-A15 core.
    DDR3 Design Requirements for KeyStone Devices
    Provides implementation instructions for the DDR3 interface incorporated in the TI KeyStone series of DSP devices. The DDR3 interface supports 1600 MT/s and lower memory speeds in a variety of topologies.
    Hardware Design Guide for KeyStone II Devices
    Describes hardware system design considerations for the KeyStone II family of processors. This design guide is intended to be used as an aid during the development of application hardware. Other aids including, but not limited to, device data manuals and explicit collateral should also be used.

User's Guides

    ARM Assembly Language Tools
    Explains how to use these object file tools: Assembler, archiver, linker, library information archiver, absolute lister, cross-reference lister, disassembler, object file display utility, name utility, strip utility, and hex conversion utility.
    KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
    Describes the operation of the KeyStone software-programmable phase-locked loop (PLL) Controller. The PLL Controller offers flexibility and convenience by way of software-configurable multipliers and dividers to modify the input signal internally. The resulting clock outputs are passed to the CorePacs, peripherals, and other modules inside the device.
    KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide
    The SerDes performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. The SerDes includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
    Keystone II Architecture DDR3 Memory Controller User's Guide
    Describes how the DDR3 memory controller is used to interface with JESD79-3C standard compliant SDRAM devices. Memory types such as DDR1 SDRAM, DDR2 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR3 memory controller SDRAM can be used for program and data storage.
    KeyStone II Architecture Debug and Trace User's Guide
    Describes the capabilities of the trace features available through the debug architecture on KeyStone devices. Trace information can be gathered at the DSP core level or at the system level. The Debug Subsystem captures and exports trace data for both levels of trace. Trace is implemented as a nonintrusive debug tool within the KeyStone architecture, but can be selected to operate in both intrusive and nonintrusive mode depending on the amount of data the user wants to export.
    KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User's Guide
    Gives a functional description of the Ethernet Switch Subsystem and related portions of the Serializer/Deserializer (SerDes) module. The Ethernet Switch Subsystem consists of the Ethernet Media Access Controller (EMAC) module, Serial Gigabit Media Independent Interface (SGMII) modules, Physical Layer (PHY) device Management Data Input/Output (MDIO) module, Ethernet Switch module, and other associated submodules that are integrated on the device.
    KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide
    Gives a functional description of the 10 Gigabit Ethernet Switch Subsystem and related portions of the Serializer/Deserializer (SerDes) module. The Ethernet Switch Subsystem consists of the Ethernet Media Access Controller (EMAC) module, Serial Gigabit Media Independent Interface (SGMII) modules, Physical Layer (PHY) device Management Data Input/Output (MDIO) module, Ethernet Switch module, and other associated submodules that are integrated on the device.
    KeyStone Architecture Security Accelerator (SA) User's Guide
    Provides hardware engines to perform encryption, decryption, and authentication operations on packets for commonly supported protocols, including IPsec ESP and AH, SRTP, and Air Cipher. The SA also provides the hardware modules to assist the host in generating public keys and random numbers.
    KeyStone II Architecture Multicore Shared Memory Controller (MSMC) User's Guide
    The MSMC manages traffic among ARM CorePacs, multiple C66x CorePacs, DMA, other mastering peripherals, and the EMIF in a multicore device. MSMC also provides a shared on-chip SRAM that is accessible by all the CorePacs and the mastering peripherals on the device. MSMC provides memory protection for accesses to the MSMC SRAM and DDR3 memory from system masters.
    KeyStone Architecture Packet Accelerator (PA) User's Guide
    One of the main components of the network coprocessor (NETCP) peripheral, the PA works together with the security accelerator (SA) and the gigabit Ethernet switch subsystem to form a network processing solution. The purpose of PA in the NETCP is to perform packet processing operations such as packet header classification, checksum generation, and multiqueue routing.
    KeyStone Architecture Timer 64P User's Guide
    Provides an overview of the 64-bit timer in the KeyStone Architecture devices. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other.
    KeyStone Architecture Inter-IC control Bus (I2C) User's Guide
    Describes the inter-integrated circuit (I2C) module in the KeyStone Architecture Digital Signal Processor (DSP). The I2C provides an interface between the KeyStone device and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. This document assumes the reader is familiar with the I2C-bus specification.
    TMS320C66x DSP Cache User's Guide
    Describes how the cache-based memory system of the C66x DSP can be efficiently used in DSP applications. The internal memory architecture of these devices is organized in a two-level hierarchy consisting of a dedicated program memory (L1P) and a dedicated data memory (L1D) on the first level. Accesses by the core to the these first level memories can complete without core pipeline stalls.
    KeyStone Architecture Network Coprocessor (NETCP) User's Guide
    Describes the network coprocessor (NETCP) hardware accelerator that processes data packets with a main focus on processing Ethernet packets. NETCP has two gigabit Ethernet (GbE) modules to send and receive packets from an IEEE 802.3 compliant network, a packet accelerator (PA) to perform packet classification operations such as header matching, and packet modification operations such as checksum generation, A and a security accelerator (SA) to encrypt and decrypt data packets.

White Papers

    Multicore SoCs Stay a Step Ahead of SoC FPGAs
    Describes the differences between SoCs and FPGAs. Recently, the integration of ARM Cortex-A cores into FPGAs and compute-intense cores could lead one to believe that the paths of true multicore SoCs and these so-called FPGA SoCs had converged. A closer examination reveals that in reality they are still very far apart and that true multicore SoCs offer increasing advantages in those critical areas required by today’s demanding products.
    A Better Way to Cloud
    Explores the factors around the shifts in cloud computing and highlights the differences between traditional cloud computing and cloud computing-based on embedded processing.

Design Files

Other Documents

Related Links

Table 12-1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 12-1 Related Links

66AK2H14 Click here Click here Click here Click here Click here
66AK2H12 Click here Click here Click here Click here Click here
66AK2H06 Click here Click here Click here Click here Click here

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.


SmartReflex, C6000, E2E are trademarks of Texas Instruments.

MPCore, NEON, CoreSight, ARM7 are trademarks of ARM Ltd or its subsidiaries.

ARM, Cortex, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.

Windows is a registered trademark of Microsoft Corp.

All other trademarks are the property of their respective owners.

Electrostatic Discharge Caution


This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.


    TI Glossary This glossary lists and explains terms, acronyms, and definitions.