SPRS866G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14


  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Enhancements in KeyStone II
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
    7. 6.7 C66x CorePac Register Descriptions
  7. ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. MPU Register Map
        2. Device-Specific MPU Registers
          1. Configuration Register (CONFIG)
      2. 8.2.2 MPU Programmable Range Registers
        1. Programmable Range n Start Address Register (PROGn_MPSAR)
        2. Programmable Range n - End Address Register (PROGn_MPEAR)
        3. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. CIC0 Register Map
        2. CIC1 Register Map
        3. CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. Boot Device Field
        2. Device Configuration Field
          1. Sleep Boot Mode Configuration
          2. I2C Boot Device Configuration
            1. I2C Passive Mode
            2. I2C Master Mode
          3. SPI Boot Device Configuration
          4. EMIF Boot Device Configuration
          5. NAND Boot Device Configuration
        3. Serial Rapid I/O Boot Device Configuration
        4. Ethernet (SGMII) Boot Device Configuration
          1. PCIe Boot Device Configuration
          2. HyperLink Boot Device Configuration
          3. UART Boot Device Configuration
        5. Boot Parameter Table
          1.  EMIF16 Boot Parameter Table
          2.  SRIO Boot Parameter Table
          3.  Ethernet Boot Parameter Table
          4.  PCIe Boot Parameter Table
          5.  I2C Boot Parameter Table
          6.  SPI Boot Parameter Table
          7.  HyperLink Boot Parameter Table
          8.  UART Boot Parameter Table
          9.  NAND Boot Parameter Table
          10. DDR3 Configuration Table
        6. Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1.  Device Status (DEVSTAT) Register
        2.  Device Configuration Register
        3.  JTAG ID (JTAGID) Register Description
        4.  Kicker Mechanism (KICK0 and KICK1) Register
        5.  DSP Boot Address Register (DSP_BOOT_ADDRn)
        6.  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7.  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8.  Reset Status (RESET_STAT) Register
        9.  Reset Status Clear (RESET_STAT_CLR) Register
        10. Boot Complete (BOOTCOMPLETE) Register
        11. Power State Control (PWRSTATECTL) Register
        12. NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. IPC Generation (IPCGRx) Registers
        14. IPC Acknowledgment (IPCARx) Registers
        15. IPC Generation Host (IPCGRH) Register
        16. IPC Acknowledgment Host (IPCARH) Register
        17. Timer Input Selection Register (TINPSEL)
        18. Timer Output Selection Register (TOUTPSEL)
        19. Reset Mux (RSTMUXx) Register
        20. Device Speed (DEVSPEED) Register
        21. ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. System Endian Status Register (SYSENDSTAT)
        27. SYNECLK_PINCTL Register
        28. USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. Core-Before-IO Power Sequencing
        2. IO-Before-Core Power Sequencing
        3. Prolonged Resets
        4. Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. Internal Clocks and Maximum Operating Frequencies
        2. Local Clock Dividers
        3. Module Clock Input
        4. Main PLL Controller Operating Modes
        5. Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. PLL Secondary Control Register (SECCTL)
        2. PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. PLL Controller Clock Align Control Register (ALNCTL)
        4. PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. SYSCLK Status Register (SYSTAT)
        6. Reset Type Status Register (RSTYPE)
        7. Reset Control Register (RSTCTRL)
        8. Reset Configuration Register (RSTCFG)
        9. Reset Isolation Register (RSISO)
      3. 11.5.3 Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
    12. 11.12 HyperLink Peripheral
    13. 11.13 UART Peripheral
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. ARM Subsystem Features
        2. DSP Features
      2. 11.26.2 ICEPick Module
        1. ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. Trace Electrical Data and Timing
      7. 11.27.7 IEEE 1149.1 JTAG
        1. IEEE 1149.1 JTAG Compatibility Statement
        2. JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAW|1517
Thermal pad, mechanical data (Package|Pins)
Orderable Information

C66x CorePac

The C66x CorePac consists of several components:

  • Level-one and level-two memories (L1P, L1D, L2)
  • Data Trace Formatter (DTF)
  • Embedded Trace Buffer (ETB)
  • Interrupt controller
  • Power-down controller
  • External memory controller
  • Extended memory controller
  • A dedicated local power/sleep controller (LPSC)

The C66x CorePac also provides support for big and little endianness, memory protection, and bandwidth management (for resources local to the CorePac). Figure 6-1 shows a block diagram of the C66x CorePac.

66AK2H14 66AK2H12 66AK2H06 C66x_CorePac_Block_Diagram_NO_RSA.gif Figure 6-1 C66x CorePac Block Diagram

For more detailed information on the C66x CorePac in the 66AK2Hxx device, see the TMS320C66x DSP CorePac User's Guide.

C66x DSP CorePac

The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. The C66x CPU also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000™ architecture (for example, execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.

For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following documents:

Memory Architecture

Each C66x CorePac of the 66AK2Hxx device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contains a 6144KB multicore shared memory (MSM). All memory on the 66AK2Hxx has a unique location in the memory map (see Section 8).

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the KeyStone Architecture DSP Bootloader User's Guide.

For more information on the operation L1 and L2 caches, see the TMS320C66x DSP Cache User's Guide.

L1P Memory

The L1P memory configuration for the 66AK2Hxx device is as follows:

  • Region 0 size is 0KB (disabled)
  • Region 1 size is 32KB with no wait states

Figure 6-2 shows the available SRAM/cache configurations for L1P.

66AK2H14 66AK2H12 66AK2H06 L1P_Memory_Configuration_6616.gif Figure 6-2 L1P Memory Configurations

L1D Memory

The L1D memory configuration for the 66AK2Hxx device is as follows:

  • Region 0 size is 0KB (disabled)
  • Region 1 size is 32KB with no wait states

Figure 6-3 shows the available SRAM/cache configurations for L1D.

66AK2H14 66AK2H12 66AK2H06 L1D_Memory_Configuration_6616.gif Figure 6-3 L1D Memory Configurations

L2 Memory

The L2 memory configuration for the 66AK2Hxx device is as follows:

  • Total memory size is 8192KB
  • Each CorePac contains 1024KB of memory
  • Local starting address for each CorePac is 0080 0000h

L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C66x CorePac. Figure 6-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

66AK2H14 66AK2H12 66AK2H06 L2_Memory_Configuration_1024.gif Figure 6-4 L2 Memory Configurations

Global addresses that are accessible to all masters in the system are in all memory local to the processors. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for CorePac0's L2 memory. CorePac0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the C66x CorePacs as their own L2 base addresses. For CorePac0, as mentioned, this is equivalent to 0x10800000, for CorePac1 this is equivalent to 0x11800000, and for CorePac2 this is equivalent to 0x12800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run time by a particular CorePac should always use the global address only.

Multicore Shared Memory SRAM

The MSM SRAM configuration for the 66AK2Hxx device is as follows:

  • Memory size of 6144KB
  • Can be configured as shared L2 or shared L3 memory
  • Allows extension of external addresses from 2GB up to 8GB
  • Has built-in memory protection features

The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the KeyStone Architecture Multicore Shared Memory Controller (MSMC) User's Guide.

L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (32KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, nonsecure access.

The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify only whether memory pages are locally or globally accessible.

The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 6-1.

Table 6-1 Available Memory Page Protection Schemes

0 0 No access to memory page is permitted.
0 1 Only direct access by DSP is permitted.
1 0 Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1 1 All accesses permitted.
x = 0, 1, 2, 3, 4, 5

Faults are handled by software in an interrupt (or an exception, programmable within the CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:

  • Block the access — reads return 0, writes are ignored
  • Capture the initiator in a status register — ID, address, and access type are stored
  • Signal the event to the DSP interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the TMS320C66x DSP CorePac User's Guide.

Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the bandwidth management control hardware:

  • Level 1 Program (L1P) SRAM/Cache
  • Level 1 Data (L1D) SRAM/Cache
  • Level 2 (L2) SRAM/Cache
  • Memory-mapped registers configuration bus

The priority level for operations initiated within the C66x CorePac are declared through registers in the CorePac. These operations are:

  • DSP-initiated transfers
  • User-programmed cache coherency operations
  • IDMA-initiated transfers

The priority level for operations initiated outside the CorePac by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC). System peripherals with no fields in PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the CorePac can be found in the TMS320C66x DSP CorePac User's Guide.

Power-Down Control

The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down controller (PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire CorePac. These power-down features can be used to design systems for lower overall system power requirements.


The 66AK2Hxx does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C66x CorePac can be found in the TMS320C66x DSP CorePac User's Guide.

C66x CorePac Revision

The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) at address 0181 2000h. The MM_REVID register is shown in Figure 6-5 and described in Table 6-2. The C66x CorePac revision is dependent on the silicon revision being used.

Figure 6-5 CorePac Revision ID Register (MM_REVID)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-n R-n
Legend: R = Read only; R/W = Read/Write; -n = value after reset

Table 6-2 CorePac Revision ID Register (MM_REVID) Field Descriptions

Bit Name Value Description
31-16 VERSION 0009h Version of the C66x CorePac implemented on the device.
15-0 REVISION xxxxh Revision of the C66x CorePac version implemented on this device.
0000h = silicon revision 1.0
0002h = silicon revision 1.1
0003h = silicon revisions 2.0, 3.0, and 3.1

C66x CorePac Register Descriptions

See the TMS320C66x DSP CorePac User's Guide for register offsets and definitions.