SNAS279F April 2005 – July 2016 ADC084S021
The ADC084S021 is a successive-approximation analog-to-digital converter designed around a charge-redistribution digital-to-analog converter.
Figure 1 and Figure 3 for the ADC084S021 are shown in Timing Requirements. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data at DIN, the serial data input pin, is written to the control register of the ADC084S021. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when CS is high and is active when CS is low. CS thus acts as an output enable, in addition to being a start conversion input. Additionally, the device goes into a power-down state when CS is high and between continuous conversion cycles.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting with the 5th clock. If there is more than one conversion in a frame, the ADC re-enters the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK, and re-enter the hold/convert mode at the N*16+4th falling edge of SCLK, where N is an integer.
SCLK is internally gated off when CS is high. If SCLK is stopped in the low state while CS is high, the subsequent fall of CS generates a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC enters the track mode at the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the device at the DIN pin on the first 8 rising edges of SCLK after the fall of CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion after the current one. That is, the conversion that is started at the fall of CS is of the voltage at the channel that was selected when the last conversion was started. The first conversion after power up is of the first channel. See Table 1 and Table 3.
If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum tCSU and tCLH times given in Timing Requirements.
There are no power-up delays or dummy conversions required with the ADC084S021. The ADC is able to sample and convert an input to full conversion immediately following power up. The first conversion result after power up is that of IN1.
The output format of the ADC084S021 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC084S021 is VA / 256, and Figure 45 shows the ideal transfer characteristic. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of VA / 512. Other code transitions occur at steps of one LSB.
Figure 46 shows an equivalent circuit for one of the ADC084S021's input channels. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time must any input go beyond (VA + 300 mV) or
(GND − 300 mV), as these ESD diodes begin conducting, which could result in erratic operation. For this reason, these ESD diodes must not be used to clamp the input signal.
The capacitor C1 in Figure 46 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track or hold switch, which is typically 500 Ω. Capacitor C2 is the ADC084S021 sampling capacitor, which is typically 30 pF. The ADC084S021 delivers the best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC084S021 to sample AC signals. Also important when sampling dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance.
The digital output of the ADC084S021, DOUT, is limited by and cannot exceed the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS, and DIN may be asserted before VA without any latch-up risk.
The ADC084S021 has two primary modes of operation necessary for capturing an analog signal: track mode and hold mode. Simplified schematics of the ADC084S021 in both track and hold modes are shown in Figure 47 and Figure 48, respectively.
Figure 47 shows the ADC084S021 in track mode: switch SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC084S021 is in this state for the first three SCLK cycles after CS is brought low.
Figure 48 shows the ADC084S021 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC084S021 is in this state for the fourth through sixteenth SCLK cycles after CS is brought low.
The time when CS is low is considered a serial frame. Each of these frames must contain an integer multiple of 16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is clocked into the DIN pin to indicate the multiplexer address for the next conversion.
Table 1 shows the control register bits for the ADC084S021.
|BIT 7 (MSB)||BIT 6||BIT 5||BIT 4||BIT 3||BIT 2||BIT 1||BIT 0|
Table 2 shows the register descriptions for bit 7 through bit 0.
|7 to 6, 2 to 0||DONTC||Don't care. The value of these bits do not affect device operation.|
|5||ADD2||These three bits determine which input channel will be sampled and converted in the next track/hold cycle. The mapping between codes and channels is shown in Table 3.|
Table 3 shows the input channel selection for register bits ADD2, ADD1, and ADD0.