The ADC084S021 is fully powered up whenever CS is low, and fully powered down when CS is high, with one exception: the ADC084S021 automatically enters power-down mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Timing Requirements).

The ADC084S021 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The ADC084S021 performs conversions continuously as long as CS is held low.

10.1 Power Management

When the ADC084S021 is operated continuously in normal mode, the maximum throughput is f_SCLK/16. Performance remains as stated in Electrical Characteristics as long as the SCLK frequency remains within the range stated at the heading of those tables. Throughput may be traded for power consumption by running f_SCLK at its maximum 3.2 MHz and performing fewer conversions per unit time, putting the ADC084S021 into shutdown mode between conversions. See Figure 44 in Typical Characteristics. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Generally, the user places the part into normal mode and then put the part back into shutdown mode. Note that the curve of Figure 44 is nearly linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.

10.2 Noise Considerations

The charging of any output load capacitance requires current from the power supply, V_A. The current pulses required from the supply to charge the output capacitance causes voltage variations of the supply voltage. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate. Load discharge currents causes ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger is the output capacitance, the more current flows through the die supply line and substrate, causing more noise to be coupled into the analog channel and degrading noise performance.

To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and improve noise performance.