The receiving device starts the initial lane
alignment process by deasserting the
SYNC signal. When a logic low
state is detected on the
SYNC input, the ADC starts transmitting
comma characters (K28.5) to establish the code group synchronization, as shown in
Figure 6-42. When synchronization is completed, the receiving device reasserts
the
SYNC signal and the ADC starts the initial lane alignment
sequence with the next local multi-frame clock (LMFC) boundary. The ADC transmits four
multi-frames, each containing K frame (K is SPI programmable). Each of the multi-frames
contains the frame start and frame end symbols. The second multi-frame also contains the
JESD204B link configuration data.