SBAS988 November   2023 ADC34RF55

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 5.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Bandwidth and Full-Scale
        2. 6.3.1.2 Input Imbalance
        3. 6.3.1.3 Over Range Indication
        4. 6.3.1.4 Analog out-of-band dither
      2. 6.3.2 Sampling Clock Input
      3. 6.3.3 ADC Foreground Calibration
        1. 6.3.3.1 Calibration Control
        2. 6.3.3.2 ADC Switch
        3. 6.3.3.3 Calibration Configuration
      4. 6.3.4 SYSREF
        1. 6.3.4.1 SYSREF Capture Detection
      5. 6.3.5 Decimation Filter
        1. 6.3.5.1 Decimation Filter Response
        2. 6.3.5.2 Decimation Filter Configuration
        3. 6.3.5.3 20-bit Output Mode
        4. 6.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 6.3.5.5 NCO Frequency Programming Using the SPI Interface
        6. 6.3.5.6 Fast Frequency Hopping
          1. 6.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 6.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 6.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 6.3.6.1.1 SYNC Signal
        2. 6.3.6.2 JESD204B Frame Assembly
          1. 6.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 6.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 6.3.6.2.3 JESD204B Frame Assembly with Complex Decimation - Single Band
          4. 6.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 6.3.6.3 SERDES Output MUX
      7. 6.3.7 Test Pattern
        1. 6.3.7.1 Transport Layer
        2. 6.3.7.2 Link Layer
        3. 6.3.7.3 Internal Capture Memory Buffer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Bypass Mode
      2. 6.4.2 Digital Averaging
    5. 6.5 Programming
      1. 6.5.1 GPIO Pin Control
      2. 6.5.2 Configuration using the SPI interface
        1. 6.5.2.1 Register Write
        2. 6.5.2.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Detailed Register Description
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Wideband RF Sampling Receiver
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Clocking
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Sampling Clock
      4. 7.2.4 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Initial Device Configuration After Power-Up
        1. 7.3.1.1  STEP 1: RESET
        2. 7.3.1.2  STEP 2: Device Configuration
        3. 7.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 7.3.1.4  STEP 4: SYSREF Synchronization
        5. 7.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 7.3.1.6  STEP 6: Analog Trim Settings
        7. 7.3.1.7  STEP 7: Calibration Configuration
        8. 7.3.1.8  STEP 8: SYSREF Synchronization
        9. 7.3.1.9  STEP 9: Run Power up Calibration
        10. 7.3.1.10 Step 10: JESD Interface Synchronization
        11. 7.3.1.11 Step 11: NCO Configuration
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band

Table 6-35 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the ADC34RF55 with complex decimation (dual band). The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes are shown in Table 6-39, Table 6-37 and Table 6-38.

Table 6-35 JESD Mode Options: Decimation - Dual Band
DECIMATION
SETTING D
(complex)		LMFSMIN FS
(Gsps)		MAX FS
(Gsps)		RATIO
[fSERDES/(FS/D)]
/8 8 16 4 1 0.52.6 40
/16 3.0
/32
/640.8
/1281.6
/8 4 16 8 1 0.51.3 80
/162.6
/32 3.0
/64
/1280.8
/16 2 16 16 1 0.51.3 160
/322.6
/64 3.0
/128
/32 1 16 32 1 0.51.3 320
/642.6
/128 3.0
Table 6-36 JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE		LMFS = 8-16-4-1LMFS = 4-16-8-1
DOUT0A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]
DOUT1A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]		B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]
DOUT2B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		C1I0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]		C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]
DOUT3B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]		D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]		D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
DOUT4CI0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]
DOUT5C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]
DOUT6D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]
DOUT7D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
Table 6-37 JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE		LMFS = 2-16-16-1
DOUT0A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]		B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]
DOUT1C1I0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]		C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]		D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]		D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
Table 6-38 JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE		LMFS = 1-16-32-1
DOUT0A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]		B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]		...
...C1I0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]		C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]		D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]		D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7