SBASAP4 April   2025 ADC3664-EP , ADC3664-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Analog Input Termination and DC Bias
            1. 7.3.1.2.2.1 AC-Coupling
            2. 7.3.1.2.2.2 DC-Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF/CTRL)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Bit Mapper
          1. 7.3.5.2.1 2-Wire Mode
          2. 7.3.5.2.2 1-Wire Mode
          3. 7.3.5.2.3 ½-Wire Mode
        3. 7.3.5.3 Output Interface and Mode Configuration
          1. 7.3.5.3.1 Configuration Example
        4. 7.3.5.4 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal operation
      2. 7.4.2 Power Down Options
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RSB|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4.5 Decimation Filter

The ADC3664-xEP supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of approximately 80% and a stopband rejection of at least 85dB. Table 7-2 gives an overview of the pass-band bandwidth of the different decimation settings with respect to ADC sampling rate FS. In real decimation mode, the output bandwidth is half of the complex bandwidth.

Table 7-2 Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX DECIMATIONDECIMATION SETTING NOUTPUT RATEOUTPUT BANDWIDTHOUTPUT RATE
(FS = 125MSPS)		OUTPUT BANDWIDTH
(FS = 125MSPS)
Complex2FS / 2 complex0.8 × FS / 262.5MSPS complex50MHz
4FS / 4 complex0.8 × FS / 431.25MSPS complex25MHz
8FS / 8 complex0.8 × FS / 815.625MSPS complex12.5MHz
16FS / 16 complex0.8 × FS / 167.8125MSPS complex6.25MHz
32FS / 32 complex0.8 × FS / 323.90625MSPS complex3.125MHz
Real2FS / 2 real0.4 × FS / 262.5MSPS25MHz
4FS / 4 real0.4 × FS / 431.25MSPS12.5MHz
8FS / 8 real0.4 × FS / 815.625MSPS6.25MHz
16FS / 16 real0.4 × FS / 167.8125MSPS3.125MHz
32FS / 32 real0.4 × FS / 323.90625MSPS1.5625MHz

The decimation filter responses normalized tot he ADC sampling clock frequency are illustrated in Figure 7-21 to Figure 7-30. They are interpreted as follows:

Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 7-20. The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.

For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS / 8 or 0.125 × FS. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at 0.25 × FS and 0.5 × FS. The stop-band attenuation is greater than 85dB.

ADC3664-SEP ADC3664-EP Interpretation of the Decimation Filter PlotsFigure 7-20 Interpretation of the Decimation Filter Plots
ADC3664-SEP ADC3664-EP Decimation by 2 complex frequency responseFigure 7-21 Decimation by 2 complex frequency response
ADC3664-SEP ADC3664-EP Decimation by 4 complex frequency responseFigure 7-23 Decimation by 4 complex frequency response
ADC3664-SEP ADC3664-EP Decimation by 8 complex frequency responseFigure 7-25 Decimation by 8 complex frequency response
ADC3664-SEP ADC3664-EP Decimation by 16 complex frequency responseFigure 7-27 Decimation by 16 complex frequency response
ADC3664-SEP ADC3664-EP Decimation by 32 complex frequency responseFigure 7-29 Decimation by 32 complex frequency response
ADC3664-SEP ADC3664-EP Decimation by 2 complex passband ripple responseFigure 7-22 Decimation by 2 complex passband ripple response
ADC3664-SEP ADC3664-EP Decimation by 4 complex passband ripple responseFigure 7-24 Decimation by 4 complex passband ripple response
ADC3664-SEP ADC3664-EP Decimation by 8 complex passband ripple responseFigure 7-26 Decimation by 8 complex passband ripple response
ADC3664-SEP ADC3664-EP Decimation by 16 complex passband ripple responseFigure 7-28 Decimation by 16 complex passband ripple response
ADC3664-SEP ADC3664-EP Decimation by 32 complex passband ripple responseFigure 7-30 Decimation by 32 complex passband ripple response