SLVSMZ0 September   2026 ADS111S02

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Voltage Reference
      3. 8.3.3 Oscillator
      4. 8.3.4 Output Data Rate and Conversion Time
      5. 8.3.5 Low-Noise PGA
      6. 8.3.6 Temperature Sensor
        1. 8.3.6.1 12-Bit Temperature Data Format (ADS101S02)
        2. 8.3.6.2 Converting from Digital Codes to Temperature, 12-Bit Temperature Sensor Data
        3. 8.3.6.3 14-Bit Temperature Data Format (ADS101S02)
        4. 8.3.6.4 Converting from Digital Codes to Temperature, 14-Bit Temperature Sensor Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous-Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface (SPI)
      2. 8.5.2 Chip Select (CS)
      3. 8.5.3 Serial Clock (SCLK)
      4. 8.5.4 Data Input (DIN)
      5. 8.5.5 Data Output and Data Ready (DOUT/DRDY)
      6. 8.5.6 Data Retrieval and Device Configuration
        1. 8.5.6.1 32-Bit Data Transmission Cycle
        2. 8.5.6.2 16-Bit Data Transmission Cycle
    6. 8.6 Conversion Data Format
  10. 9 Register Maps
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Connecting Multiple Devices
      3. 10.1.3 Single-Ended Inputs
      4. 10.1.4 Unused Inputs and Outputs
      5. 10.1.5 Input Protection
      6. 10.1.6 Analog Input Filtering
      7. 10.1.7 Duty Cycling For Low Power
      8. 10.1.8 Pseudo Code Example
    2. 10.2 Typical Applications
      1. 10.2.1 K-Type Thermocouple with Thermistor Cold-Junction Compensation
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 Server Card System Monitoring Application
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Supply Sequencing
      2. 10.3.2 Power-Supply Decoupling
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.5 Data Output and Data Ready (DOUT/DRDY)

DOUT/DRDY is a dual-function output pin. During SPI communication, conversion and register data are shifted out on the rising edge of SCLK. This pin also functions as a data-ready indicator, that transitions low when a conversion completes and new data are available. In multi-device systems where conversion completion must be monitored across multiple devices on the SPI bus, periodically lower the CS to poll the DOUT/DRDY status of the device. This method allows the system to identify which device has completed a conversion without requiring dedicated interrupt lines for each device.

When operating in continuous-conversion mode, CS can be periodically pulled low to use DOUT/DRDY as a data ready signal. If no data transfer occurs, DOUT/DRDY transitions high 8µs before the next conversion completes. DOUT/DRDY can trigger a microcontroller to start reading data. This transition is shown in Figure 8-6. Complete the data transfer before DOUT/DRDY returns high, to avoid missing subsequent conversion results.

ADS101S02 ADS111S02 DOUT/DRDY Behavior Without Data Retrieval in Continuous-Conversion Mode With CS Held Low
(1) In continuous-conversion mode CS can be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available.
Figure 8-6 DOUT/DRDY Behavior Without Data Retrieval in Continuous-Conversion Mode With CS Held Low

When CS is high, DOUT/DRDY is configured by default with a weak internal pullup resistor. This feature reduces the risk of DOUT/DRDY floating near midsupply and causing leakage current in the controller. To disable this pullup resistor and configure the pin as a true high-impedance output, set PULL_UP_EN = 0b.