SLVSMZ0 September 2026 ADS111S02
ADVANCE INFORMATION
Conversion data are coded depending on the MUX[2:0] configuration. Configurations that use AINN = GND use unipolar straight binary data format, all other configurations use binary two's complement data format, MSB first (sign bit). Table 8-5 shows the conversion data format based on the MUX[2:0] settings.
| MUX[2:0] | AINP | AINN | CONVERSION DATA FORMAT |
|---|---|---|---|
| 000b | AIN0 | AIN1 | Binary Two's Compliment |
| 001b | AIN0 | AIN3 | Binary Two's Compliment |
| 010b | AIN1 | AIN3 | Binary Two's Compliment |
| 011b | AIN2 | AIN3 | Binary Two's Compliment |
| 100b | AIN0 | GND | Unipolar Straight Binary |
| 101b | AIN1 | GND | Unipolar Straight Binary |
| 110b | AIN2 | GND | Unipolar Straight Binary |
| 111b | AIN3 | GND | Unipolar Straight Binary |
Table 8-6 and Table 8-7 show the output coding for the 12- and 16-bit devices, respectively. In binary two's-complement format, the conversion data clips to positive and negative full-scale code values when the input signal exceeds the respective positive and negative full-scale values. In unipolar straight binary format, conversion data clips to full-scale or zero code values when the input signal exceeds full-scale or is below zero, respectively.
| DIFFERENTIAL INPUT VOLTAGE (V) | IDEAL OUTPUT CODE(1) | |
|---|---|---|
| BINARY TWO'S-COMPLEMENT FORMAT | UNIPOLAR STRAIGHT BINARY FORMAT | |
| ≥ FSR × (212 – 1) / 212 | 7FFh | FFFh |
| ≥ FSR × (211 – 1) / 211 | FFEh | |
| FSR / 211 | 001h | 002h |
| 0 | 000h | 000h |
| –FSR / 211 | FFFh | |
| –FSR × (211 – 1) / 211 | 801h | |
| ≤ –FSR | 800h | |
| DIFFERENTIAL INPUT VOLTAGE (V) | IDEAL OUTPUT CODE(1) | |
|---|---|---|
| BINARY TWO'S-COMPLEMENT FORMAT | UNIPOLAR STRAIGHT BINARY FORMAT | |
| ≥ FSR × (216 – 1) / 216 | 7FFFh | FFFFh |
| ≥ FSR × (215 – 1) / 215 | FFFEh | |
| FSR / 215 | 0001h | 0002h |
| 0 | 0000h | 0000h |
| –FSR / 215 | FFFFh | |
| –FSR × (215 – 1) / 215 | 8001h | |
| ≤ –FSR | 8000h | |