SBASAH6A March 2022 – October 2022 ADS117L11
PRODUCTION DATA
The device is reset through SPI operation by writing 01011000b to the CONTROL register. Writing any other value to this register does not result in reset. In 4-wire SPI mode, reset takes effect at the end of the frame at the time CS is taken high. In 3-wire SPI mode, reset takes effect on the last falling edge of SCLK of the register write operation. Reset in 3-wire SPI mode requires that the SPI is synchronized to the SPI host. If SPI synchronization is not assured, use the pattern described in the Section 8.4.5.3 section to reset the device. Reset can be validated by checking the POR_FLAG of the STATUS register.