SBASBA2 October   2026 ADS125R14

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ADS125R11 and ADS125R14 Recommended Operating Conditions
    4. 6.4 ADS125R13 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
  8. 7 Timing Diagrams
  9. 8 Typical Characteristics
  10. 9 Parameter Measurement Information
    1. 9.1 Detailed Measurements
      1. 9.1.1 Offset and Gain Error
      2. 9.1.2 Offset and Gain Drift Measurement
      3. 9.1.3 NMRR
      4. 9.1.4 CMRR
      5. 9.1.5 PSRR
      6. 9.1.6 INL
      7. 9.1.7 THD
    2. 9.2 Noise Performance
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1 Analog Inputs
      2. 10.3.2 Sensor Detect Current Sources
      3. 10.3.3 Input Buffer
      4. 10.3.4 Delta-Sigma Modulator
        1. 10.3.4.1 PGA Gain
      5. 10.3.5 Reference Voltage
      6. 10.3.6 Digital Filter
        1. 10.3.6.1 Frequency Response
        2. 10.3.6.2 Settling Time
      7. 10.3.7 GENERAL-PURPOSE I/O (D0D3)
      8. 10.3.8 D0/CLKOUT Pin
      9. 10.3.9 D1/ERROR Pin
    4. 10.4 Device Functional Modes
      1. 10.4.1 Speed Modes
      2. 10.4.2 Clock Operation
      3. 10.4.3 Synchronization
        1. 10.4.3.1 Cycling Through the Inputs
        2. 10.4.3.2 One-Shot Conversions
        3. 10.4.3.3 Continuous Conversions
        4. 10.4.3.4 Delay Time
        5. 10.4.3.5 Conversion Restart after Register Change
      4. 10.4.4 Standby Mode
      5. 10.4.5 Power-Down Mode
      6. 10.4.6 Reset
        1. 10.4.6.1 Power-on Reset
      7. 10.4.7 Autozero Mode
      8. 10.4.8 Calibration
        1. 10.4.8.1 Calibration Commands
          1. 10.4.8.1.1 Self-Calibration
          2. 10.4.8.1.2 System-Calibration
          3. 10.4.8.1.3 Calibration Time
    5. 10.5 Programming
      1. 10.5.1 Serial Interface (SPI)
        1. 10.5.1.1  Chip Select (CS)
        2. 10.5.1.2  Serial Clock (SCLK)
        3. 10.5.1.3  Data Input (DIN)
        4. 10.5.1.4  Data Output (DOUT)
        5. 10.5.1.5  Data Ready (DRDY)
        6. 10.5.1.6  Data Output/Data Ready (DOUT/DRDY)
        7. 10.5.1.7  Conversion Data Format
        8. 10.5.1.8  Reading Conversion Data
          1. 10.5.1.8.1 Read Data Continuous Mode (RDATAC)
          2. 10.5.1.8.2 Stop Read Data Continuous Mode (SDATAC)
        9. 10.5.1.9  SPI CRC
        10. 10.5.1.10 Register CRC
      2. 10.5.2 Device Commands
        1. 10.5.2.1  RDATA: Read Conversion Data
        2. 10.5.2.2  RDATAC: Set Read Data Continuous Mode
        3. 10.5.2.3  SDATAC: Stop Read Data Continuous
        4. 10.5.2.4  RREG: Read From Registers
        5. 10.5.2.5  WREG: Write to Registers
        6. 10.5.2.6  SELFCAL, SELFOCAL, SELFGCAL, SYSOCAL, SYSGCAL: Calibration Commands
        7. 10.5.2.7  SYNC: Synchronize A/D Conversion
        8. 10.5.2.8  STBY: Standby Mode
        9. 10.5.2.9  PWDN: Power-down
        10. 10.5.2.10 RESET: ADC Reset
  12. 11Registers
    1. 11.1 Register Summary Table
      1. 11.1.1  STATUS Register (Page = 0h, Address = 0h) [Reset = 01h]
      2. 11.1.2  MUX Register (Page = 0h, Address = 1h) [Reset = 01h]
      3. 11.1.3  ADCON Register (Page = 0h, Address = 2h) [Reset = 20h]
      4. 11.1.4  DRATE Register (Page = 0h, Address = 3h) [Reset = F0h]
      5. 11.1.5  GPIO Register (Page = 0h, Address = 4h) [Reset = E0h]
      6. 11.1.6  OFC0 Register (Page = 0h, Address = 5h) [Reset = 00h]
      7. 11.1.7  OFC1 Register (Page = 0h, Address = 6h) [Reset = 00h]
      8. 11.1.8  OFC2 Register (Page = 0h, Address = 7h) [Reset = 00h]
      9. 11.1.9  FSC0 Register (Page = 0h, Address = 8h) [Reset = 00h]
      10. 11.1.10 FSC1 Register (Page = 0h, Address = 9h) [Reset = 00h]
      11. 11.1.11 FSC2 Register (Page = 0h, Address = Ah) [Reset = 40h]
      12. 11.1.12 PAGE_PTR Register (Page = 0h, Address = Fh) [Reset = 00h]
      13. 11.1.13 CONFIG0 Register (Page = 1h, Address = 0h) [Reset = 14h]
      14. 11.1.14 CONFIG1 Register (Page = 1h, Address = 1h) [Reset = 88h]
      15. 11.1.15 CONFIG2 Register (Page = 1h, Address = 2h) [Reset = 40h]
      16. 11.1.16 CRC Register (Page = 1h, Address = 3h) [Reset = 00h]
      17. 11.1.17 STATUS1 Register (Page = 1h, Address = 4h) [Reset = 07h]
      18. 11.1.18 DEV_ID Register (Page = 1h, Address = 5h) [Reset = XXh]
      19. 11.1.19 REV_ID Register (Page = 1h, Address = 6h) [Reset = XXh]
      20. 11.1.20 PAGE_PTR Register (Page = 1h, Address = Fh) [Reset = 00h]
  13. 12Application and Implementation
    1. 12.1 Application Information
      1. 12.1.1 Analog Inputs
      2. 12.1.2 Reference Inputs
      3. 12.1.3 Clock Options
      4. 12.1.4 SPI Serial Interface
      5. 12.1.5 Simultaneous Sampling
    2. 12.2 Initialization Setup
      1. 12.2.1 Initialization Procedure
    3. 12.3 Typical Applications
      1. 12.3.1 Resistive Bridge Sensor
        1. 12.3.1.1 Design Requirements
        2. 12.3.1.2 Detailed Design Procedure
        3. 12.3.1.3 Application Data
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 15.1 Tape and Reel Information
    3. 15.2 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|28
Thermal pad, mechanical data (Package|Pins)

10.5.1.7 Conversion Data Format

Conversion data are programmable to 16-bit, 24-bit or 32-bit output data formats. 32-bit data format provides 28 active bits and is useful for slow sample rates where the quantization error of 24-bit data can limit resolution. The 16-bit data format reduces data transfer time for faster sample rates where 24-bit resolution is not always necessary. The output data format is programmed by the FORMAT[1:0] bits (default = 24 bits).

Conversion data are coded in either two's complement, to represent positive and negative differential signals (bipolar input signals), or coded in straight binary to represent only positive differential signals (unipolar input signals). The RANGE bit selects the input range (default = bipolar). Table 10-19 shows the code values for bipolar input range and Table 10-20 shows the code values for unipolar input range. For either bipolar and unipolar input range, conversion data clips to the minimum and maximum values to avoid code overflow when the respective minimum and maximum input ranges are exceeded.

Table 10-19 Code Values (Bipolar Input Range)
INPUT VOLTAGE (VIN)(1) 16-bit FORMAT 24-bit FORMAT 32-bit FORMAT
≥(2VREF / Gain) · (2n – 1) / 2n 7FFFh 7FFFFFh 7FFFFFF0h
(2VREF / Gain) / (2n – 1) 0001h 000001h 00000010h
0 0000h 000000h 00000000h
(–2VREF / Gain) / 2n FFFFh FFFFFFh FFFFFFF0h
≤–2VREF / Gain 8000h 800000h 80000000h
(1) n = 15 (16-bit format), n = 23 (24-bit format), n = 27 (32-bit format). Output codes are ideal values and exclude the effects of noise, INL, offset and gain errors.
Table 10-20 Code Values (Unipolar Input Range)
INPUT VOLTAGE (VIN)(1) 16-bit FORMAT 24-bit FORMAT 32-bit FORMAT
≥2VREF / Gain FFFFh FFFFFFh FFFFFFF0h
(2VREF / Gain) / 2n 0001h 000001h 00000010h
≤0 0000h 000000h 00000000h
(1) n = 16 (16-bit format), n = 24 (24-bit format), n = 28 (32-bit format). Output codes are ideal values and exclude the effects of noise, INL, offset and gain errors.