SBASAD2 November 2021 ADS130B04-Q1
The device provides conversion data for each channel at the data rate. All data are available immediately following DRDY assertion. The conversion status of all channels is available as the DRDY[3:0] bits in the STATUS register. The STATUS register content is automatically output as the response to the NULL command.
Conversion data are 16 bits. The LSBs are zero padded when operating with a 24-bit or 32-bit word size.
Data are given in binary two's complement format. Use Equation 8 to calculate the size of one code (LSB).
A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFh and a negative full-scale input (VIN ≤ –FSR = –1.2 / Gain) produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale.
Table 8-8 summarizes the ideal output codes for different input signals.
(VIN = VAINP – VAINN)
|IDEAL OUTPUT CODE|
|≥ FSR (215 – 1) / 215||7FFFh|
|FSR / 215||0001h|
|–FSR / 215||FFFFh|
Figure 8-17 shows the mapping of the analog input signal to the output codes.