SBASAD2 November 2021 ADS130B04-Q1
The ADS130B04-Q1 features an SPI timeout as a means to recover SPI communication, especially in situations where CS is permanently tied low. Enable the SPI timeout using the TIMEOUT bit in the MODE register. When enabled, the entire SPI frame (first SCLK to last SCLK) must complete in 215 MCLK cycles, otherwise the SPI logic will reset. When a timeout happens the device starts interpreting the data starting with the next SCLK as a new SPI frame.