SBAS561C June   2012  â€“ January 2017 ADS131E04 , ADS131E06 , ADS131E08

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Electromagnetic Interference (EMI) Filter
      2. 9.3.2  Input Multiplexer
        1. 9.3.2.1 Device Noise Measurements
        2. 9.3.2.2 Test Signals (TestP and TestN)
        3. 9.3.2.3 Temperature Sensor (TempP, TempN)
        4. 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)
      3. 9.3.3  Analog Input
      4. 9.3.4  PGA Settings and Input Range
        1. 9.3.4.1 Input Common-Mode Range
      5. 9.3.5  ΔΣ Modulator
      6. 9.3.6  Clock
      7. 9.3.7  Digital Decimation Filter
      8. 9.3.8  Voltage Reference
      9. 9.3.9  Input Out-of-Range Detection
      10. 9.3.10 General-Purpose Digital I/O (GPIO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
        2. 9.4.1.2 Input Signal Step
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Continuous Conversion Mode
      5. 9.4.5 Data Retrieval
        1. 9.4.5.1 Data Ready (DRDY)
        2. 9.4.5.2 Reading Back Data
        3. 9.4.5.3 Status Word
        4. 9.4.5.4 Readback Length
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multibyte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  OFFSETCAL: Channel Offset Calibration
        8. 9.5.3.8  RDATAC: Start Read Data Continuous Mode
        9. 9.5.3.9  SDATAC: Stop Read Data Continuous Mode
        10. 9.5.3.10 RDATA: Read Data
        11. 9.5.3.11 RREG: Read from Register
        12. 9.5.3.12 WREG: Write to Register
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = xxh]
        2. 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h]
        3. 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = E0h]
        4. 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = 40]
        5. 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]
        6. 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]
        7. 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]
        8. 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]
        9. 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device Up for Basic Data Capture
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 Synchronizing Multiple Devices
        2. 10.1.3.2 Standard Configuration
        3. 10.1.3.3 Daisy-Chain Configuration
      4. 10.1.4 Power Monitoring Specific Applications
      5. 10.1.5 Current Sensing
      6. 10.1.6 Voltage Sensing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Timing
    2. 11.2 Recommended External Capacitor Values
    3. 11.3 Device Connections for Unipolar Power Supplies
    4. 11.4 Device Connections for Bipolar Power Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PAG Package
64-Pin TQFP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD 19, 21, 22, 56, 59 Supply Analog supply. Connect a 1-µF (or larger) capacitor to AVSS for each AVDD pin.
AVDD1 54 Supply Charge pump analog supply. Connect a 1-µF (or larger) capacitor to AVSS1.
AVSS 20, 23, 32, 57, 58 Supply Analog ground
AVSS1 53 Supply Charge pump analog ground
CS 39 Digital input Chip select; active low
CLK 37 Digital input Master clock input. Connect to DGND if unused.
CLKSEL 52 Digital input Master clock select
DAISY_IN 41 Digital input Daisy-chain input. Connect to DGND if unused.
DGND 33, 49, 51 Supply Digital ground
DIN 34 Digital input Serial data input
DOUT 43 Digital output Serial data output
DRDY 47 Digital output Data ready; active low. Connect to DGND with a 10-kΩ resistor if unused.
DVDD 48, 50 Supply Digital core power supply. Connect a 1-µF (or larger) capacitor to DGND for each DVDD pin.
GPIO1 42 Digital input/output General-purpose input/output pin 1. Connect to DGND with a 10-kΩ resistor if unused.
GPIO2 44 Digital input/output General-purpose input/output pin 2. Connect to DGND with a 10-kΩ resistor if unused.
GPIO3 45 Digital input/output General-purpose input/output pin 3. Connect to DGND with a 10-kΩ resistor if unused.
GPIO4 46 Digital input/output General-purpose input/output pin 4. Connect to DGND with a 10-kΩ resistor if unused.
IN1N(1) 15 Analog input Negative analog input 1
IN1P(1) 16 Analog input Positive analog input 1
IN2N(1) 13 Analog input Negative analog input 2
IN2P(1) 14 Analog input Positive analog input 2
IN3N(1) 11 Analog input Negative analog input 3
IN3P(1) 12 Analog input Positive analog input 3
IN4N(1) 9 Analog input Negative analog input 4
IN4P(1) 10 Analog input Positive analog input 4
IN5N(1) 7 Analog input Negative analog input 5 (ADS131E06 and ADS131E08 only)
IN5P(1) 8 Analog input Positive analog input 5 (ADS131E06 and ADS131E08 only)
IN6N(1) 5 Analog input Negative analog input 6 (ADS131E06 and ADS131E08 only)
IN6P(1) 6 Analog input Positive analog input 6 (ADS131E06 and ADS131E08 only)
IN7N(1) 3 Analog input Negative analog input 7 (ADS131E08 only)
IN7P(1) 4 Analog input Positive analog input 7 (ADS131E08 only)
IN8N(1) 1 Analog input Negative analog input 8 (ADS131E08 only)
IN8P(1) 2 Analog input Positive analog input 8 (ADS131E08 only)
NC 27, 29, 62, 64 — No connection, leave floating. Can be connected to AVDD or AVSS with a 10-kΩ or higher resistor.
OPAMPN 61 Analog input Op amp inverting input; leave floating if unused and power-down the op amp.
OPAMPP 60 Analog input Op amp noninverting input; leave floating if unused and power-down the op amp.
OPAMPOUT 63 Analog output Op amp output; leave floating if unused and power-down the op amp.
PWDN 35 Digital input Power-down; active low
RESET 36 Digital input System reset; active low
RESV1 31 Digital input Reserved for future use. Connect directly to DGND.
SCLK 40 Digital input Serial clock input
START 38 Digital input Start conversion
TESTN 18 Analog input/output Test signal, negative pin. See the Unused Inputs and Outputs section for unused pins.
TESTP 17 Analog input/output Test signal, positive pin. See the Unused Inputs and Outputs section for unused pins.
VCAP1 28 Analog output Analog bypass capacitor. Connect a 22-µF capacitor to AVSS.
VCAP2 30 Analog output Analog bypass capacitor. Connect a 1-µF capacitor to AVSS.
VCAP3 55 Analog output Analog bypass capacitor. Connect a parallel combination of 1-µF and 0.1-µF capacitors to AVSS.
VCAP4 26 Analog output Analog bypass capacitor. Connect a 1-µF capacitor to AVSS.
VREFN 25 Analog input Negative reference voltage. Connect to AVSS
VREFP 24 Analog input/output Positive reference voltage. Connect a minimum 10-µF capacitor to VREFN.
(1) Connect any unused or powered-down analog input pins to AVDD.