SBAS561C June   2012  – January 2017 ADS131E04 , ADS131E06 , ADS131E08

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Electromagnetic Interference (EMI) Filter
      2. 9.3.2  Input Multiplexer
        1. 9.3.2.1 Device Noise Measurements
        2. 9.3.2.2 Test Signals (TestP and TestN)
        3. 9.3.2.3 Temperature Sensor (TempP, TempN)
        4. 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)
      3. 9.3.3  Analog Input
      4. 9.3.4  PGA Settings and Input Range
        1. 9.3.4.1 Input Common-Mode Range
      5. 9.3.5  ΔΣ Modulator
      6. 9.3.6  Clock
      7. 9.3.7  Digital Decimation Filter
      8. 9.3.8  Voltage Reference
      9. 9.3.9  Input Out-of-Range Detection
      10. 9.3.10 General-Purpose Digital I/O (GPIO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
        2. 9.4.1.2 Input Signal Step
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Continuous Conversion Mode
      5. 9.4.5 Data Retrieval
        1. 9.4.5.1 Data Ready (DRDY)
        2. 9.4.5.2 Reading Back Data
        3. 9.4.5.3 Status Word
        4. 9.4.5.4 Readback Length
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multibyte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  OFFSETCAL: Channel Offset Calibration
        8. 9.5.3.8  RDATAC: Start Read Data Continuous Mode
        9. 9.5.3.9  SDATAC: Stop Read Data Continuous Mode
        10. 9.5.3.10 RDATA: Read Data
        11. 9.5.3.11 RREG: Read from Register
        12. 9.5.3.12 WREG: Write to Register
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = xxh]
        2. 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h]
        3. 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = E0h]
        4. 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = 40]
        5. 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]
        6. 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]
        7. 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]
        8. 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]
        9. 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device Up for Basic Data Capture
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 Synchronizing Multiple Devices
        2. 10.1.3.2 Standard Configuration
        3. 10.1.3.3 Daisy-Chain Configuration
      4. 10.1.4 Power Monitoring Specific Applications
      5. 10.1.5 Current Sensing
      6. 10.1.6 Voltage Sensing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Timing
    2. 11.2 Recommended External Capacitor Values
    3. 11.3 Device Connections for Unipolar Power Supplies
    4. 11.4 Device Connections for Bipolar Power Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Power Supply Recommendations

11.1 Power-Up Timing

Before device power up, all digital and analog inputs must be low. At the time of power up, keep all of these signals low until the power supplies have stabilized, as shown in Figure 65.

Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a reset pulse using either the RESET pin or RESET command to initialize the digital portion of the chip. Issue the reset after tPOR or after the VCAP1 voltage is greater than 1.1 V, whichever time is longer. Note that:

  • tPOR is described in Table 22.
  • The VCAP1 pin charge time is set by the RC time constant set by the capacitor value on VCAP1; see Figure 28.

After releasing RESET, the configuration registers must be programmed (see the CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h] subsection of the Register Map section for details) to the desired settings. The power-up sequence timing is shown in Table 22.

ADS131E04 ADS131E06 ADS131E08 POR_timingdiagram_sbas459.gif
1. Timing to reset pulse is tPOR or after tBG, whichever is longer.
2. When using an external clock, tPOR timing does not start until CLK is present and valid.
Figure 65. Power-Up Timing Diagram

Table 22. Timing Requirements for Figure 65

MIN MAX UNIT
tPOR Wait after power up until reset 218 tCLK
tRST Reset low duration 1 tCLK

11.2 Recommended External Capacitor Values

The ADS131E0x power-up time is set by the time required for the critical voltage nodes to settle to their final values. The analog supplies (AVDD and AVSS), digital supply (DVDD), and internal node voltages (VCAPx pins) must be up and stable when the data converter samples are taken to ensure performance. The combined current sourcing capability of the supplies and size of the bypass capacitors dictate the ramp rate of AVDD, AVSS, and DVDD. The VCAPx voltages are charged internally using the supply voltages. Table 23 lists the internal node voltages, their function, and recommended capacitor values to optimize the power-up time.

Table 23. Recommended External Capacitor Values

PIN FUNCTION RECOMMENDED CAPACITOR VALUE
NAME NO.
VCAP1 28 Band-gap voltage for the ADC 22 µF to AVSS
VCAP2 30 Modulator common-mode 1 µF to AVSS
VCAP3 55 PGA charge pump 0.1 µF || 1 µF to AVSS
VCAP4 26 Reference common-mode 1 µF to AVSS
VREFP 24 Reference voltage after the internal buffer 0.1 µF || 10 µF to AVSS
AVDD 19, 21, 22, 56, 59 Analog supply 0.1 µF || 1 µF each to AVSS
AVDD1 54 Internal PGA charge pump analog supply 0.1 µF || 1 µF to AVSS1
DVDD 48, 50 Digital supply 0.1 µF || 1 µF each to DGND

11.3 Device Connections for Unipolar Power Supplies

Figure 66 shows the ADS131E0x connected to a unipolar supply. In this example, the analog supply (AVDD) is referenced to the analog ground (AVSS) and the digital supply (DVDD) is referenced to the digital ground (DGND). The ADS131E0x supports an analog supply range of AVDD = 2.7 V to 5.25 V when operated in unipolar supply mode.

ADS131E04 ADS131E06 ADS131E08 ai_single_supply_bas561.gif

NOTE:

Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible.
Figure 66. Unipolar Power Supply Operation

11.4 Device Connections for Bipolar Power Supplies

Figure 67 shows the ADS131E0x connected to a bipolar supply. In this example, the analog supply (AVDD) is referenced to the analog ground (AVSS) and the digital supply (DVDD) is referenced to the digital ground (DGND). The ADS131E0x supports an analog supply range of AVDD and AVSS = ±1.5 V to ±2.5 V when operated in bipolar supply mode.

ADS131E04 ADS131E06 ADS131E08 ai_bipolar_supply_bas561.gif

NOTE:

Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible.
Figure 67. Bipolar Power Supply Operation