SBAS561 Data sheet

SBAS561C June 2012 – January 2017 ADS131E04 , ADS131E06 , ADS131E08

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PAG|64
- MTQF006A

Thermal pad, mechanical data (Package|Pins)

PAG|64
- QFND323A

Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Power-supply voltage	AVDD to AVSS	–0.3	5.5	V
	AVSS to DGND	–3	0.2
	DVDD to DGND	–0.3	3.9
Analog input voltage	Analog input to AVSS	AVSS – 0.3	AVDD + 0.3	V
Digital input voltage	Digital input to DVDD	DGND – 0.3	DVDD + 0.3	V
Input current	Momentary	–100	100	mA
Input current	Continuous, all other pins except power-supply pins	–10	10	mA
Temperature	Junction, T_J		150	°C
Temperature	Storage, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
POWER SUPPLY
AVDD	Analog power supply	AVDD to AVSS	2.7	5.0	5.25	V
DVDD	Digital power supply	DVDD to DGND	1.7	1.8	3.6	V
	Analog to digital supply	AVDD to DVDD	–2.1		3.6	V
ANALOG INPUTS
V_IN	Differential input voltage	V_IN = V_(INxP) – V_(INxN)	–V_REF / Gain		V_REF / Gain	V
V_CM	Common-mode input voltage	V_CM = (V_(INxP) – V_(INxN)) / 2	See the Input Common-Mode Range section			V
VOLTAGE REFERENCE INPUTS
V_REF	Reference input voltage	AVDD = 3 V, V_REF = (V_VREFP – V_VREFN)	2	2.5	AVDD	V
V_REF	Reference input voltage	AVDD = 5 V, V_REF = (V_VREFP – V_VREFN)	2	4	AVDD	V
VREFN	Negative reference input			AVSS		V
VREFP	Positive input		AVDD – 3	AVSS + 2.5	AVDD	V
EXTERNAL CLOCK SOURCE
f_CLK	Master clock rate	CLKSEL pin = 0, (AVDD – AVSS) = 3 V	1.7	2.048	2.25	MHz
f_CLK	Master clock rate	CLKSEL pin = 0, (AVDD – AVSS) = 5 V	1.0	2.048	2.25	MHz
DIGITAL INPUTS
	Input voltage		DGND – 0.1		DVDD + 0.1	V
TEMPERATURE RANGE
T_A	Operating ambient temperature		–40		105	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS131E0x	UNIT
		PAG (TQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	35	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	31	°C/W
R_θJB	Junction-to-board thermal resistance	26	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	NA	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	NA	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at 25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, V_REF = 2.4 V, external f_CLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUTS
C_i	Input capacitance					20		pF
I_IB	Input bias current		PGA output in normal range			5		nA
	DC input impedance					200		MΩ
PGA PERFORMANCE
	Gain settings				1, 2, 4, 8, 12
BW	Bandwidth				See Table 3
ADC PERFORMANCE
DR	Data rate		f_CLK = 2.048 MHz		1		64	kSPS
	Resolution		DR = 1 kSPS, 2 kSPS, 4 kSPS, 8 kSPS, and 16 kSPS		24			Bits
	Resolution		DR = 32 kSPS and 64 kSPS		16			Bits
CHANNEL PERFORMANCE (DC PERFORMANCE)
INL	Integral nonlinearity		Full-scale, best fit			10		ppm
	Dynamic range		G = 1		105			dB
	Dynamic range		Gain settings other than 1		See the Noise Measurements section
E_O	Offset error					350		μV
	Offset error drift					0.65		μV/°C
E_G	Gain error		Excluding voltage reference error			0.1%
	Gain drift		Excluding voltage reference drift			3		ppm/°C
	Gain match between channels					0.2		% of FS
CHANNEL PERFORMANCE (AC PERFORMANCE)
CMRR	Common-mode rejection ratio		f_CM = 50 Hz and 60 Hz⁽¹⁾			–110		dB
PSRR	Power-supply rejection ratio		f_PS = 50 Hz and 60 Hz			–80		dB
	Crosstalk		f_IN = 50 Hz and 60 Hz			–110		dB
	Accuracy		3000:1 dynamic range with a 1-second measurement (V_RMS / I_RMS)	AVDD = 3 V, V_REF = 2.4 V		0.04%
	Accuracy			AVDD = 5 V, V_REF = 4 V		0.025%
SNR	Signal-to-noise ratio		f_IN = 50 Hz and 60 Hz, gain = 1			107		dB
THD	Total harmonic distortion		10 Hz, –0.5 dBFs			–93		dB
INTERNAL REFERENCE
V_REF	Output voltage		T_A = 25°C, V_REF = 2.4 V		2.394	2.4	2.406	V
V_REF	Output voltage		T_A = 25°C, V_REF = 4 V			4		V
	V_REF accuracy					±0.2%
	Temperature drift		T_A = –40°C to +105°C			20		ppm/°C
	Start-up time		Settled to 0.2%			150		ms
EXTERNAL REFERENCE
	Input impedance					6		kΩ
INTERNAL OSCILLATOR
	Accuracy					±2%
			T_A = 25°C				±0.5%
			T_A = –40°C to 105°C				2.5%
	Internal oscillator clock frequency		Nominal frequency			2.048		MHz
	Internal oscillator start-up time					20		μs
	Internal oscillator power consumption					120		μW
FAULT DETECT AND ALARM
	Comparator threshold accuracy					±30		mV
OPERATIONAL AMPLIFIER
	Integrated noise		0.1 Hz to 250 Hz			9		µV_RMS
	Noise density		2 kHz			120		nV/√Hz
GBP	Gain bandwidth product		50 kΩ \|\| 10-pF load			100		kHz
SR	Slew rate		50 kΩ \|\| 10-pF load			0.25		V/µs
	Load current					50		µA
THD	Total harmonic distortion		f_IN = 100 Hz			70		dB
	Common-mode input range				AVSS + 0.7		AVDD – 0.3	V
	Quiescent power consumption					20		µA
SYSTEM MONITORS
	Supply reading error	Analog				2%
	Supply reading error	Digital				2%
	Device wake up		From power-up to DRDY low			150		ms
	Device wake up		STANDBY mode			31.25		µs
	Temperature sensor reading	Voltage	T_A = 25°C			145		mV
	Temperature sensor reading	Coefficient				490		μV/°C
SELF-TEST SIGNAL
	Signal frequency		See the Register Map section for settings			f_CLK / 2²¹		Hz
	Signal frequency		See the Register Map section for settings			f_CLK / 2²⁰		Hz
	Signal voltage		See the Register Map section for settings			±1		mV
	Signal voltage		See the Register Map section for settings			±2		mV
DIGITAL INPUT AND OUTPUT (DVDD = 1.8 V to 3.6 V)
V_IH	Logic level, input voltage	High			0.8 DVDD		DVDD+0.1	V
V_IL	Logic level, input voltage	Low			–0.1		0.2 DVDD	V
V_OH	Logic level, output voltage	High	I_OH = –500 µA		0.9 DVDD			V
V_OL	Logic level, output voltage	Low	I_OL = +500 µA				0.1 DVDD	V
I_IN	Input current		0 V < V_DigitalInput < DVDD		–10		10	μA
SUPPLY CURRENT (OPERATIONAL AMPLIFIER TURNED OFF)
I_AVDD	Normal mode		AVDD – AVSS = 3 V			5.1		mA
I_AVDD			AVDD – AVSS = 5 V			5.8		mA
I_DVDD			DVDD = 3.3 V			1		mA
I_DVDD			DVDD = 1.8 V			0.4		mA
POWER DISSIPATION (ANALOG SUPPLY = 3 V)
	Quiescent power dissipation	ADS131E04	Normal mode			9.3	10.2	mW
			Power-down mode			10		µW
			Standby mode			2		mW
		ADS131E06	Normal mode			12.7	13.5	mW
			Power-down mode			10		µW
			Standby mode			2		mW
		ADS131E08	Normal mode			16	17.6	mW
			Power-down mode			10		µW
			Standby mode			2		mW
POWER DISSIPATION (ANALOG SUPPLY = 5 V)
	Quiescent power dissipation	ADS131E04	Normal mode			18		mW
			Power-down mode			20		µW
			Standby mode			4.2		mW
		ADS131E06	Normal mode			24.3		mW
			Power-down mode			20		µW
			Standby mode			4.2		mW
		ADS131E08	Normal mode			29.7		mW
			Power-down mode			20		µW
			Standby mode			4.2		mW

(1) CMRR is measured with a common-mode signal of (AVSS + 0.3 V) to (AVDD – 0.3 V). The values indicated are the minimum of the eight channels.

7.6 Timing Requirements

over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted)

		2.7 V ≤ DVDD ≤ 3.6 V		1.7 V ≤ DVDD ≤ 2.0 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_CLK	Master clock period	444	588	444	588	ns
t_CSSC	Delay time, first SCLK rising edge after CS falling edge	6		17		ns
t_SCLK	SCLK period	50		66.6		ns
t_{SPWH, L}	Pulse duration, SCLK high or low	15		25		ns
t_DIST	Setup time, DIN valid before SCLK falling edge	10		10		ns
t_DIHD	Hold time, DIN valid after SCLK falling edge	10		11		ns
t_CSH	Pulse duration, CS high	2		2		t_CLK
t_SCCS	Delay time, CS rising edge after final SCLK falling edge	4		4		t_CLK
t_SDECODE	Command decode time	4		4		t_CLK
t_DISCK2ST	Setup time, DAISY_IN valid before SCLK falling edge	10		10		ns
t_DISCK2HT	Hold time, DAISY_IN valid after SCLK falling edge	10		10		ns

7.7 Switching Characteristics

over operating ambient temperature range, DVDD = 1.7 V to 3.6 V, and load on DOUT = 20 pF || 100 kΩ (unless otherwise noted)

PARAMETER		2.7 V ≤ DVDD ≤ 3.6 V		1.7 V ≤ DVDD ≤ 2.0 V		UNIT
PARAMETER		MIN	MAX	MIN	MAX	UNIT
t_CSDOD	Propagation delay time, CS falling edge to DOUT driven	10		20		ns
t_DOST	Propagation delay time, SCLK rising edge to valid new DOUT		17		32	ns
t_DOHD	Hold time, SCLK falling edge to invalid DOUT	10		10		ns
t_CSDOZ	Propagation delay time, CS rising edge to DOUT high impedance		10		20	ns

ADS131E04 ADS131E06 ADS131E08 tim_serial_bas561.gif

NOTE:

SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. Serial Interface Timing

ADS131E04 ADS131E06 ADS131E08 tim_daisy_chain_bas561.gif

1. n = Number of channels × resolution + 24 bits. Number of channels is 8; resolution is 24-bit.

Figure 2. Daisy-Chain Interface Timing

7.8 Typical Characteristics

all plots are at T_A = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.