SBAS853A January   2020  – April 2021 ADS131M02

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Startup Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0110 0110)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M02 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Power Metrology Applications
      6. 9.1.6 Code Example
      7. 9.1.7 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement Front-End
        2. 9.2.2.2 Current Measurement Front-End
        3. 9.2.2.3 ADC Setup
        4. 9.2.2.4 Calibration
        5. 9.2.2.5 Formulae
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Behavior
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Noise Measurements

Adjust the data rate and gain to optimize the ADS131M02 noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS131M02 noise performance using the 1.2-V internal reference and a 3.0-V analog power supply. The data are representative of typical noise performance at TA = 25°C when fCLKIN = 8.192 MHz. The modulator clock frequency fMOD = fCLKIN / 2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the RMS noise for each reading. Table 7-2 shows the dynamic range and effective resolution calculated from the noise data. Equation 1 calculates dynamic range. Equation 2 calculates effective resolution. In each case, VREF corresponds to the internal 1.2-V reference. In global-chop mode, noise is improved by a factor of √ 2.

The noise performance scales with the OSR and gain settings, but is independent from the configured power mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the applied clock frequency for the different power modes.

Equation 1. GUID-5F919C6C-910A-461E-A4B8-F3307E31DF57-low.gif
Equation 2. GUID-616B3C3D-E080-4631-8BBF-7989C9FBF52E-low.gif
Table 7-1 Noise (µVRMS) at TA = 25°C
OSR DATA RATE (kSPS),
fCLKIN = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 1.90 1.69 1.56 0.95 0.64 0.42 0.42 0.42
8192 0.5 2.39 2.13 2.13 1.29 0.86 0.57 0.57 0.57
4096 1 3.38 2.99 2.88 1.74 1.17 0.77 0.77 0.77
2048 2 4.25 3.91 3.79 2.27 1.52 1.00 1.00 1.00
1024 4 5.35 4.68 4.52 2.70 1.82 1.20 1.20 1.20
512 8 7.56 6.62 6.37 3.82 2.55 1.69 1.69 1.69
256 16 10.68 9.56 9.09 5.42 3.63 2.39 2.39 2.40
128 32 21.31 15.26 13.52 7.89 5.21 3.41 3.42 3.42
64 64 75.34 41.63 26.84 14.59 8.9 5.57 5.58 5.58
Table 7-2 Dynamic Range (Effective Resolution) at TA = 25°C
OSR DATA RATE (kSPS),
fCLKIN = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 113 (20.3) 108 (19.4) 103 (18.6) 101 (18.3) 98 (17.8) 96 (17.5) 90 (16.5) 84 (15.4)
8192 0.5 111 (19.9) 106 (19.1) 100 (18.1) 98 (17.8) 96 (17.4) 93 (17.0) 87 (16.0) 81 (15.0)
4096 1 108 (19.4) 103 (18.6) 97 (17.7) 96 (17.4) 93 (17.0) 91 (16.6) 85 (15.6) 79 (14.6)
2048 2 106 (19.1) 101 (18.2) 95 (17.3) 93 (17.0) 91 (16.6) 88 (16.2) 82 (15.2) 76 (14.2)
1024 4 104 (18.8) 99 (18.0) 93 (17.0) 92 (16.8) 89 (16.3) 87 (15.9) 81 (14.9) 75 (13.9)
512 8 101 (18.3) 96 (17.5) 90 (16.5) 89 (16.3) 86 (15.8) 84 (15.4) 78 (14.4) 72 (13.4)
256 16 98 (17.8) 93 (16.9) 87 (16.0) 86 (15.8) 83 (15.3) 81 (14.9) 75 (13.9) 69 (12.9)
128 32 92 (16.8) 89 (16.3) 84 (15.4) 83 (15.2) 80 (14.8) 78 (14.4) 72 (13.4) 65 (12.4)
64 64 81 (15.0) 80 (14.8) 78 (14.4) 77 (14.3) 75 (14.0) 74 (13.7) 68 (12.7) 62 (11.7)