Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
In the design of any application involving a high-speed data converter, particular attention should be paid to the design of the analog input, the clocking solution, and careful layout of the clock and analog signals. The ADS5562 evaluation module (EVM) is one practical example of the design of the analog input circuit and clocking solution, as well as a practical example of good circuit board layout practices around the ADC.
The analog inputs of the ADS5562 device must be fully differential and biased to an appropriate common mode voltage, VCM. End equipment typically does not have a signal that already meets the requisite amplitude and common mode and is fully differential. Therefore, a signal conditioning circuit is required for the analog input. If the amplitude of the input circuit is such that no gain is needed to make full use of the full-scale range of the ADC, then a transformer coupled circuit as used on the EVM can be used with good results. The transformer coupling is inherently low-noise, and inherently AC-coupled so that the signal may be biased to VCM after the transformer coupling. Figure 59 shows an example of transformer coupling as used on the ADS556x EVM.
If signal gain is required, or the input bandwidth is to include the spectrum all the way down to DC such that AC coupling is not possible, then an amplifier-based signal conditioning circuit would be required. Figure 60 shows the LMH6552 device interfaced with the ADS5562 device. The LMH6552 device is configured to have to single-ended input with a differential outputs follow by the first Nyquist-based low-pass filter with 40-MHz bandwidth. Figure 60 also shows the power supply recommendations for the amplifier.
Clocking a high-speed ADC such as the ADS5562 device requires a fully differential-clock signal from a clean, low-jitter clock source and driven by an appropriate clock buffer, often with LVPECL or LVDS signaling levels. The sample clock must also be biased up to the appropriate common mode voltage, but unlike the analog input, the data converter itself will often internally bias the clock to the appropriate VCM if the clock signal is AC coupled as in the typical clock driver circuit shown in Figure 50 through Figure 53.
The ADS5562 device requires a fully differential analog input with a full-scale range not to exceed 3.56-V peak-to-peak differential, biased to a common-mode voltage of 1.5 V. In addition the input circuit must provide proper transmission line termination (or proper load resistors in an amplifier-based solution) so the input of the impedance of the ADC analog inputs should be considered as well.
The ADS5562 device is capable of a typical SNR of 82.8 dBFS for input frequencies of about 30 MHz, which is well under the Nyquist limit for this ADC operating at 80 Msps. The amplifier and clocking solution have a direct impact on performance in terms of SNR. Therefore the amplifier and clocking solution should be selected such that the SNR performance of at least 82 dBFS is preserved.
The ADS5562 device has a maximum sample rate of 80 MHz and an input bandwidth of approximately 300 MHz. For this application, the first Nyquist zone is involved, so the frequency bandwidth must be limited under 40 MHz.
The signal-to-noise ratio of the ADC is limited by three different factors: the quantization noise, the thermal noise, and the total jitter of the sample clock. Quantization noise is driven by the resolution of the ADC, which is 16 bits for the ADS5562 device. Thermal noise is typically not noticeable in high-speed pipelined converters such as the ADS5562 device, but may be estimated by looking at the signal to noise ratio of the ADC with very-low input frequencies and using Equation 3 to solve for thermal noise. For this estimation, use the specified SNR for the lowest frequency listed (see the Specifications section. The lowest input frequency listed for the ADS5562 device is at 3 MHz, and the SNR at that frequency is 84 dB. Therefore, use 84 dB as the SNR limit for this application because of thermal noise. This value is just an approximation, and the lower the input frequency that has an SNR specification the better this approximation is. The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher input frequencies.
Quantization noise is also a limiting factor for SNR, as the theoretical maximum achievable SNR as a function of the number of bits of resolution is set by Equation 2.
For a 16-bit ADC, the maximum SNR = 1.76 + (6.02 × 16) = 98.08 dB. This value is the number that is entered into Equation 3 for quantization noise as we solve for total SNR for different amounts of clock jitter using Equation 3.
Use Equation 4 to calculate the SNR limitation because of sample clock jitter.
Note that the clock jitter in Equation 4 is the total amount of clock jitter, whether the jitter source is internal to the ADC or external because of the clocking source. The total clock jitter (TJitter) has two components – the internal aperture jitter (90 fs for ADS5562) which is set by the noise of the clock input buffer, and the external clock jitter from the clocking source and all associated buffering of the clock signal. Use Equation 5 to calculate the total clock jitter from the aperture jitter and the external clock jitter.
The external clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as a bandpass filter at the clock input while a faster clock slew rate may at times also improve the ADC aperture jitter slightly.
The ADS5562 device has an internal aperture jitter of 90 fs, which is largely fixed. The SNR depending on amount of external jitter for different input frequencies is shown in Figure 61. Often the design requirements list a target SNR for a system, and Equation 3 through Equation 5 are then used to calculate the external clock jitter needed from the clocking solution to meet the system objectives.
Figure 61 shows that with an external clock jitter of 200 fs rms, the expected SNR of the ADS5562 device is greater than 82 dBFS at an input tone of 40 MHz, which is the Nyquist limit. Having less external clock jitter such as 150 fs rms, or even 100 fs rms, results in an SNR that exceeds the design target, but possibly at the expense of a more costly clocking solution. An external clock jitter of greater than 200 fs does not meet the design target. Because the design target for SNR is established at 82 dB, and a margin of error is necessary for the SNR contribution from the amplifier and filter on the analog signal, the design goal of 150 fs external clock jitter is established to achieve an SNR for the ADC of approximately 83 dB.
The amplifier and any input filtering has its own SNR performance, and the SNR performance of the amplifier front end combines with the SNR of the ADC to yield a system SNR that is less than that of the ADC. System SNR can be calculated from the SNR of the amplifier conditioning circuit and the overall ADC SNR as in Equation 6. In Equation 6, the SNR of the ADC is the value derived from the data sheet specifications and the clocking derivation presented in the Clocking Source for ADC5562 section.
The SNR of the amplifier and filter can be calculated from the noise specifications in the data sheet for the amplifier, the amplitude of the signal and the bandwidth of the filter. The noise from the amplifier is band-limited by the filter, and the rolloff of the filter depends on the order of the filter. Therefore, replacing the filter rolloff with an equivalent brick-wall filter bandwidth is convenient. For example, a 1st order filter can be approximated by a brick-wall filter with bandwidth of 1.57 times the bandwidth of the 1st order filter. For this design, assume a 1st order filter is used. Use Equation 7 to calculate the amplifier and filter noise.
In Equation 7, the parameters of the equation may be seen to be in terms of signal amplitude in the numerator and amplifier noise in the denominator, or SNR. For the numerator, use the full-scale voltage specification of the ADS5562 device, or 3.56-V peak-to-peak differential. Because Equation 7 requires the signal voltage to be in rms, convert 3.56 VPP to 1.26 V rms.
The noise specification for the LMH6552 device is listed as 1.1 nV/√Hz times the amplifier gain. Therefore, use this value to integrate the noise component from DC out to the filter cutoff, using the equivalent brick wall filter of 40 MHz × 1.57, or 62.8 MHz. The result of 1.1 nV/√Hz over √62.8 MHz times gain yields 8717 nV, or 8.717 µV, assuming a gain factor of 2 for the amplifier.
Using 1.26-V rms for VO and 8.717 µV for EFILTEROUT, the SNR of the amplifier and filter as given by Equation 7 is approximately 103.2 dB.
Taking the SNR of the ADC as 83 dB from Figure 61, and SNR of the amplifier and filter as 103.2 dB, Equation 6 predicts the system SNR to be 82.96 dB. In other words, the SNR of the ADC and the SNR of the front end combine as the square root of the sum of squares, and because the SNR of the amplifier front end is much greater than the SNR of the ADC in this example, the SNR of the ADC dominates Equation 6 and the system SNR is almost the SNR of the ADC. The assumed design requirement is 82 dB, and after a clocking solution was selected and an amplifier or filter solution was selected, the predicted SNR of is 82.96 dB. At this point, consider making tradeoffs of either the clocking specification or amplifier gain to see how such tradeoffs begin to affect the expected system performance.
Figure 61 shows the SNR of the ADC as a function of clock jitter and input frequency for the ADS5562 device. This plot of curves take into account the aperture jitter of the ADC, the number of bits of resolution, and the thermal noise estimation so that the plot can be used to predict SNR for a given input frequency and external clock jitter. Figure 61 then may be used to set the jitter requirement for the clocking solution for a given input bandwidth and given design goal for SNR.