SLWS207B May   2008  – January 2016 ADS5560 , ADS5562

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Electrical Characteristics for ADS5560 Fs = 40 MSPS
    7. 6.7  AC Electrical Characteristics for ADS5562, Fs = 80 MSPS
    8. 6.8  Electrical Characteristics for ADS5562
    9. 6.9  Electrical Characteristics for ADS5560
    10. 6.10 Digital Characteristics
    11. 6.11 Timing Characteristics for LVDS and CMOS Modes
    12. 6.12 Serial Interface Timing Characteristics
    13. 6.13 Reset Timing
    14. 6.14 Timing Characteristics at Lower Sampling Frequencies
    15. 6.15 Typical Characteristics
      1. 6.15.1 ADS5562 - 80 MSPS
      2. 6.15.2 ADS5560 - 40 MSPS
      3. 6.15.3 Valid Up to Max Clock Rate (ADS5562 or ADS5560)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Frequency Noise Suppression
      2. 7.3.2 Analog Input Circuit
        1. 7.3.2.1 Drive Circuit Recommendations
        2. 7.3.2.2 Example Driving Circuit
        3. 7.3.2.3 Input Common-Mode
        4. 7.3.2.4 Programmable Fine Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Sampling Frequency Operation
      2. 7.4.2 Clock Input
        1. 7.4.2.1 Power-Down
          1. 7.4.2.1.1 Global STANDBY
          2. 7.4.2.1.2 Output Buffer Disable
          3. 7.4.2.1.3 Input Clock Stop
        2. 7.4.2.2 Power Supply Sequence
      3. 7.4.3 Output Interface
        1. 7.4.3.1 DDR LVDS Outputs
        2. 7.4.3.2 LVDS Buffer Current Programmability
        3. 7.4.3.3 LVDS Buffer Internal Termination
        4. 7.4.3.4 Parallel CMOS
        5. 7.4.3.5 Output Clock Position Programmability
      4. 7.4.4 Output Data Format
      5. 7.4.5 Reference
        1. 7.4.5.1 Internal Reference
        2. 7.4.5.2 External Reference
    5. 7.5 Programming
      1. 7.5.1 Device Programming Modes
      2. 7.5.2 Using Parallel Interface Control Only
        1. 7.5.2.1 Using Serial Interface Programming Only
        2. 7.5.2.2 Using Both Serial Interface And Parallel Controls
        3. 7.5.2.3 Description of Parallel Pins
      3. 7.5.3 Serial Interface
      4. 7.5.4 Register Initialization
    6. 7.6 Register Maps
      1. 7.6.1 Register Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADC5562
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Supply Decoupling
      2. 10.1.2 Exposed Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN With Exposed Thermal Pad
LVDS Mode – Top View
ADS5560 ADS5562 p0023-09_lws207.gif

Pin Functions - LVDS Mode

PIN I/O DESCRIPTION
NO. NAME
9, 12, 14, 17, 19, 25 AGND I Analog ground
8, 18, 20,
22, 24, 26		 AVDD I Analog power supply
4 CLKOUTM O Differential output clock, complement
5 CLKOUTP O Differential output clock, true
10 CLKP I Differential clock input
11 CLKM
31 D0_D1_M O Differential output data D0 and D1 multiplexed, complement.
32 D0_D1_P O Differential output data D0 and D1 multiplexed, true
43 D10_D11_M O Differential output data D10 and D11 multiplexed, complement
44 D10_D11_P O Differential output data D10 and D11 multiplexed, true
45 D12_D13_M O Differential output data D12 and D13 multiplexed, complement
46 D12_D13_P O Differential output data D12 and D13 multiplexed, true
47 D14_D15_M O Differential output data D14 and D15 multiplexed, complement
48 D14_D15_P O Differential output data D14 and D15 multiplexed, true
33 D2_D3_M O Differential output data D2 and D3 multiplexed, complement
34 D2_D3_P O Differential output data D2 and D3 multiplexed, true
37 D4_D5_M O Differential output data D4 and D5 multiplexed, complement
38 D4_D5_P O Differential output data D4 and D5 multiplexed, true
39 D6_D7_M O Differential output data D6 and D7 multiplexed, complement
40 D6_D7_P O Differential output data D6 and D7 multiplexed, true
41 D8_D9_M O Differential output data D8 and D9 multiplexed, complement
42 D8_D9_P O Differential output data D8 and D9 multiplexed, true
6 DFS I Data Format Select input.
This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output mode type. See Table 7 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to DRGND.
1, 36 DRGND I Digital and output buffer ground
2, 35 DRVDD I Digital and output buffer supply
15 INP I Differential analog input
16 INM
23 MODE I Mode select input.
This pin selects the Internal or External reference mode. See Table 8 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to AGND.
21 NC — Do not connect
7 OE I Output buffer enable input, active high.
The pin has an internal 100-kΩ pullup resistor to DRVDD.
3 OVR O Out-of-range indicator, CMOS level signal
30 RESET I Serial interface reset input.
When using the serial interface, the user should apply a high-going pulse on this pin to reset the internal registers.
When the serial interface is not used, the user should tie RESET permanently high. (SCLK, SDATA and SEN can be used as parallel pin controls).
The pin has an internal 100-kΩ pulldown resistor to DRGND.
29 SCLK I This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED MODE control when RESET is tied high. See Table 4 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to DRGND.
28 SDATA I This pin functions as serial interface data input when RESET is low.
It functions as STANDBY control pin when RESET is tied high.
See Table 5 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to DRGND.
27 SEN I This pin functions as serial interface enable input when RESET is low.
It functions as CLKOUT edge programmability when RESET is tied high. See Table 6 for detailed information.
The pin has an internal 100-kΩ pullup resistor to DRVDD.
13 VCM I/O Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets the internal reference.
— PAD — Connect the PAD to the ground plane. See the Exposed Thermal Pad section.
RGZ Package
48-Pin VQFN With Exposed Thermal Pad
CMOS Mode – Top View
ADS5560 ADS5562 p0023-10_lws207.gif

Pin Functions - CMOS Mode

PIN I/O DESCRIPTION
NO. NAME
9, 12, 14, 17, 19, 25 AGND I Analog ground
8, 18, 20,
22, 24, 26		 AVDD I Analog power supply
5 CLKOUT O CMOS output clock
10 CLKP I Differential clock input
11 CLKM
31 D0 O CMOS output data D0
32 D1 O CMOS output data D1
43 D10 O CMOS output data D10
44 D11 O CMOS output data D11
45 D12 O CMOS output data D12
46 D13 O CMOS output data D13
47 D14 O CMOS output data D14
48 D15 O CMOS output data D15
33 D2 O CMOS output data D2
34 D3 O CMOS output data D3
37 D4 O CMOS output data D4
38 D5 O CMOS output data D5
39 D6 O CMOS output data D6
40 D7 O CMOS output data D7
41 D8 O CMOS output data D8
42 D9 O CMOS output data D9
6 DFS I Data Format Select input.
This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output mode type. See Table 7 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to DRGND.
1, 36 DRGND I Digital and output buffer ground
2, 35 DRVDD I Digital and output buffer supply
15 INP I Differential analog input
16 INM
23 MODE I Mode select input.
This pin selects the Internal or External reference mode. See Table 8 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to AGND.
21 NC — Do not connect
7 OE I Output buffer enable input, active high.
The pin has an internal 100-kΩ pullup resistor to DRVDD.
3 OVR O Out-of-range indicator, CMOS level signal
30 RESET I Serial interface reset input.
When using the serial interface, the user should apply a high-going pulse on this pin to reset the internal registers.
When the serial interface is not used, the user should tie RESET permanently high. (SCLK, SDATA and SEN can be used as parallel pin controls).
The pin has an internal 100-kΩ pulldown resistor to DRGND.
29 SCLK I This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED MODE control when RESET is tied high. See Table 4 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to DRGND.
28 SDATA I This pin functions as serial interface data input when RESET is low.
It functions as STANDBY control pin when RESET is tied high.
See Table 5 for detailed information.
The pin has an internal 100-kΩ pulldown resistor to DRGND.
27 SEN I This pin functions as serial interface enable input when RESET is low.
It functions as CLKOUT edge programmability when RESET is tied high. See Table 6 for detailed information.
The pin has an internal 100-kΩ pullup resistor to DRVDD.
4 UNUSED — Unused pin in CMOS mode
13 VCM I/O Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets the internal references.
— PAD — Connect the PAD to the ground plane. See the Exposed Thermal Pad section.