SLWS207B May   2008  – January 2016 ADS5560 , ADS5562

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Electrical Characteristics for ADS5560 Fs = 40 MSPS
    7. 6.7  AC Electrical Characteristics for ADS5562, Fs = 80 MSPS
    8. 6.8  Electrical Characteristics for ADS5562
    9. 6.9  Electrical Characteristics for ADS5560
    10. 6.10 Digital Characteristics
    11. 6.11 Timing Characteristics for LVDS and CMOS Modes
    12. 6.12 Serial Interface Timing Characteristics
    13. 6.13 Reset Timing
    14. 6.14 Timing Characteristics at Lower Sampling Frequencies
    15. 6.15 Typical Characteristics
      1. 6.15.1 ADS5562 - 80 MSPS
      2. 6.15.2 ADS5560 - 40 MSPS
      3. 6.15.3 Valid Up to Max Clock Rate (ADS5562 or ADS5560)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Frequency Noise Suppression
      2. 7.3.2 Analog Input Circuit
        1. 7.3.2.1 Drive Circuit Recommendations
        2. 7.3.2.2 Example Driving Circuit
        3. 7.3.2.3 Input Common-Mode
        4. 7.3.2.4 Programmable Fine Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Sampling Frequency Operation
      2. 7.4.2 Clock Input
        1. 7.4.2.1 Power-Down
          1. 7.4.2.1.1 Global STANDBY
          2. 7.4.2.1.2 Output Buffer Disable
          3. 7.4.2.1.3 Input Clock Stop
        2. 7.4.2.2 Power Supply Sequence
      3. 7.4.3 Output Interface
        1. 7.4.3.1 DDR LVDS Outputs
        2. 7.4.3.2 LVDS Buffer Current Programmability
        3. 7.4.3.3 LVDS Buffer Internal Termination
        4. 7.4.3.4 Parallel CMOS
        5. 7.4.3.5 Output Clock Position Programmability
      4. 7.4.4 Output Data Format
      5. 7.4.5 Reference
        1. 7.4.5.1 Internal Reference
        2. 7.4.5.2 External Reference
    5. 7.5 Programming
      1. 7.5.1 Device Programming Modes
      2. 7.5.2 Using Parallel Interface Control Only
        1. 7.5.2.1 Using Serial Interface Programming Only
        2. 7.5.2.2 Using Both Serial Interface And Parallel Controls
        3. 7.5.2.3 Description of Parallel Pins
      3. 7.5.3 Serial Interface
      4. 7.5.4 Register Initialization
    6. 7.6 Register Maps
      1. 7.6.1 Register Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADC5562
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Supply Decoupling
      2. 10.1.2 Exposed Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage AVDD –0.3 3.9 V
DRVDD –0.3 3.9 V
Voltage between AGND and DRGND –0.3 0.3 V
Voltage between AVDD and DRVDD –0.3 3.3 V
Voltage applied to VCM pin (in external reference mode) –0.3 1.8 V
Voltage applied to analog input pins INP, INM –0.3 (3.6, AVDD + 0.3 ) V
CLKP, CLKM(2), MODE –0.3 (3.6, AVDD + 0.3 )
RESET, SCLK, SDATA, SEN, OE, DFS –0.3 (3.6, DRVDD + 0.3 ) V
TA Operating free-air temperature –40 85 °C
Tjmax Operating junction temperature 125 °C
Lead temperature 1,6 mm (1/16") from the case for 10 s 220 °C
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When AVDD is turned off, TI recommends switching off the input clock (or ensure the voltage on CLKP, CLKM is <|0.3 V|). This prevents the ESD protection diodes at the clock input pins from turning on.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES AND REFERENCES
AVDD Analog supply voltage 3 3.3 3.6 V
DRVDD Digital supply voltage 3 3.3 3.6 V
ANALOG INPUTS
Differential input voltage range (with default fine gain=1 dB) 3.56 VPP
Input common-mode voltage 1.5 ±0.1 V
Voltage applied on VCM in external reference mode 1.5 ±0.05 V
CLOCK INPUT
Sample rate ADS5562 DEFAULT SPEED mode > 25 80 MSPS
LOW SPEED mode(2) 1 25 MSPS
ADS5560 DEFAULT SPEED mode > 25 40 MSPS
LOW SPEED mode 1 25 MSPS
Clock amplitude, ac-coupled, differential (VCLKP – VCLKM)(1) 0.4 VPP
Clock duty cycle 45% 50% 55%
DIGITAL OUTPUTS
CL Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes) 5 pF
RL Differential external load resistance between the LVDS output pairs (LVDS mode) 100 Ω
Operating free-air temperature –40 85 °C
(1) Supported clock waveform formats: sine wave, LVPECL, LVDS, and LVCMOS
(2) See the Low Sampling Frequency Operation section for details.

6.4 Thermal Information

THERMAL METRIC(1) ADS5560
ADS5562		 UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 27.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.4 °C/W
RθJB Junction-to-board thermal resistance 4.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine gain (1 dB). Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 bits
ANALOG INPUT
Differential input voltage range (1) 3.56 VPP
Differential input capacitance 5 pF
Analog input bandwidth 300 MHz
Analog input common-mode current (per input pin) 6.6 μA/MSPS
VCM Common-mode output voltage Internal reference mode 1.5 V
VCM output current capability Internal reference mode ±4 mA
DC ACCURACY
No Missing Codes 0-dB gain Assured
DNL Differential non-linearity –0.95 0.5 3 LSB
INL Integral non-linearity –8.5 ±3 8.5 LSB
Offset error –25 ±10 25 mV
Offset error temperature coefficient 0.005 mV/°C
Variation of offset error across AVDD supply 1.5 mV/V
There are two sources of gain error: I) internal reference inaccuracy and ii) channel gain error
EGREF Gain error due to internal reference inaccuracy alone –2.5 ±1 2.5 % full scale
ECHAN Channel gain error alone –2.5 ± 1 2.5 % full scale
Channel gain error temperature coefficient 0.01 Δ%/°C
POWER SUPPLY
IAVDD Analog supply current ADS5560 210 250 mA
ADS5562 160 190
IDRVDD Digital supply current LVDS mode
CL = 5 pF, IO = 3.5 mA, RL = 100 Ω		 ADS5560 52 mA
ADS5562 44
CMOS mode
CL = 5 pF, FIN = 3 MHz		 ADS5560 60 mA
ADS5562 37
Total power LVDS mode ADS5560 865 1100 mW
ADS5562 674 810
Standby power STANDBY mode with clock running ADS5560 155 mW
ADS5562 135
Clock stop power 125 150 mW
(1) The full-scale voltage range is a function of the fine gain settings. See Table 1.

6.6 AC Electrical Characteristics for ADS5560 Fs = 40 MSPS

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine gain(1). Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR
Signal to noise ratio		 LVDS interface FIN = 3 MHz 84.3 dBFS
FIN = 10 MHz 80 84
FIN = 25 MHz 82.5
FIN = 30 MHz 81.8
CMOS interface FIN = 3 MHz 83.5 dBFS
FIN = 10 MHz 78 83.1
FIN = 25 MHz 81.8
FIN = 30 MHz 81.6
RMS output noise Inputs tied to common-mode 1.42 LSB
SINAD
Signal to noise and distortion ratio		 LVDS interface FIN = 3 MHz 83.2 dBFS
FIN = 10 MHz 76 83
FIN = 25 MHz 79
FIN = 30 MHz 77
CMOS interface FIN = 3 MHz 82 dBFS
FIN = 10 MHz 75 81.4
FIN = 25 MHz 79.3
FIN = 30 MHz 78
ENOB
Effective number of bits		 LVDS interface, FIN = 10 MHz 12.4 13.5 bits
SFDR
Spurious free dynamic range		 FIN = 3 MHz 90 dBc
FIN = 10 MHz 78 88
FIN = 25 MHz 83
FIN = 30 MHz 79
HD2
Second harmonic		 FIN = 3 MHz 94 dBc
FIN = 10 MHz 78 92
FIN = 25 MHz 90
FIN = 30 MHz 88
(1) After reset, the device is initialized to 1-dB fine gain setting. For SFDR and SNR performance across fine gains, see the Typical Characteristics section.

6.7 AC Electrical Characteristics for ADS5562, Fs = 80 MSPS

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine gain(1). Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR
Signal to noise ratio		 LVDS interface FIN = 3 MHz 84 dBFS
FIN = 10 MHz 79 83.8
FIN = 25 MHz 83.2
FIN = 30 MHz 82.8
CMOS interface FIN = 3 MHz 81.7 dBFS
FIN = 10 MHz 77 81.4
FIN = 25 MHz 80.7
FIN = 30 MHz 80.4
RMS output noise Inputs tied to common-mode 1.42 LSB
SINAD
Signal to noise and distortion ratio		 LVDS interface FIN = 3 MHz 80.5 dBFS
FIN = 10 MHz 75 80.5
FIN = 25 MHz 79.5
FIN = 30 MHz 79
CMOS interface FIN = 3 MHz 80.5 dBFS
FIN = 10 MHz 73.5 80.2
FIN = 25 MHz 79.3
FIN = 30 MHz 77.9
ENOB
Effective number of bits		 LVDS interface, FIN = 10 MHz 12.2 13.1 bits
SFDR
Spurious free dynamic range		 FIN = 3 MHz 85 dBc
FIN = 10 MHz 77 85
FIN = 25 MHz 83
FIN = 30 MHz 80
HD2
Second harmonic		 FIN = 3 MHz 90 dBc
FIN = 10 MHz 77 89
FIN = 25 MHz 88
FIN = 30 MHz 88

6.8 Electrical Characteristics for ADS5562

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0 dB fine gain(1), internal reference mode, DDR LVDS interface. Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HD3
Third harmonic		 FIN = 3 MHz 85 dBc
FIN = 10 MHz 77 85
FIN = 25 MHz 83
FIN = 30 MHz 80
Worst harmonic
other than HD2, HD3		 FIN = 3 MHz 104 dBc
FIN = 10 MHz 102
FIN = 25 MHz 100
FIN = 30 MHz 100
THD
Total harmonic distortion		 FIN = 3 MHz 84 dBc
FIN = 10 MHz 75.5 83
FIN = 25 MHz 82
FIN = 30 MHz 80
IMD
Two-tone intermodulation distortion		 FIN1 = 5 MHz, FIN2 = 10 MHz, each tone –7 dBFS 92 dBFS
Voltage overload recovery time Recovery to 1% for 6-dB overload 1 clock cycles
(1) After reset, the device is initialized to 1-dB fine gain setting. For SFDR and SNR performance across fine gains, see the Typical Characteristics section.

6.9 Electrical Characteristics for ADS5560

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine gain(1). Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HD3
Third harmonic		 FIN = 3 MHz 90 dBc
FIN = 10 MHz 78 88
FIN = 25 MHz 83
FIN = 30 MHz 79
Worst harmonic
other than HD2, HD3		 FIN = 3 MHz 104 dBc
FIN = 10 MHz 102
FIN = 25 MHz 101
FIN = 30 MHz 101
THD
Total harmonic distortion		 FIN = 3 MHz 88 dBc
FIN = 10 MHz 76.5 86
FIN = 25 MHz 81
FIN = 30 MHz 78
IMD
Two-tone intermodulation distortion		 FIN1 = 5 MHz, FIN2 = 10 MHz, each tone –7 dBFS 98 dBFS
Voltage overload recovery time Recovery to 1% for 6-dB overload 1 clock cycles

6.10 Digital Characteristics

DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1, AVDD = 3 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
High-level input voltage 2.4 V
Low-level input voltage 0.8 V
High-level input current 33 μA
Low-level input current –33 μA
Input capacitance 4 pF
DIGITAL OUTPUTS – CMOS MODE
High-level output voltage DRVDD V
Low-level output voltage 0 V
Output capacitance Capacitance inside the device from each output pin to ground 4 pF
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage, VODH 350 mV
Low-level output voltage, VODL –350 mV
Output common-mode voltage, VOCM 1.2 V
Output capacitance Capacitance inside the device from each output pin to ground 4 pF
(1) All LVDS and CMOS specifications are characterized, but not tested at production.
(2) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.

6.11 Timing Characteristics for LVDS and CMOS Modes

Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 3 to 3.6 V, Sampling frequency = 80 MSPS, sine wave input clock, 50% clock duty cycle, 1.5-VPP clock amplitude, CL = 5 pF(2) , no internal termination, IO = 3.5 mA, RL = 100 Ω(3) Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3 to 3.6 V, unless otherwise noted.(1)
MIN NOM MAX UNIT
ta Aperture delay 0.5 1.2 2 ns
tj Aperture jitter Sampling frequency = 80 MSPS 90 fs rms
Sampling frequency = 40 MSPS 135 fs rms
Wake-up time Time to data stable(8) after coming out of STANDBY mode 60 200 μs
Time to valid data after stopping and restarting the input clock 80 μs
Latency 16 Clock cycles
DDR LVDS MODE(4)
LVDS bit clock duty cycle 47% 50% 53%
tsu Data setup time(5) Data valid(6) to zero-crossing of CLKOUTP 2 3 ns
th Data hold time(5) Zero-crossing of CLKOUTP to data becoming invalid(6) 2 3 ns
tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 9.5 11 12.5 ns
tr Data rise time Rise time measured from –100 mV to 100 mV 0.15 0.22 0.3 ns
tf Data fall time Fall time measured from 100 mV to –100 mV 0.15 0.22 0.3 ns
tr Output clock rise time Rise time measured from –100 mV to 100 mV 0.15 0.22 0.3 ns
tf Output clock fall time Fall time measured from 100 mV to –100 mV 0.15 0.22 0.3 ns
tOE Output enable (OE) to data delay Time to data valid after OE becomes active 700 ns
PARALLEL CMOS MODE
CMOS output clock duty cycle 50%
tsu Data setup time Data valid(7) to 50% of CLKOUT rising edge 6.5 8 ns
th Data hold time 50% of CLKOUT rising edge to data becoming invalid (7) 2 3 ns
tPDI Clock propagation delay Input clock rising edge cross-over to 50% of CLKOUT rising edge 6.3 7.8 9.3 ns
tr Data rise time Rise time measured from 20% to 80% of DRVDD 1 1.5 2 ns
tf Data fall time Fall time measured from 80% to 20% of DRVDD 1 1.5 2 ns
tr Output clock rise time Rise time measured from 20% to 80% of DRVDD 0.7 1 1.2 ns
tf Output clock fall time Fall time measured from 80% to 20% of DRVDD 1.2 1.5 1.8 ns
tOE Output enable (OE) to data delay Time to data valid after OE becomes active 200 ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) CL is the effective external single-ended load capacitance between each output pin and ground.
(3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to logic high of 100 mV and logic low of –100 mV.
(7) Data valid refers to logic high of 2.6 V and logic low of 0.66 V.
(8) Data stable is defined as the point at which the SNR is within 2 dB of thenormal value.

6.12 Serial Interface Timing Characteristics

Typical values at 25°C, minimum and maximum values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN NOM MAX UNIT
fSCLK SCLK frequency > DC 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDATA setup time 25 ns
tDH SDATA hold time 25 ns

6.13 Reset Timing

Typical values at 25°C, minimum and maximum values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN NOM MAX UNIT
t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active 5 ms
t2 Reset pulse width Pulse width of active RESET signal 10 ns
1 μs
t3 Register write delay Delay from RESET disable to SEN active 25 ns
tPO Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ms

6.14 Timing Characteristics at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS) tsu, SETUP TIME (ns) th, HOLD TIME (ns) tPDI, CLOCK PROPAGATION DELAY (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
DDR LVDS
65 2.7 3.7 2.7 3.7 11.5 13 14.5
40 5 6 5 6 16.5 18 19.5
20 8 11 8 11 30.5 32 33.5
PARALLEL CMOS
65 8 9.5 3 4 7 8.5 10
40 14 15.5 6.5 7.5 8 9.5 11
20 14 6.5 5 10.5 15
ADS5560 ADS5562 reset_time_lws192.gif

NOTE:

A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. If the pulse is greater than 1 µs, the device could enter the parallel configuration mode briefly then return back to serial interface mode. For parallel interface operation, RESET must be tied permanently HIGH.
Figure 1. Reset Timing Diagram
ADS5560 ADS5562 t0334-01_lws207.gif Figure 2. LVDS Output Voltage Levels
ADS5560 ADS5562 t0105-08_lws207.gif Figure 3. Latency
ADS5560 ADS5562 t0106-06_lws207.gif Figure 4. LVDS Mode Timing
ADS5560 ADS5562 t0107-04_lws207.gif Figure 5. CMOS Mode Timing

6.15 Typical Characteristics

6.15.1 ADS5562 – 80 MSPS

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine gain (1 dB), 32k Point FFT (unless otherwise noted)
ADS5560 ADS5562 g001_lws207.gif Figure 6. FFT for 5 MHz, –1-dBFS Input Signal
ADS5560 ADS5562 g003_lws207.gif Figure 8. FFT for 5 MHz, –80-dBFS Input Signal (Small Signal)
ADS5560 ADS5562 g006_lws207.gif Figure 10. SNR vs Fin, 0-dB Gain
ADS5560 ADS5562 g009_lws207.gif Figure 12. SFDR Across Fine Gain
ADS5560 ADS5562 g013_A_lws207.gif Figure 14. Performance vs AVDD Supply
ADS5560 ADS5562 g015_lws207.gif Figure 16. Performance vs Temperature
ADS5560 ADS5562 g017_lws207.gif Figure 18. Performance vs Clock Amplitude
ADS5560 ADS5562 g019_lws207.gif Figure 20. Output Noise Histogram
ADS5560 ADS5562 g002_lws207.gif Figure 7. FFT for 20 MHz, –1-dBFS Input Signal
ADS5560 ADS5562 g004_lws207.gif Figure 9. Intermodulation Distortion
ADS5560 ADS5562 g007_lws207.gif Figure 11. SFDR vs FIN
ADS5560 ADS5562 g010_lws207.gif Figure 13. SNR Across Fine Gain
ADS5560 ADS5562 g014_A_lws207.gif Figure 15. Performance vs DRVDD Supply
ADS5560 ADS5562 g016_lws207.gif Figure 17. Performance vs Input Amplitude, 0-dB Gain
ADS5560 ADS5562 g018_lws207.gif Figure 19. Performance vs Clock Duty Cycle
ADS5560 ADS5562 g020_lws207.gif Figure 21. Performance in External Reference Mode

6.15.2 ADS5560 – 40 MSPS

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine gain (1 dB), 32k Point FFT (unless otherwise noted)
ADS5560 ADS5562 g022_lws207.gif Figure 22. FFT for 5 MHz, –1-dBFS Input Signal
ADS5560 ADS5562 g024_lws207.gif Figure 24. FFT for 5 MHz, –80-dBFS Input Signal
ADS5560 ADS5562 g027_lws207.gif Figure 26. SNR vs Fin, 0-dB Gain
ADS5560 ADS5562 g030_lws207.gif Figure 28. SFDR Across Fine Gain
ADS5560 ADS5562 g034_A_lws207.gif Figure 30. Performance vs AVDD Supply
ADS5560 ADS5562 g036_lws207.gif Figure 32. Performance vs Temperature
ADS5560 ADS5562 g038_lws207.gif Figure 34. Performance vs Clock Amplitude
ADS5560 ADS5562 g040_lws207.gif Figure 36. Output Noise Histogram
ADS5560 ADS5562 g023_lws207.gif Figure 23. FFT for 20 MHz, –1-dBFS Input Signal
ADS5560 ADS5562 g025_lws207.gif Figure 25. Intermodulation Distortion
ADS5560 ADS5562 g028_lws207.gif Figure 27. SFDR vs Fin
ADS5560 ADS5562 g031_lws207.gif Figure 29. SNR Across Fine Gain
ADS5560 ADS5562 g035_A_lws207.gif Figure 31. Performance vs DRVDD Supply
ADS5560 ADS5562 g037_lws207.gif Figure 33. Performance vs Input Amplitude, 0-dB Gain
ADS5560 ADS5562 g039_lws207.gif Figure 35. Performance vs Clock Duty Cycle
ADS5560 ADS5562 g041_lws207.gif Figure 37. Performance in External Reference Mode

6.15.3 Valid Up to Max Clock Rate (ADS5562 or ADS5560)

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Maximum Rated, sine wave input clock, 1.5-VPP clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine gain (1 dB), 32k Point FFT (unless otherwise noted)
ADS5560 ADS5562 g043_lws207.gif Figure 38. CMRR vs Common-Mode Frequency
ADS5560 ADS5562 m0049-04_lws207.gif Figure 40. SFDR Contour, 0-dB Gain
ADS5560 ADS5562 g044_lws207.gif Figure 39. Power Dissipation vs Sampling Frequency
ADS5560 ADS5562 m0048-04_lws207.gif Figure 41. SNR Contour, 0-dB Gain