SBAS629B October 2015 – June 2017 ADS9110
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing these circuits, followed by an application circuit designed using the ADS9110.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input signal and its low output impedance provides a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is critical to meet the linearity and noise performance of the ADS9110.
Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:
A charge kickback filter is designed as a low-pass, RC filter, where the 3-dB bandwidth is optimized based on specific application requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals, keep the filter bandwidth low to band-limit the noise fed into the input of the ADC, thereby increasing the signal-to-noise ratio (SNR) of the system.
Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected from each input pin of the ADC to the ground (as shown in Figure 92). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be at least 15 times the specified value of the ADC sampling capacitance. For the ADS9110, the input sampling capacitance is equal to 60 pF, thus it is recommended to keep CFLT greater than 900 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design. For the ADS9110, limiting the value of RFLT to a maximum of 10-Ω is recommended in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors must be kept less than 1% to keep the inputs balanced.
The driver amplifier must be selected such that its closed-loop output impedance is at least 5X less than the RFLT.
The external reference source to the ADS9110 must provide low-drift and very accurate voltage for the ADC reference input and support the dynamic charge requirements without affecting the noise and linearity performance of the device. The output broadband noise of most references can be in the order of a few hundred μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz.
After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (see Figure 38), between each pair of REFP and REFM pins for regulating the voltage at the reference input of the ADC. The effective capacitance of any large capacitor reduces with the applied voltage based on the voltage rating and type. Using X7R-type capacitors is strongly recommended.
The amplifier selected as the reference driver must have an extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC reference pins without any stability issues.
Design an application circuit optimized for using the ADS9110 to achieve:
The application circuits are illustrated in Figure 93. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.
The input signal is processed through the OPA625 (a high-bandwidth, low-distortion, high-precision amplifier in an inverting gain configuration) and a low-pass RC filter before being fed into the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the OPA625 in an inverting gain configuration. The low-power OPA625 as an input driver provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications. To exercise the complete dynamic range of the ADS9110, the common-mode voltage at the ADS9110 inputs is established at a value of 2.25 V (4.5 V / 2) by using the noninverting pins of the OPA625 amplifiers.
The reference driver circuit, illustrated in Figure 93, generates a voltage of 4.5 VDC using a single 5-V supply. This circuit is suitable to drive the reference of the ADS9110 at higher sampling rates up to 2 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.
The reference buffer is designed with the OPA625 and OPA378 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The OPA625 is a high-bandwidth amplifier with a very low open-loop output impedance of 1 Ω up to a frequency of 1 MHz. The low open-loop output impedance makes the OPA625 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The relatively higher offset and drift specifications of the OPA625 are corrected by using a dc-correcting amplifier (the OPA378) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA378.
Design an application circuit optimized for using the ADS9110 with a fully differential amplifier (FDA) to achieve:
The application circuits are illustrated in Figure 96 and Figure 97. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.
The reference voltage of 4.5 V generated by the REF6045, a high-precision voltage reference with integrated high-bandwidth buffer.
In both applications, the input signal is processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in an inverting gain configuration and a low-pass RC filter before going to the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4551 as an input driver that provides exceptional ac performance because of its extremely low-distortion and high bandwidth specifications. In addition, the components of the charge kickback filter keep the noise from the front-end circuit low without adding distortion to the input signal. The 10 Ω in the loop resistor improves the phase margin of the THS4551 when driving capacitive loads.
The circuit in Figure 96 shows a fully-differential data acquisition (DAQ) block optimized for low distortion and noise using the THS4551 and the REF6045 with the ADS9110. This front-end circuit configuration requires a differential signal at the input of the FDA and provides a differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551. To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
The circuit in Figure 97 shows a single-ended to differential DAQ block optimized for low distortion and noise using the THS4551 and the REF6045 with the ADS9110. This front-end circuit configuration requires a single-ended ac signal at the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551. To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the input signal.
|fIN = 2 kHz, SNR = 98.7 dB, THD = –121.5 dB|
|fIN = 2 kHz, SNR = 97.8 dB, THD = –119.2 dB|
|Typical INL of ±0.5 LSB|
|Typical INL of ±0.5 LSB|