SBAS650C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Clocking and Timing Signal Generation

The crystal oscillator generates a master clock signal using an external crystal. In the default mode, a divide-by-2 block converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller. The clocking functionality is shown in Figure 8-7.

GUID-383C64E5-046E-4553-A3E0-47C4F5F0C7EB-low.gifFigure 8-7 AFE Clocking

To enable flexible clocking, the AFE4403 has a clock divider with programmable division ratios. While the default division ratio is divide-by-2, the clock divider can be programmed to select between ratios of 1, 2, 4, 6, 8, or 12. The division ratio should be selected based on the external clock input frequency such that the divided clock has a frequency close to 4 MHz. For this reason, CLKOUT is referred as a 4-MHz clock in this document. When operating with an external clock input, the divider is reset based on the RESET rising edge. Figure 8-8 shows the case where the divider ratio is set to divide-by-2.

GUID-A64D289A-AD81-43E8-9934-11CE2FB4E085-low.gifFigure 8-8 Clock Divider Reset

The device supports both external clock mode as well as an internal clock mode with external crystal.

In the external clock mode, an external clock is input on the XIN pin and the device internally generates the internal clock (used by the timing engine and the ADC) by a programmable division ratio. After division, the internal clock should be within a range of 4 MHz to 6 MHz. The exact frequency of this divided clock is one of the pieces of information required to establish the heart rate being measured from the pulse data.

In internal clock mode, an external crystal (connected between XIN and XOUT) is used to generate the clock. To generate sustained oscillations, the oscillator within the AFE provides negative resistance to cancel out the ESR of the crystal. A good rule of thumb is to limit the ESR of the crystal to less than a third of the negative resistance achievable by the oscillator. Figure 8-9 shows the connection of Crystal to AFE4403.

GUID-1817948B-2ED3-4CBE-A362-828236EBFC2F-low.gifFigure 8-9 Connection of Crystal to AFE4403

In Figure 8-9 the crystal is characterized by a capacitance, Csh (shunt capacitance of the crystal) and an equivalent series resistance (ESR). C1 and C2 are external capacitors added at the XIN and XOUT pins.

The negative resistance achievable from the internal oscillator is given by Equation 4:

Equation 4. R = –1 / (2 × ω × Csh × [1 + Csh / CL])

where

  • CL = (C1 × C2) / (C1 + C2),
  • ω is the frequency of oscillation in rads,
  • Csh is the shunt capacitor of the crystal, and
  • C1, C2 are the capacitors to ground from the XIN, XOUT pins. A value of approximately 15 pF is recommended for C1, C2.

For example, with Csh = 8 pF, C1 = C2 = 15 pF, and a frequency of 8 MHz, the result is Equation 5:

Equation 5. R = –600 Ω

Thus, the crystal ESR is limited to less than approximately 200 Ω.

TI highly recommends that a single clock source be used to generate the clock required by the AFE as well as the clock needed by the microcontroller (MCU). If an independent clock source is used by the MCU, then any energy coupling into the AFE supply or ground or input pins can cause aliased spurious tones close to the heart rate being measured. To enable operation with the single clock source between the AFE and the MCU, two options are possible:

  1. AFE clock as master: The AFE uses a crystal to generate its clock. CLKOUT from the AFE is used as the input clock for the MCU.
  2. MCU clock as master: The AFE operates with an external clock provided by the MCU.

Note that the switching of CLKOUT consumes power. Thus, if CLKOUT is not used, it can be shut off using the CLKOUT_TRI bit.