SPRS657F February   2010  – January 2017 AM1705

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 Memory Map Summary
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  External Memory Interface A (ASYNC)
      4. 3.6.4  External Memory Interface B (SDRAM only)
      5. 3.6.5  Serial Peripheral Interface Modules (SPI0, SPI1)
      6. 3.6.6  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      7. 3.6.7  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      8. 3.6.8  Enhanced Quadrature Encoder Pulse Module (eQEP)
      9. 3.6.9  Boot
      10. 3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      11. 3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)
      12. 3.6.12 Timers
      13. 3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
      14. 3.6.14 Universal Serial Bus Modules (USB0)
      15. 3.6.15 Ethernet Media Access Controller (EMAC)
      16. 3.6.16 Multimedia Card/Secure Digital (MMC/SD)
      17. 3.6.17 Reserved and No Connect
      18. 3.6.18 Supply and Ground
      19. 3.6.19 Unused USB0 (USB2.0) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments on the device
        5. 6.7.1.5 AINTC Memory Map
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Connection Examples
      3. 6.10.3 External Memory Interface A (EMIFA) Registers
      4. 6.10.4 EMIFA Electrical Data/Timing
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Registers
      4. 6.11.4 EMIFB Electrical Data/Timing
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 6.18 Enhanced Capture (eCAP) Peripheral
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 Timers
      1. 6.21.1 Timer Electrical Data/Timing
    22. 6.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.22.1 I2C Device-Specific Information
      2. 6.22.2 I2C Peripheral Registers Description(s)
      3. 6.22.3 I2C Electrical Data/Timing
        1. 6.22.3.1 Inter-Integrated Circuit (I2C) Timing
    23. 6.23 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.23.1 UART Peripheral Registers Description(s)
      2. 6.23.2 UART Electrical Data/Timing
    24. 6.24 USB0 OTG (USB2.0 OTG)
      1. 6.24.1 USB2.0 (USB0) Electrical Data/Timing
      2. 6.24.2 USB0 Unused Signal Configuration
    25. 6.25 Power and Sleep Controller (PSC)
      1. 6.25.1 Power Domain and Module Topology
        1. 6.25.1.1 Power Domain States
        2. 6.25.1.2 Module States
    26. 6.26 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.26.1 PRUSS Register Descriptions
    27. 6.27 Emulation Logic
      1. 6.27.1 JTAG Port Description
      2. 6.27.2 Scan Chain Configuration Parameters
      3. 6.27.3 Initial Scan Chain Configuration
        1. 6.27.3.1 Adding TAPS to the Scan Chain
      4. 6.27.4 JTAG 1149.1 Boundary Scan Considerations
    28. 6.28 IEEE 1149.1 JTAG
      1. 6.28.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
      2. 6.28.2 JTAG Test-Port Electrical Data/Timing
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for PTP
    2. 8.2 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.2.1 Standoff Height
      2. 8.2.2 PowerPAD™ PCB Footprint
    3. 8.3 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Comparison

3.1 Device Characteristics

Table 3-1 provides an overview of the device. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 3-1 Characteristics of the Device

HARDWARE FEATURES AM1705
Peripherals


Not all peripherals pins are available at the same time (for more detail, see the Device Configurations section). 		EMIFB 16-bit, up to 128 MB SDRAM
EMIFA Asynchronous (8-bit bus width) RAM, Flash, NOR, NAND
Flash Card Interface MMC and SD cards supported
EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers
Timers 2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as Watch Dog)
UART 3 (one with RTS and CTS flow control)
SPI 2 (Each with one hardware chip select)
I2C 2 (both Master/Slave)
Multichannel Audio Serial Port [McASP] 2(each with transmit/receive, FIFO buffer, 16/12/4 serializers)
10/100 Ethernet MAC with Management Data I/O 1 (RMII Interface)
eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
eQEP 2 32-bit QEP channels with 4 inputs/channel
USB 2.0 (USB0) Full-Speed/Low-Speed OTG Controller with on-chip OTG PHY
General-Purpose Input/Output Port 8 banks of 16-bit
PRU Subsystem (PRUSS) 2 Programmable PRU Cores
On-Chip Memory Size (Bytes) 168KB RAM, 64KB ROM
Organization ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM

ADDITIONAL MEMORY
128KB RAM
JTAG BSDL_ID DEVIDR0 register 0x8B7D F02F (Silicon Revision 1.1)
0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)
CPU Frequency MHz ARM926 375 MHz (1.2V) or 456 MHz (1.3V)
Voltage Core (V) 1.2 V nominal for 375 MHz version
1.3 V nominal for 456 MHz version
I/O (V) 3.3 V
Package 24 mm x 24 mm, 176-Pin, 0.5 mm pitch, TQFP (PTP)
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 375 MHz Versions - PD
456 MHz Version - PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters..

3.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

3.3 ARM Subsystem

The ARM Subsystem includes the following features:

  • ARM926EJ-S RISC processor
  • ARMv5TEJ (32/16-bit) instruction set
  • Little endian
  • System Control Co-Processor 15 (CP15)
  • MMU
  • 16KB Instruction cache
  • 16KB Data cache
  • Write Buffer
  • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
  • ARM Interrupt controller

3.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

  • ARM926EJ -S integer core
  • CP15 system control coprocessor
  • Memory Management Unit (MMU)
  • Separate instruction and data caches
  • Write buffer
  • Separate instruction and data (internal RAM) interfaces
  • Separate instruction and data AHB bus interfaces
  • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com

3.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

3.3.3 MMU

A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

  • Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
  • Mapping sizes are:
    • 1MB (sections)
    • 64KB (large pages)
    • 4KB (small pages)
    • 1KB (tiny pages)
  • Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)
  • Hardware page table walks
  • Invalidate entire TLB, using CP15 register 8
  • Invalidate TLB entry, selected by MVA, using CP15 register 8
  • Lockdown of TLB entries, using CP15 register 10

3.3.4 Caches and Write Buffer

The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features:

  • Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
  • Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache
  • Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables
  • Critical-word first cache refilling
  • Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption
  • Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.
  • Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

3.3.5 Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

  • Trace Port provides real-time trace capability for the ARM9.
  • Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

This device uses ETM9™ version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is available from ARM Ltd. Reference the 'CoreSight™ ETM9™ Technical Reference Manual, revision r0p1' and the 'ETM9 Technical Reference Manual, revision r2p2'.

3.3.7 ARM Memory Mapping

By default the ARM has access to most on and off chip memory areas, EMIFA, EMIFB, and the additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default.

To improve security and/or robustness, the device has extensive memory and peripheral protection units which can be configured to limit access rights to the various on/off chip resources to specific hosts; including the ARM as well as other master peripherals. This allows the system tasks to be partitioned between the ARM and DSP as best suites the particular application; while enhancing the overall robustness of the solution.

See Table 3-2 for a detailed top level device memory map that includes the ARM memory space.

3.4 Memory Map Summary

Table 3-2 AM1705 Top Level Memory Map

Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Map Master Peripheral Mem Map
0x0000 0000 0x0000 0FFF 4K - PRUSS Local Address Space
0x0000 1000 0x01BB FFFF -
0x01BC 0000 0x01BC 0FFF 4K ARM ETB memory -
0x01BC 1000 0x01BC 17FF 2K ARM ETB reg -
0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher -
0x01BC 1900 0x01BF FFFF -
0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller
0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0
0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1
0x01C0 8800 0x01C0 FFFF -
0x01C1 0000 0x01C1 0FFF 4K PSC 0
0x01C1 1000 0x01C1 1FFF 4K PLL Controller
0x01C1 2000 0x01C1 3FFF -
0x01C1 4000 0x01C1 4FFF 4K SYSCFG
0x01C1 5000 0x01C1 FFFF -
0x01C2 0000 0x01C2 0FFF 4K Timer64P 0
0x01C2 1000 0x01C2 1FFF 4K Timer64P 1
0x01C2 2000 0x01C2 2FFF 4K I2C 0
0x01C2 3000 0x01C2 3FFF
0x01C2 4000 0x01C3 FFFF
0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0
0x01C4 1000 0x01C4 1FFF 4K SPI 0
0x01C4 2000 0x01C4 2FFF 4K UART 0
0x01C4 3000 0x01CF FFFF -
0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control
0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control
0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data
0x01D0 3000 0x01D0 3FFF -
0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control
0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control
0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data
0x01D0 7000 0x01D0 BFFF -
0x01D0 C000 0x01D0 CFFF 4K UART 1
0x01D0 D000 0x01D0 DFFF 4K UART 2
0x01D0 E000 0x01DF FFFF
0x01E0 0000 0x01E0 FFFF 64K USB0
0x01E1 0000 0x01E1 1FFF -
0x01E1 2000 0x01E1 2FFF 4K SPI 1
0x01E1 3000 0x01E1 3FFF -
0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1)
0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2)
0x01E1 6000 0x01E1 FFFF -
0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM
0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers
0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers
0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port
0x01E2 5000 0x01E2 5FFF -
0x01E2 6000 0x01E2 6FFF 4K GPIO
0x01E2 7000 0x01E2 7FFF 4K PSC 1
0x01E2 8000 0x01E2 8FFF 4K I2C 1
0x01E2 9000 0x01EF FFFF -
0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0
0x01F0 1000 0x01F0 1FFF 4K HRPWM 0
0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1
0x01F0 3000 0x01F0 3FFF 4K HRPWM 1
0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2
0x01F0 5000 0x01F0 5FFF 4K HRPWM 2
0x01F0 6000 0x01F0 6FFF 4K ECAP 0
0x01F0 7000 0x01F0 7FFF 4K ECAP 1
0x01F0 8000 0x01F0 8FFF 4K ECAP 2
0x01F0 9000 0x01F0 9FFF 4K EQEP 0
0x01F0 A000 0x01F0 AFFF 4K EQEP 1
0x01F0 B000 0x5FFF FFFF -
0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2)
0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3)
0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4)
0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5)
0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers
0x6800 8000 0x7FFF FFFF -
0x8000 0000 0x8001 FFFF 128K On-chip RAM
0x8002 0000 0xAFFF FFFF -
0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers
0xB000 8000 0xBFFF FFFF -
0xC000 0000 0xC7FF FFFF 128M EMIFB SDRAM Data
0xC800 0000 0xFFFC FFFF
0xFFFD 0000 0xFFFD FFFF 64K ARM local ROM -
0xFFFE 0000 0xFFFE DFFF -
0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt Controller -
0xFFFF 0000 0xFFFF 1FFF 8K ARM local RAM - ARM local RAM (PRU 0 Only) -
0xFFFF 2000 0xFFFF FFFF -

3.5 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

3.5.1 Pin Map (Bottom View)

AM1705 ptp_am1705.gif Figure 3-1 Pin Map (PTP)

3.6 Terminal Functions

Table 3-3 to Table 3-20 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.

3.6.1 Device Reset and JTAG

Table 3-3 Reset and JTAG Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) DESCRIPTION
PTP
RESET
RESET 146 I Device reset input
JTAG
TMS 152 I IPU JTAG test mode select
TDI 153 I IPU JTAG test data input
TDO 156 O IPD JTAG test data output
TCK 155 I IPU JTAG test clock
TRST 150 I IPD JTAG test reset
RTCK / GP7[14] 157 I/O IPD JTAG Test Clock Return Clock Output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.2 High-Frequency Oscillator and PLL

Table 3-4 High-Frequency Oscillator and PLL Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) DESCRIPTION
PTP
1.2-V OSCILLATOR
OSCIN 143 I Oscillator input
OSCOUT 145 O Oscillator output
OSCVSS 144 GND Oscillator ground
1.2-V PLL
PLL0_VDDA 141 PWR PLL analog VDD (1.2-V filtered supply)
PLL0_VSSA 142 GND PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.3 External Memory Interface A (ASYNC)

Table 3-5 External Memory Interface A (EMIFA) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 I/O IPU MMC/SD, GPIO, BOOT EMIFA data bus
EMA_D[6]/MMCSD_DAT[6]/GP0[6] 52 I/O IPU MMC/SD, GPIO
EMA_D[5]/MMCSD_DAT[5]/GP0[5] 51 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/GP0[4] 49 I/O IPU
EMA_D[3]/MMCSD_DAT[3]/GP0[3] 48 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/GP0[2] 46 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/GP0[1] 45 I/O IPU
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 I/O IPU MMC/SD, GPIO, BOOT
EMA_A[12]/GP1[12] 42 O IPU GPIO EMIFA address bus
EMA_A[11]/ GP1[11] 41 O IPU
EMA_A[10]/GP1[10] 27 O IPU
EMA_A[9]/GP1[9] 40 O IPU
EMA_A[8]/GP1[8] 39 O IPU
EMA_A[7]/GP1[7] 37 O IPD
EMA_A[6]/GP1[6] 36 O IPD
EMA_A[5]/GP1[5] 35 O IPD
EMA_A[4]/GP1[4] 34 O IPD
EMA_A[3]/GP1[3] 32 O IPD
EMA_A[2]/MMCSD_CMD/GP1[2] 31 O IPU MMCSD, GPIO EMIFA address bus
EMA_A[1]/MMCSD_CLK/GP1[1] 30 O IPU
EMA_A[0]/GP1[0] 29 O IPD GPIO
EMA_BA[1]/GP1[13] 26 O IPU EMIFA bank address
EMA_BA[0]/GP1[14] 25 O IPU GPIO
EMA_CS[3] /GP2[6] 21 O IPU GPIO EMIFA Async Chip Select
EMA_CS[2]/GP2[5]/BOOT[15] 23 O IPU GPIO, BOOT
EMA_OE /AXR0[13]/GP2[7] 22 O IPU McASP0, GPIO EMIFA output enable
EMA_WAIT[0]/ GP2[10] 19 I IPU GPIO EMIFA wait input/interrupt
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.4 External Memory Interface B (SDRAM only)

Table 3-6 External Memory Interface B (EMIFB) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
EMB_D[15]/GP6[15] 74 I/O IPD GPIO EMIFB SDRAM data bus
EMB_D[14]/GP6[14] 76 I/O IPD
EMB_D[13]/GP6[13] 78 I/O IPD
EMB_D[12]/GP6[12] 79 I/O IPD
EMB_D[11]/GP6[11] 80 I/O IPD
EMB_D[10]/GP6[10] 82 I/O IPD
EMB_D[9]/GP6[9] 83 I/O IPD
EMB_D[8]/GP6[8] 84 I/O IPD
EMB_D[7]/GP6[7] 62 I/O IPD
EMB_D[6]/GP6[6] 63 I/O IPD
EMB_D[5]/GP6[5] 64 I/O IPD
EMB_D[4]/GP6[4] 66 I/O IPD
EMB_D[3]/GP6[3] 68 I/O IPD
EMB_D[2]/GP6[2] 70 I/O IPD
EMB_D[1]/GP6[1] 72 I/O IPD
EMB_D[0]/GP6[0] 73 I/O IPD
EMB_A[12]/GP3[13] 89 O IPD GPIO EMIFB SDRAM row/column address bus
EMB_A[11]/GP7[13] 91 O IPD
EMB_A[10]/GP7[12] 105 O IPD
EMB_A[9]/GP7[11] 92 O IPD
EMB_A[8]/GP7[10] 94 O IPD
EMB_A[7]/GP7[9] 95 O IPD
EMB_A[6]/GP7[8] 96 O IPD
EMB_A[5]/GP7[7] 97 O IPD
EMB_A[4]/GP7[6] 98 O IPD GPIO EMIFB SDRAM row/column address
EMB_A[3]/GP7[5] 100 O IPD
EMB_A[2]/GP7[4] 101 O IPD
EMB_A[1]/GP7[3] 102 O IPD
EMB_A[0]/GP7[2] 103 O IPD
EMB_BA[1]/GP7[0] 106 O IPU EMIFB SDRAM bank address
EMB_BA[0]/GP7[1] 107 O IPU
EMB_CLK 86 O IPU EMIF SDRAM clock
EMB_SDCKE 88 O IPU EMIFB SDRAM clock enable
EMB_WE 59 O IPU EMIFB write enable
EMB_RAS 110 O IPU EMIFB SDRAM row address strobe
EMB_CAS 57 O IPU EMIFB column address strobe
EMB_CS[0] 108 O IPU EMIFB SDRAM chip select 0
EMB_WE_DQM[1] /GP5[14] 85 O IPU GPIO EMIFB write enable/data mask for EMB_D
EMB_WE_DQM[0] /GP5[15] 60 O IPU
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.5 Serial Peripheral Interface Modules (SPI0, SPI1)

Table 3-7 Serial Peripheral Interface (SPI) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
SPI0
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 I/O IPU UART0, EQEP0B, GPIO, BOOT SPI0 chip select
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 I/O IPU UART0, EQEP0A, GPIO, BOOT SPI0 enable
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 I/O IPD eQEP1, GPIO, BOOT SPI0 clock
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 I/O IPD eQEP0, GPIO, BOOT SPI0 data slave-in-master-out
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 I/O IPD SPI0 data slave-out-master-in
SPI1
SPI1_SCS[0] /UART2_TXD/GP5[13] 8 I/O IPU UART2, GPIO SPI1 chip select
SPI1_ENA /UART2_RXD/GP5[12] 7 I/O IPU SPI1 enable
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 I/O IPD eQEP1, GPIO, BOOT SPI1 clock
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 I/O IPU I2C1, GPIO, BOOT SPI1 data slave-in-master-out
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 I/O IPU SPI1 data slave-out-master-in
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.6 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)

The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed.

Table 3-8 Enhanced Capture Module (eCAP) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
eCAP0
ACLKX0/ECAP0/APWM0/GP2[12] 126 I/O IPD McASP0, GPIO enhanced capture 0 input or auxiliary PWM 0 output
eCAP1
ACLKR0/ECAP1/APWM1/GP2[15] 130 I/O IPD McASP0, GPIO enhanced capture 1 input or auxiliary PWM 1 output
eCAP2
ACLKR1/ECAP2/APWM2/GP4[12] 165 I/O IPD McASP1, GPIO enhanced capture 2 input or auxiliary PWM 2 output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.7 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)

Table 3-9 Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
eHRPWM0
ACLKX1/EPWM0A/GP3[15] 162 I/O IPD McASP1, GPIO eHRPWM0 A output (with high-resolution)
AHCLKX1/EPWM0B/GP3[14] 160 I/O IPD eHRPWM0 B output
AMUTE1/EPWMTZ/GP4[14] 132 I/O IPD McASP1, eHRPWM1, GPIO, eHRPWM2 eHRPWM0 trip zone input
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 I/O IPD McASP1, eHRPWM0, GPIO Sync input to eHRPWM0 module or sync output to external PWM
eHRPWM1
AXR1[8]/EPWM1A/GP4[8] 168 I/O IPD McASP1, GPIO eHRPWM1 A (with high-resolution)
AXR1[7]/EPWM1B/GP4[7] 169 I/O IPD eHRPWM1 B output
AMUTE1/EPWMTZ/GP4[14] 132 I/O IPD McASP1, eHRPWM0, GPIO, eHRPWM2 eHRPWM1 trip zone input
eHRPWM2
AXR1[6]/EPWM2A/GP4[6] 170 I/O IPD McASP1, GPIO eHRPWM2 A (with high-resolution)
AXR1[5]/EPWM2B/GP4[5] 171 I/O IPD eHRPWM2 B output
AMUTE1/EPWMTZ/GP4[14] 132 I/O IPD McASP1, eHRPWM0, GPIO, eHRPWM2 eHRPWM2 trip zone input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.8 Enhanced Quadrature Encoder Pulse Module (eQEP)

Table 3-10 Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
eQEP0
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 I IPU SPIO, UART0, GPIO, BOOT eQEP0A quadrature input
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 I IPU eQEP0B quadrature input
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 I IPD SPI0, GPIO, BOOT eQEP0 index
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 I IPD eQEP0 strobe
eQEP1
AXR1[3]/EQEP1A/GP4[3] 174 I IPD McASP1, GPIO eQEP1A quadrature input
AXR1[4]/EQEP1B/GP4[4] 173 I IPD eQEP1B quadrature input
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 I IPD SPI0, GPIO, BOOT eQEP1 index
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 I IPD SPI1, GPIO, BOOT eQEP1 strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.9 Boot

Table 3-11 Boot Terminal Functions(3)

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
EMA_CS[2]/GP2[5]/BOOT[15] 23 I IPU EMIFA, GPIO Boot Selection Signals
EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 I IPU EMIFA, McASP0, GPIO
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 I IPU EMIFA, MMC/SD, GPIO
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 I IPU
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 I IPD McASP0, EMAC, GPIO
AFSX0/GP2[13]/BOOT[10] 127 I IPD McASP0, GPIO
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 I IPU UART0, I2C0, Timer0, GPIO
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I IPU UART0, I2C0, Timer0, GPIO
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 I IPD SPI1, eQEP1, GPIO
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 I IPU SPI1, I2C1, GPIO
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 I IPU
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 I IPU SPI0, UART0, eQEP0, GPIO
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 I IPU SPI0, UART0, eQEP0, GPIO
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 I IPD SPIO, eQEP1, GPIO
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 I IPD SPI0, eQEP0, GPIO
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 I IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Boot decoding will be defined in the ROM datasheet.

3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)

Table 3-12 Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
UART0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I IPU I2C0, BOOT, Timer0, GPIO, UART0 receive data
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 O IPU I2C0, Timer0, GPIO, BOOT UART0 transmit data
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4] 9 O IPU SPIO, eQEP0, GPIO, BOOT UART0 ready-to-send output
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3] 12 I IPU UART0 clear-to-send input
UART1
UART1_RXD/AXR0[9]/GP3[9](3) 122 I IPD McASP0, GPIO UART1 receive data
UART1_TXD/AXR0[10]/GP3[10](3) 123 O IPD UART1 transmit data
UART2
SPI1_ENA/UART2_RXD/GP5[12] 7 I IPU SPI1, GPIO UART2 receive data
SPI1_SCS[0]/UART2_TXD/GP5[13] 8 O IPU UART2 transmit data
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if UART1 boot mode is used.

3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)

Table 3-13 Inter-Integrated Circuit (I2C) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
I2C0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I/O IPU UART0, Timer0, GPIO, BOOT I2C0 serial data
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 I/O IPU UART0, Timer0, GPIO, BOOT I2C0 serial clock
I2C1
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 I/O IPU SPI1, GPIO, BOOT I2C1 serial data
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 I/O IPU I2C1 serial clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.12 Timers

Table 3-14 Timers Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 I IPU UART0, I2C0, GPIO, BOOT Timer0 lower input
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 O IPU Timer0 lower output
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)

Table 3-15 Multichannel Audio Serial Ports (McASPs) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
McASP0
EMA_OE/AXR0[13]/GP2[7] 22 I/O IPU EMIFA, GPIO McASP0 serial data
EMA_WE/AXR0[12]/GP2[3]/BOOT[14] 55 I/O IPU EMIFA, GPIO, BOOT
AXR0[11] / GP3[11] 124 I/O IPD McASP2, GPIO
UART1_TXD/AXR0[10]/GP3[10] 123 I/O IPD GPIO
UART1_RXD/AXR0[9]/GP3[9] 122 I/O IPD GPIO
AXR0[8]/MDIO_D/GP3[8] 121 I/O IPU MDIO, GPIO
AXR0[7]/MDIO_CLK/GP3[7] 120 I/O IPD
AXR0[6]/RMII_RXER/GP3[6] 118 I/O IPD EMAC, GPIO
AXR0[5]/RMII_RXD[1]/GP3[5] 117 I/O IPD
AXR0[4]/RMII_RXD[0]/GP3[4] 116 I/O IPD
AXR0[3]/RMII_CRS_DV/GP3[3] 115 I/O IPD
AXR0[2]/RMII_TXEN/GP3[2] 113 I/O IPD
AXR0[1]/RMII_TXD[1]/GP3[1] 112 I/O IPD
AXR0[0]/RMII_TXD[0]/GP3[0] 111 I/O IPD
AHCLKX0/USB_REFCLKIN/GP2[11] 125 I/O IPD USB, GPIO McASP0 transmit master clock
ACLKX0/ECAP0/APWM0/GP2[12] 126 I/O IPD eCAP0, GPIO McASP0 transmit bit clock
AFSX0/GP2[13]/BOOT[10] 127 I/O IPD GPIO, BOOT McASP0 transmit frame sync
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 I/O IPD EMAC, GPIO, BOOT McASP0 receive master clock
ACLKR0/ECAP1/APWM1/GP2[15] 130 I/O IPD eCAP1, GPIO McASP0 receive bit clock
AFSR0/GP3[12] 131 I/O IPD GPIO McASP0 receive frame sync
McASP1
AXR1[11]/GP5[11] 6 I/O IPU GPIO McASP1 serial data
AXR1[10]/GP5[10] 4 I/O IPU
AXR1[8]/EPWM1A/GP4[8] 168 I/O IPD eHRPWM1 A, GPIO
AXR1[7]/EPWM1B/GP4[7] 169 I/O IPD eHRPWM1 B, GPIO
AXR1[6]/EPWM2A/GP4[6] 170 I/O IPD eHRPWM2 A, GPIO
AXR1[5]/EPWM2B/GP4[5] 171 I/O IPD eHRPWM2 B, GPIO
AXR1[4]/EQEP1B/GP4[4] 173 I/O IPD eQEP, GPIO
AXR1[3]/EQEP1A/GP4[3] 174 I/O IPD
AXR1[2]/GP4[2] 175 I/O IPD GPIO
AXR1[1]/GP4[1] 176 I/O IPD
AXR1[0]/GP4[0] 1 I/O IPD
AHCLKX1/EPWM0B/GP3[14] 160 I/O IPD eHRPWM0, GPIO McASP1 transmit master clock
ACLKX1/EPWM0A/GP3[15] 162 I/O IPD eHRPWM0, GPIO McASP1 transmit bit clock
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 I/O IPD eHRPWM0, GPIO McASP1 transmit frame sync
ACLKR1/ECAP2/APWM2/GP4[12] 165 I/O IPD eCAP2, GPIO McASP1 receive bit clock
AFSR1/GP4[13] 166 I/O IPD GPIO McASP1 receive frame sync
AMUTE1/EPWMTZ/GP4[14] 132 O IPD eHRPWM0, eHRPWM1, eHRPWM2, GPIO McASP1 mute output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.14 Universal Serial Bus Modules (USB0)

Table 3-16 Universal Serial Bus (USB) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) DESCRIPTION
PTP
USB0 2.0 OTG (USB0)
USB0_DM 138 A USB0 PHY data minus
USB0_DP 137 A USB0 PHY data plus
USB0_VDDA33 140 PWR USB0 PHY 3.3-V supply
USB0_VDDA18 135 PWR USB0 PHY 1.8-V supply input
USB0_VDDA12(3) 134 PWR USB0 PHY 1.2-V LDO output for bypass cap.
For proper device operation, this pin is recommended to be connected via a 0.22 μF capacitor to VSS (GND), even if USB0 is not being used.
AHCLKX0/USB_REFCLKIN/GP2[11] 125 I IPD USB_REFCLKIN. Optional clock input.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 uF capacitor to VSS.

3.6.15 Ethernet Media Access Controller (EMAC)

Table 3-17 Ethernet Media Access Controller (EMAC) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
RMII
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 I/O IPD McASP0, GPIO, BOOT EMAC 50-MHz clock input or output
AXR0[6]/RMII_RXER/GP3[6] 118 I IPD McASP0, GPIO EMAC RMII receiver error
AXR0[5]/RMII_RXD[1]/GP3[5] 117 I IPD EMAC RMII receive data
AXR0[4]/RMII_RXD[0]/GP3[4] 116 I IPD
AXR0[3]/RMII_CRS_DV/GP3[3] 115 I IPD EMAC RMII carrier sense data valid
AXR0[2]/RMII_TXEN/GP3[2] 113 O IPD EMAC RMII transmit enable
AXR0[1]/RMII_TXD[1]/GP3[1] 112 O IPD EMAC RMII trasmit data
AXR0[0]/RMII_TXD[0]/GP3[0] 111 O IPD
MDIO
AXR0[8]/MDIO_D/GP3[8] 121 I/O IPU McASP0, GPIO MDIO data clock
AXR0[7]/MDIO_CLK/GP3[7] 120 O IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.16 Multimedia Card/Secure Digital (MMC/SD)

Table 3-18 Multimedia Card/Secure Digital (MMC/SD) Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP
EMA_A[1]/MMCSD_CLK/GP1[1] 30 O IPU EMIFA, GPIO MMCSD Clock
EMA_A[2]/MMCSD_CMD/GP1[2] 31 I/O IPU MMCSD Command
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13] 54 I/O IPU EMIFA, GPIO, BOOT MMC/SD data
EMA_D[6]/MMCSD_DAT[6]/GP0[6] 52 I/O IPU EMIFA, GPIO
EMA_D[5]/MMCSD_DAT[5]/GP0[5] 51 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/GP0[4] 49 I/O IPU
EMA_D[3]/MMCSD_DAT[3]/GP0[3] 48 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/GP0[2] 46 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/GP0[1] 45 I/O IPU
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12] 44 I/O IPU EMIFA, GPIO, BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

3.6.17 Reserved and No Connect

Table 3-19 Reserved and No Connect Terminal Functions

SIGNAL NAME PIN NO TYPE(1) DESCRIPTION
PTP
RSV2 133 - Reserved. For proper device operation, this pin must be tied directly to CVDD.
RSV3 149 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD or left unconnected [do not connect to ground (VSS)].
RSV4 148 I Reserved. For proper device operation, this pin must be tied low or to CVDD.
NC 136 - No Connect (leave unconnected)
NC 139 - No Connect (leave unconnected)
(1) PWR = Supply voltage.

3.6.18 Supply and Ground

Table 3-20 Supply and Ground Terminal Functions

SIGNAL NAME PIN NO TYPE(1) DESCRIPTION
PTP
CVDD (Core supply) 10, 20, 28, 38, 50, 56, 61, 69, 77, 93, 104, 114, 147, 154, 161, 167 PWR Core supply voltage pins
RVDD (Internal RAM supply) 67, 159 PWR Internal ram supply voltage pins
DVDD (I/O supply) 5, 15, 24, 33, 43, 47, 53, 58, 65, 71, 75, 81, 87, 90, 99, 109, 119, 128, 151, 158, 164, 172 PWR I/O supply voltage pins
VSS (Ground) 177 GND Ground pins
(1) PWR = Supply voltage, GND - Ground.

3.6.19 Unused USB0 (USB2.0) Pin Configurations

Table 3-21 Unused USB0 Pin Configurations

SIGNAL NAME Configuration
(When USB0 is not used)
USB0_DM No connect
USB0_DP No connect
USB0_VDDA33 No connect
USB0_VDDA18 No connect
USB0_VDDA12 Internal USB0 PHY output connected to an external 0.22μF filter capacitor, even if USB0 is not used.
AHCLKX0/USB_REFCLKIN/
GP2[11]		 No connect or use as alternate function