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Product details

Parameters

Arm MHz (Max.) 375, 456 DRAM SDRAM Arm CPU Arm9 Ethernet MAC 10/100 USB 1 SPI 2 I2C 2 Operating temperature range (C) -40 to 105, -40 to 90, 0 to 90 Serial I/O McASP, SPI, I2C, UART UART 3 open-in-new Find other Other Sitara processors

Package | Pins | Size

HLQFP (PTP) 176 676 mm² 26 x 26 open-in-new Find other Other Sitara processors

Features

  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interface)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-Bit-Wide Data)
      • NAND (8-Bit-Wide Data)
    • EMIFB
      • 16-Bit SDRAM With 128-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled Through Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 Full-Speed Client
    • USB 2.0 Full- and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • Two Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 176-Pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
  • Commercial, Industrial, or Extended Temperature

All trademarks are the property of their respective owners.

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Description

The AM1705 is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are 4-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; three multichannel audio serial ports (McASPs) with serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The I2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers and a Windows® debugger interface for visibility into source code execution.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 31
Type Title Date
* Datasheet AM1705 ARM® Microprocessor datasheet (Rev. F) Jan. 31, 2017
* Errata AM1705 ARM Microprocessor Silicon Errata (Silicon Revisions 3.0, 2.1, and 2.0) (Rev. E) Jun. 17, 2014
Technical articles How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory Aug. 24, 2020
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Y) Feb. 04, 2020
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. V) Feb. 04, 2020
Technical articles Designing smarter remote terminal units for microgrids Oct. 02, 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) Jun. 03, 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) Jun. 03, 2019
Technical articles Security versus functional safety: a view from the Processor Software Development Kit May 31, 2019
Application note General Hardware Design/BGA PCB Design/BGA Feb. 22, 2019
Application note OMAP-L13x / C674x / AM1x schematic review guidelines Feb. 14, 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) Nov. 19, 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) Nov. 19, 2018
Technical articles Simplified software development through the Processor SDK and tools Oct. 02, 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS Sep. 24, 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) Jan. 16, 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) Jan. 16, 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) Sep. 30, 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) Sep. 30, 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) Jun. 21, 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) Jun. 21, 2017
User guide AM1705 ARM Microprocessor Technical Reference Manual (Rev. D) Sep. 21, 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) Apr. 30, 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) Apr. 30, 2016
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) Nov. 05, 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) Nov. 05, 2014
Application note Using the AM17xx Bootloader (Rev. C) May 31, 2012
Application note Powering the AM1705 and AM1707 With the TPS650061 (Rev. A) Oct. 18, 2011
Application note AM17x Power Consumption Summary Jun. 30, 2010
Application note AM17xx Pin Multiplexing Utility Mar. 01, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DEBUG PROBE Download
XDS200 USB Debug Probe
TMDSEMU200-U
295
Description

The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBE Download
995
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBE Download
1495
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

SOFTWARE DEVELOPMENT KIT (SDK) Download
Linux EZ Software Development Kit (EZSDK) for Sitara™ Processors
LINUXEZSDK-SITARA SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

Features

The Sitara Linux SDK features:

  • Open Linux support
  • GUI-based application launcher
  • 3-D graphics support
  • Example application with available source code

The Linux SDK includes the following components:

  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • Application launcher
  • 3D graphics (...)
SOFTWARE DEVELOPMENT KIT (SDK) Download
Windows® Embedded Compact/CE SDK - ARM9™-based AM18x, OMAP-L13x Processor
WINCESDK-AM1XOMAPL1X Microsoft Windows Embedded Compact (WEC7) and CE (WinCE 6.0) operating systems are optimized for embedded devices that require minimum storage based on a componentized architecture.

WinCE BSPs for ARM9-based processors are now available from Adeneo Embedded.

IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors
CCSTUDIO-SITARA

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

Design tools & simulation

SIMULATION MODEL Download
SPRM490.ZIP (5 KB) - BSDL Model
SIMULATION MODEL Download
SPRM491A.ZIP (109 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Powering the AM1705 and AM1707 with the TPS650061
PR1061 — Low cost integrated power solution for AM17xx processors
Design files

CAD/CAE symbols

Package Pins Download
HLQFP (PTP) 176 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

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