8.2.2.1 Board Designs

TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-3 and Figure 8-1.

1. This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and operating frequency (see the DDR3 memory device data sheet).

Figure 8-1 DDR3 Memory Controller Clock Timing

8.2.2.2 DDR3 EMIF

The processor contains one DDR3 EMIF.

8.2.2.3 DDR3 Device Combinations

Because there are several possible combinations of device counts and single- or dual-side mounting, Table 8-4 summarizes the supported device configurations.

1. Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of the board.
2. This is two mirrored pairs of DDR3 devices.
3. Three or five DDR3 device combination is not available on this device, but combination types are retained for consistency with the AM57xx family of devices.

8.2.2.4 DDR3 Interface Schematic

8.2.2.4.2 16-Bit DDR3 Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-2 and Figure 8-3); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection against external electrical noise causing activity on the signals.

The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.

Figure 8-2 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices

Figure 8-3 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices

8.2.2.5 Compatible JEDEC DDR3 Devices

Table 8-5 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface. Generally, the DDR3 interface is compatible with DDR3-1333 devices in the x8 or x16 widths.

1. Refer to Table 8-3 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of supported DDR clock rates.
2. For valid DDR3 device configurations and device counts, see Section 8.2.2.4, Figure 8-2, and Figure 8-3.

8.2.2.6 PCB Stackup

The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-6. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in Table 8-7.

1. Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers.
2. No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation.
3. Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
4. An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape.
5. Z is the nominal singled-ended impedance selected for the PCB specified by PS9.

8.2.2.7 Placement

Figure 8-4 shows the required placement for the processor as well as the DDR3 devices. The dimensions for this figure are defined in Table 8-8. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3 devices are omitted from the placement.

Figure 8-4 Placement Specifications

1. DDR3 keepout region to encompass entire DDR3 routing area.
2. Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
3. If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be separated by this specification.

8.2.2.8 DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 8-5. The size of this region varies with the placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-8. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region. Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the two signals from the DDR3 controller should be separated from each other by the specification in Table 8-8, (see KOD37).

Figure 8-5 DDR3 Keepout Region

8.2.2.9 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 8-9 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk bypass capacitance may be needed for other circuitry.

1. These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass capacitors and DDR3 signal routing.

8.2.2.10 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 8-10 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 8-10.

1. LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
2. Closer/shorter is better.
3. Measured from the nearest processor power/ground ball to the center of the capacitor package.
4. Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls, between the DDR interfaces on the package.
5. See the Via Channel™ escape for the processor package.
6. Measured from the DDR3 device power/ground ball to the center of the capacitor package.
7. Per DDR3 device.
8. An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
9. An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
10. Up to a total of two pairs of DDR power/ground balls may share a via.
11. The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.

8.2.2.11 Net Classes

Table 8-11 lists the clock net classes for the DDR3 interface. Table 8-12 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination and routing rules that follow.

1. Only used on 32-bit wide DDR3 memory systems.

1. Only used on 32-bit wide DDR3 memory systems.

8.2.2.12 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in the routing rules in the following sections.

8.2.2.13 VREF_DDR Routing

ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing congestion.

8.2.2.14 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.

8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following subsections show the topology and routing for various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the terms for the routing specification detailed in Table 8-13.

8.2.2.15.1 Four DDR3 Devices

Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices

Figure 8-6 shows the topology of the CK net classes and Figure 8-7 shows the topology for the corresponding ADDR_CTRL net classes.

Figure 8-6 CK Topology for Four x8 DDR3 Devices

Figure 8-7 ADDR_CTRL Topology for Four x8 DDR3 Devices

8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices

Figure 8-8 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-9 shows the corresponding ADDR_CTRL routing.

Figure 8-8 CK Routing for Four Single-Side DDR3 Devices

Figure 8-9 ADDR_CTRL Routing for Four Single-Side DDR3 Devices

To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of increased routing and assembly complexity. Figure 8-10 and Figure 8-11 show the routing for CK and ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.

Figure 8-10 CK Routing for Four Mirrored DDR3 Devices

Figure 8-11 ADDR_CTRL Routing for Four Mirrored DDR3 Devices

8.2.2.15.2 Two DDR3 Devices

Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices

Figure 8-12 shows the topology of the CK net classes and Figure 8-13 shows the topology for the corresponding ADDR_CTRL net classes.

Figure 8-12 CK Topology for Two DDR3 Devices

Figure 8-13 ADDR_CTRL Topology for Two DDR3 Devices

8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices

Figure 8-14 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-15 shows the corresponding ADDR_CTRL routing.

Figure 8-14 CK Routing for Two Single-Side DDR3 Devices

Figure 8-15 ADDR_CTRL Routing for Two Single-Side DDR3 Devices

To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 8-16 and Figure 8-17 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration.

Figure 8-16 CK Routing for Two Mirrored DDR3 Devices

Figure 8-17 ADDR_CTRL Routing for Two Mirrored DDR3 Devices

8.2.2.15.3 One DDR3 Device

A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as one bank (CS), 16 bits wide.

8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device

Figure 8-18 shows the topology of the CK net classes and Figure 8-19 shows the topology for the corresponding ADDR_CTRL net classes.

Figure 8-18 CK Topology for One DDR3 Device

Figure 8-19 ADDR_CTRL Topology for One DDR3 Device

8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device

Figure 8-20 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-21 shows the corresponding ADDR_CTRL routing.

Figure 8-20 CK Routing for One DDR3 Device

Figure 8-21 ADDR_CTRL Routing for One DDR3 Device

8.2.2.16 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point to point, so its definition is simple.

Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure there are nearby ground vias to allow the return currents to transition between reference planes if both reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return currents to transition between reference planes if one of the reference planes is ground. The goal is to minimize the size of the return current loops.

8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-22 and Figure 8-23 show these topologies.

Figure 8-22 DQS Topology

Figure 8-23 DQ/DM Topology

8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices

Figure 8-24 and Figure 8-25 show the DQS and DQ/DM routing.

Figure 8-24 DQS Routing With Any Number of Allowed DDR3 Devices

Figure 8-25 DQ/DM Routing With Any Number of Allowed DDR3 Devices

8.2.2.17 Routing Specification

8.2.2.17.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 8-26 and Figure 8-27 show this distance for four loads and two loads, respectively. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-13.

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-26 CACLM for Four Address Loads on One Side of PCB

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-27 CACLM for Two Address Loads on One Side of PCB

Table 8-13 CK and ADDR_CTRL Routing Specification⁽²⁾⁽³⁾

NO.	PARAMETER	MIN	TYP	MAX	UNIT
CARS31	A1+A2 length			500(1)	ps
CARS32	A1+A2 skew			29	ps
CARS33	A3 length			125	ps
CARS34	A3 skew(4)			6	ps
CARS35	A3 skew(5)			6	ps
CARS36	A4 length			125	ps
CARS37	A4 skew			6	ps
CARS38	AS length		5(1)	17	ps
CARS39	AS skew		1.3(1)	14	ps
CARS310	AS+/AS- length		5	12	ps
CARS311	AS+/AS- skew			1	ps
CARS312	AT length(6)		75		ps
CARS313	AT skew(7)		14		ps
CARS314	AT skew(8)			1	ps
CARS315	CK/ADDR_CTRL trace length			1020	ps
CARS316	Vias per trace			3(1)	vias
CARS317	Via count difference			1(15)	vias
CARS318	Center-to-center CK to other DDR3 trace spacing(9)	4w
CARS319	Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)	4w
CARS320	Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(9)	3w
CARS321	CK center-to-center spacing(11) (12)
CARS322	CK spacing to other net(9)	4w
CARS323	Rcp(13)	Zo-1	Zo	Zo+1	Ω
CARS324	Rtt(13)(14)	Zo-5	Zo	Zo+5	Ω

1. Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rice time and fall time confirms desired operation.
2. The use of vias should be minimized.
3. Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
4. Non-mirrored configuration (all DDR3 memories on same side of PCB).
5. Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
6. While this length can be increased for convenience, its length should be minimized.
7. ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
8. CK net class only.
9. Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
10. The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
11. CK spacing set to ensure proper differential impedance.
12. The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo.
13. Source termination (series resistor at driver) is specifically not allowed.
14. Termination values should be uniform across the net class.
15. Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.

8.2.2.17.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL, a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 8-28 shows this distance for four loads. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-14.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3

Figure 8-28 DQLM for Any Number of Allowed DDR3 Devices

Table 8-14 Data Routing Specification⁽²⁾

NO.	PARAMETER	MIN	TYP	MAX	UNIT
DRS31	DB0 length			340	ps
DRS32	DB1 length			340	ps
DRS33	DB2 length			340	ps
DRS34	DB3 length			340	ps
DRS35	DBn skew(3)			5	ps
DRS36	DQSn+ to DQSn- skew			1	ps
DRS37	DQSn to DBn skew(3)(4)			5(10)	ps
DRS38	Vias per trace			2(1)	vias
DRS39	Via count difference			0(10)	vias
DRS310	Center-to-center DBn to other DDR3 trace spacing(6)	4			w(5)
DRS311	Center-to-center DBn to other DBn trace spacing(7)	3			w(5)
DRS312	DQSn center-to-center spacing(8) (9)
DRS313	DQSn center-to-center spacing to other net	4			w(5)

1. Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rice time and fall time confirms desired operation.
2. External termination disallowed. Data termination should use built-in ODT functionality.
3. Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
4. Each DQS pair is length matched to its associated byte.
5. Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
6. Other DDR3 trace spacing means other DDR3 net classes not within the byte.
7. This applies to spacing within the net classes of a byte.
8. DQS pair spacing is set to ensure proper differential impedance.
9. The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo.
10. Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.