SPRS999 August   2017 AM5718-HIREL

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Device Comparison Table
  4. Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem - Video Output Ports
      3. 4.4.3  Display Subsystem - High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power On Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY-1.5 V and 1.8 V
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
      4. 7.23.4 GMAC RGMII Timings
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Single-Ended Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 QSPI Board Design and Layout Guidelines
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
  9. Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical Packaging and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZBO|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements and Switching Characteristics

Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions unless otherwise specified.

Interface Clock Specifications

Interface Clock Terminology

The interface clock is used at the system level to sequence the data and/or to control transfers accordingly with the interface protocol.

Interface Clock Frequency

The two interface clock characteristics are:

  • The maximum clock frequency
  • The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the Device IC and does not take into account any system consideration (PCB, peripherals).

The system designer will have to consider these system considerations and the Device IC timing characteristics as well to define properly the maximum operating frequency that corresponds to the maximum frequency supported to transfer the data on this interface.

Timing Parameters and Information

The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other related terminologies have been abbreviated as follows:

Table 7-1 Timing Parameters

SUBSCRIPTS
SYMBOL PARAMETER
c Cycle time (period)
d Delay time
dis Disable time
en Enable time
h Hold time
su Setup time
START Start bit
t Transition time
v Valid time
w Pulse duration (width)
X Unknown, changing, or don't care level
F Fall time
H High
L Low
R Rise time
V Valid
IV Invalid
AE Active Edge
FE First Edge
LE Last Edge
Z High impedance

Parameter Information

AM5718-HIREL pm_tstcirc_prs403.gif Figure 7-1 Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals.

This load capacitance value does not indicate the maximum load the device is capable of driving.

1.8V and 3.3V Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD I/O)/2.

AM5718-HIREL pm_io_volt_prs403.gif Figure 7-2 Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks.

AM5718-HIREL pm_transvolt_prs403.gif Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels

1.8V and 3.3V Signal Transition Rates

The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed timings, unless specific instructions otherwise are given in the individual timing sub-sections of the datasheet.

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routes. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input transitions are more susceptible to glitches due to noise and special care should be taken for slow input clocks.

Virtual and Manual I/O Timing Modes

Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing Modes. Table 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device interfaces. The individual interface timing sections found later in this document provide the full description of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.

Table 7-2 Modes Summary

Virtual or Manual IO Mode Name Data Manual Timing Mode
DPI Video Output
No Virtual or Manual IO Timing Mode Required DPI1/3 Video Output Default Timings - Rising-edge Clock Reference
DSS_VIRTUAL1 DPI1/3 Video Output Default Timings - Falling-edge Clock Reference
VOUT1_MANUAL1 DPI1 Video Output Alternate Timings
VOUT2_IOSET1_MANUAL1 DPI2 Video Output IOSET1 Alternate Timings
VOUT2_IOSET1_MANUAL2 DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET1_MANUAL3 DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
VOUT2_IOSET2_MANUAL1 DPI2 Video Output IOSET2 Alternate Timings
VOUT2_IOSET2_MANUAL2 DPI2 Video Output IOSET2 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET2_MANUAL3 DPI2 Video Output IOSET2 Default Timings - Falling-edge Clock Reference
VOUT3_MANUAL1 DPI3 Video Output Alternate Timings
GPMC
No Virtual or Manual IO Timing Mode Required GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings
GPMC_VIRTUAL1 GPMC Synchronous Mode - Alternate Timings
McASP
No Virtual or Manual IO Timing Mode Required McASP1 Asynchronous and Synchronous Transmit Timings
MCASP1_VIRTUAL1_SYNC_RX See Table 7-52
MCASP1_VIRTUAL2_ASYNC_RX See Table 7-52
No Virtual or Manual IO Timing Mode Required McASP2 Asynchronous and Synchronous Transmit Timings
MCASP2_VIRTUAL1_SYNC_RX_80M See Table 7-53
MCASP2_VIRTUAL2_ASYNC_RX See Table 7-53
MCASP2_VIRTUAL3_SYNC_RX See Table 7-53
MCASP2_VIRTUAL4_ASYNC_RX_80M See Table 7-53
No Virtual or Manual IO Timing Mode Required McASP3 Synchronous Transmit Timings
MCASP3_VIRTUAL2_SYNC_RX See Table 7-54
No Virtual or Manual IO Timing Mode Required McASP4 Synchronous Transmit Timings
MCASP4_VIRTUAL1_SYNC_RX See Table 7-55
No Virtual or Manual IO Timing Mode Required McASP5 Synchronous Transmit Timings
MCASP5_VIRTUAL1_SYNC_RX See Table 7-56
No Virtual or Manual IO Timing Mode Required McASP6 Synchronous Transmit Timings
MCASP6_VIRTUAL1_SYNC_RX See Table 7-57
No Virtual or Manual IO Timing Mode Required McASP7 Synchronous Transmit Timings
MCASP7_VIRTUAL2_SYNC_RX See Table 7-58
No Virtual or Manual IO Timing Mode Required McASP8 Synchronous Transmit Timings
MCASP8_VIRTUAL1_SYNC_RX See Table 7-59
eMMC/SD/SDIO
No Virtual or Manual IO Timing Mode Required MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12 (Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and Pad Loopback) Timings
MMC1_VIRTUAL1 MMC1 SDR50 (Pad Loopback) Timings
MMC1_VIRTUAL4 MMC1 DS (Internal Loopback) Timings
MMC1_VIRTUAL5 MMC1 SDR50 (Internal Loopback) Timings
MMC1_VIRTUAL6 MMC1 DDR50 (Internal Loopback) Timings
MMC1_MANUAL1 MMC1 DDR50 (Pad Loopback) Timings
MMC1_MANUAL2 MMC1 SDR104 Timings
No Virtual or Manual IO Timing Mode Required MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings
MMC2_VIRTUAL2 MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings
MMC2_MANUAL1 MMC2 DDR (Pad Loopback) Timings
MMC2_MANUAL2 MMC2 DDR (Internal Loopback) Timings
MMC2_MANUAL3 MMC2 HS200 Timings
No Virtual or Manual IO Timing Mode Required MMC3 DS, SDR12, HS, SDR25 Timings
MMC3_MANUAL1 MMC3 SDR50 Timings
No Virtual or Manual IO Timing Mode Required MMC4 DS, SDR12, HS, SDR25 Timings
QSPI
No Virtual or Manual IO Timing Mode Required QSPI Mode 3 Timings
QSPI1_MANUAL1 QSPI Mode 0 Timings
GMAC
No Virtual or Manual IO Timing Mode Required GMAC MII0/1 Timings
GMAC_RGMII0_MANUAL1 GMAC RGMII0 with Transmit Clock Internal Delay Enabled
GMAC_RGMII1_MANUAL1 GMAC RGMII1 with Transmit Clock Internal Delay Enabled
GMAC_RMII0_MANUAL1 GMAC RMII0 Timings
GMAC_RMII1_MANUAL1 GMAC RMII1 Timings
VIP
VIP_MANUAL1 VIN1A (IOSET7) and VIN2A (IOSET10) Rise-Edge Capture Mode Timings
VIP_MANUAL2 VIN1A (IOSET7) and VIN2A (IOSET10) Fall-Edge Capture Mode Timings
VIP_MANUAL3 VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIP_MANUAL4 VIN2B (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIP_MANUAL5 VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIP_MANUAL6 VIN2B (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL7 VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) Rise-Edge Capture Mode Timings
VIP_MANUAL8 VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIP_MANUAL9 VIN1B (IOSET6/7) Rise-Edge Capture Mode Timings
VIP_MANUAL10 VIN1B (IOSET5) and VIN2B (IOSET2/11) Rise-Edge Capture Mode Timings
VIP_MANUAL11 VIN1B (IOSET5) and VIN2B (IOSET2/11) Fall-Edge Capture Mode Timings
VIP_MANUAL12 VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) Fall-Edge Capture Mode Timings
VIP_MANUAL13 VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL14 VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIP_MANUAL15 VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIP_MANUAL16 VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
PRU-ICSS
No Virtual or Manual IO Timing Mode Required All PRU_ICSS Modes not covered below
PR1_PRU1_DIR_IN_MANUAL PRU-ICSS1 PRU1 Direct Input Mode Timings
PR1_PRU1_DIR_OUT_MANUAL PRU-ICSS1 PRU1 Direct Output Mode Timings
PR1_PRU1_PAR_CAP_MANUAL PRU-ICSS1 PRU1 Parallel Capture Mode Timings
PR2_PRU0_DIR_IN_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Direct Input Mode Timings
PR2_PRU0_DIR_IN_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Input Mode Timings
PR2_PRU0_DIR_OUT_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Direct Output Mode Timings
PR2_PRU0_DIR_OUT_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Output Mode Timings
PR2_PRU1_DIR_IN_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Input Mode Timings
PR2_PRU1_DIR_IN_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings
PR2_PRU1_DIR_OUT_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Output Mode Timings
PR2_PRU1_DIR_OUT_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings
PR2_PRU0_PAR_CAP_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Parallel Capture Mode Timings
PR2_PRU0_PAR_CAP_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode Timings
PR2_PRU1_PAR_CAP_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode Timings
PR2_PRU1_PAR_CAP_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA, INTC, MLB
No Virtual or Manual IO Timing Mode Required All Modes

Video Input Ports (VIP)

The Device includes 1 Video Input Ports (VIP)

Table 7-3, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs.

CAUTION

The I/O timings provided in this section are valid only for VIN1 and VIN2 if signals within a single IOSET are used. The IOSETs are defined in Table 7-4.

Table 7-3 Timing Requirements for VIP (3)(4)(5)

NO. PARAMETER DESCRIPTION MIN MAX UNIT
V1 tc(CLK) Cycle time, vinx_clki (3) (5) 6.06 (2) ns
V2 tw(CLKH) Pulse duration, vinx_clki high (3) (5) 0.45*P (2) ns
V3 tw(CLKL) Pulse duration, vinx_clki low (3) (5) 0.45*P (2) ns
V4 tsu(CTL/DATA-CLK) Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3) (4) (5) 3.11 (2) ns
V6 th(CLK-CTL/DATA) Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition (3) (4) (5) -0.05 (2) ns
  1. For maximum frequency of 165 MHz.
  2. P = vinx_clki period.
  3. x in vinx = 1a, 1b, 2a, 2b.
  4. n in dn = 0 to 7 when x = 1b, 2b.
    n = 0 to 23 when x = 1a, 2a.
  5. i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
AM5718-HIREL SPRS906_TIMING_VIP_01.gif Figure 7-4 Video Input Ports clock signal
AM5718-HIREL SPRS906_TIMING_VIP_02.gif Figure 7-5 Video Input Ports timings

In Table 7-4 and Table 7-5 are presented the specific groupings of signals (IOSET) for use with vin1 and vin2.

Table 7-4 VIN1 IOSETs

SIGNALS IOSET2 IOSET3 IOSET4 (1) IOSET5 (1) IOSET6 (1) IOSET7 (1) IOSET8 IOSET9 IOSET10
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin1a
vin1a_clk0 P1 2 B11 4 B11 3 P4 4 P4 4 B26 8 AC5 9 E17 7 E17 7
vin1a_hsync0 N7 2 C11 4 C11 3 R3 4 P7 4 E21 8 AB8 9 F12 7 F12 7
vin1a_vsync0 R4 2 E11 4 E11 3 T2 4 N1 4 F20 8 AB5 9 G12 7 G12 7
vin1a_fld0 P9 2 D11 4 D11 3 P9 4 J7 4 F21 8 C17 9 C14 7 C14 7
vin1a_de0 N9 2 B10 4 B10 3 P7 5 H6 4 C23 8 AB4 9 D14 7 D14 7
vin1a_d0 M6 2 B7 4 B7 3 R6 4 R6 4 B14 8 AD6 9 D18 7 C17 7
vin1a_d1 M2 2 B8 4 B8 3 T9 4 T9 4 J14 8 AC8 9 B19 7 B19 7
vin1a_d2 L5 2 A7 4 A7 3 T6 4 T6 4 G13 8 AC3 9 F15 7 F15 7
vin1a_d3 M1 2 A8 4 A8 3 T7 4 T7 4 J11 8 AC9 9 B18 7 B18 7
vin1a_d4 L6 2 C9 4 C9 3 P6 4 P6 4 E12 8 AC6 9 A16 7 A16 7
vin1a_d5 L4 2 A9 4 A9 3 R9 4 R9 4 F13 8 AC7 9 C15 7 C15 7
vin1a_d6 L3 2 B9 4 B9 3 R5 4 R5 4 C12 8 AC4 9 A18 7 A18 7
vin1a_d7 L2 2 A10 4 A10 3 P5 4 P5 4 D12 8 AD4 9 A19 7 A19 7
vin1a_d8 L1 2 E8 4 E8 3 U2 4 U2 4 E15 8 AA4 9 F14 7 F14 7
vin1a_d9 K2 2 D9 4 D9 3 U1 4 U1 4 A20 8 AB3 9 G14 7 G14 7
vin1a_d10 J1 2 D7 4 D7 3 P3 4 P3 4 B15 8 AB9 9 A13 7 A13 7
vin1a_d11 J2 2 D8 4 D8 3 R2 4 R2 4 A15 8 AA3 9 E14 7 E14 7
vin1a_d12 H1 2 A5 4 A5 3 K7 4 K7 4 D15 8 D17 9 A12 7 A12 7
vin1a_d13 J3 2 C6 4 C6 3 M7 4 M7 4 B16 8 G16 9 B13 7 B13 7
vin1a_d14 H2 2 C8 4 C8 3 J5 4 J5 4 B17 8 A21 9 A11 7 A11 7
vin1a_d15 H3 2 C7 4 C7 3 K6 4 K6 4 A17 8 C18 9 B12 7 B12 7
vin1a_d16 R6 2 F11 4 F11 3 C18 8
vin1a_d17 T9 2 G10 4 G10 3 A21 8
vin1a_d18 T6 2 F10 4 F10 3 G16 8
vin1a_d19 T7 2 G11 4 G11 3 D17 8
vin1a_d20 P6 2 E9 4 E9 3 AA3 8
vin1a_d21 R9 2 F9 4 F9 3 AB9 8
vin1a_d22 R5 2 F8 4 F8 3 AB3 8
vin1a_d23 P5 2 E7 4 E7 3 AA4 8
vin1b
vin1b_clk1 P7 6 M4 4 V1 5 N9 6
vin1b_hsync1 H5 6 H5 6 U7 5 N7 6
vin1b_vsync1 H6 6 H6 6 V6 5 R4 6
vin1b_fld1 M4 6 W2 5 P4 6
vin1b_de1 N6 6 N6 6 V7 5 P9 6
vin1b_d0 K7 6 K7 6 U4 5 R6 6
vin1b_d1 M7 6 M7 6 V2 5 T9 6
vin1b_d2 J5 6 J5 6 Y1 5 T6 6
vin1b_d3 K6 6 K6 6 W9 5 T7 6
vin1b_d4 J7 6 J7 6 V9 5 P6 6
vin1b_d5 J4 6 J4 6 U5 5 R9 6
vin1b_d6 J6 6 J6 6 V5 5 R5 6
vin1b_d7 H4 6 H4 6 V4 5 P5 6
  1. The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad Configuration Registers.

Table 7-5 VIN2 IOSETs

SIGNALS IOSET1 IOSET2 IOSET4 IOSET5 IOSET6 IOSET7 (1) IOSET8 (1) IOSET9 (1) IOSET10 (1) IOSET11
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin2a
vin2a_clk0 E1 0 E1 0 V1 4 B11 3 P4 4 P4 4 B26 8
vin2a_hsync0 G1 0 G1 0 U7 4 C11 3 R3 4 P7 4 E21 8
vin2a_vsync0 G6 0 G6 0 V6 4 E11 3 T2 4 N1 4 F20 8
vin2a_fld0 H7 0 G2 1 W2 4 D11 3 P9 4 J7 4 F21 8
vin2a_de0 G2 0 V7 4 B10 3 P7 5 H6 4 C23 8
vin2a_d0 F2 0 F2 0 U4 4 B7 3 R6 4 R6 4 B14 8
vin2a_d1 F3 0 F3 0 V2 4 B8 3 T9 4 T9 4 J14 8
vin2a_d2 D1 0 D1 0 Y1 4 A7 3 T6 4 T6 4 G13 8
vin2a_d3 E2 0 E2 0 W9 4 A8 3 T7 4 T7 4 J11 8
vin2a_d4 D2 0 D2 0 V9 4 C9 3 P6 4 P6 4 E12 8
vin2a_d5 F4 0 F4 0 U5 4 A9 3 R9 4 R9 4 F13 8
vin2a_d6 C1 0 C1 0 V5 4 B9 3 R5 4 R5 4 C12 8
vin2a_d7 E4 0 E4 0 V4 4 A10 3 P5 4 P5 4 D12 8
vin2a_d8 F5 0 F5 0 V3 4 E8 3 U2 4 U2 4 E15 8
vin2a_d9 E6 0 E6 0 Y2 4 D9 3 U1 4 U1 4 A20 8
vin2a_d10 D3 0 D3 0 U6 4 D7 3 P3 4 P3 4 B15 8
vin2a_d11 F6 0 F6 0 U3 4 D8 3 R2 4 R2 4 A15 8
vin2a_d12 D5 0 D5 0 A5 3 K7 4 K7 4 D15 8
vin2a_d13 C2 0 C2 0 C6 3 M7 4 M7 4 B16 8
vin2a_d14 C3 0 C3 0 C8 3 J5 4 J5 4 B17 8
vin2a_d15 C4 0 C4 0 C7 3 K6 4 K6 4 A17 8
vin2a_d16 B2 0 B2 0 F11 3 C18 8
vin2a_d17 D6 0 D6 0 G10 3 A21 8
vin2a_d18 C5 0 C5 0 F10 3 G16 8
vin2a_d19 A3 0 A3 0 G11 3 D17 8
vin2a_d20 B3 0 B3 0 E9 3 AA3 8
vin2a_d21 B4 0 B4 0 F9 3 AB9 8
vin2a_d22 B5 0 B5 0 F8 3 AB3 8
vin2a_d23 A4 0 A4 0 E7 3 AA4 8
vin2b
vin2b_clk1 P7 6 M4 4 H7 2 H7 2 AB5 4 P7 6 M4 4
vin2b_hsync1 H5 6 H5 6 G1 3 G1 3 AC5 4 H5 6 H5 6
vin2b_vsync1 H6 6 H6 6 G6 3 G6 3 AB4 4 H6 6 H6 6
vin2b_fld1 M4 6 G2 2 M4 6
vin2b_de1 N6 6 N6 6 G2 3 AB8 4 N6 6 N6 6
vin2b_d0 K7 6 K7 6 A4 2 A4 2 AD6 4 K7 6 K7 6
vin2b_d1 M7 6 M7 6 B5 2 B5 2 AC8 4 M7 6 M7 6
vin2b_d2 J5 6 J5 6 B4 2 B4 2 AC3 4 J5 6 J5 6
vin2b_d3 K6 6 K6 6 B3 2 B3 2 AC9 4 K6 6 K6 6
vin2b_d4 J7 6 J7 6 A3 2 A3 2 AC6 4 J7 6 J7 6
vin2b_d5 J4 6 J4 6 C5 2 C5 2 AC7 4 J4 6 J4 6
vin2b_d6 J6 6 J6 6 D6 2 D6 2 AC4 4 J6 6 J6 6
vin2b_d7 H4 6 H4 6 B2 2 B2 2 AD4 4 H4 6 H4 6
  1. The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad Configuration Registers.


NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module chapter in the Device TRM.

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Manual Functions Mapping for VIP1 1A IOSET7 and 2A IOSET10 for a definition of the Manual modes.

Table 7-6 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-6 Manual Functions Mapping for VIP1 1A IOSET7 and 2A IOSET10

BALL BALL NAME VIP_MANUAL1 VIP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 8 8(1)
E21 gpio6_14 1400 240 1767 0 CFG_GPIO6_14_IN vin2a_hsync0 vin1a_hsync0
F20 gpio6_15 1170 240 1522 0 CFG_GPIO6_15_IN vin2a_vsync0 vin1a_vsync0
F21 gpio6_16 1470 0 1600 0 CFG_GPIO6_16_IN vin2a_fld0 vin1a_fld0
B14 mcasp1_aclkr 2145 200 2509 0 CFG_MCASP1_ACLKR_IN vin2a_d0 vin1a_d0
G13 mcasp1_axr2 2740 900 2680 1180 CFG_MCASP1_AXR2_IN vin2a_d2 vin1a_d2
J11 mcasp1_axr3 2933 200 2700 600 CFG_MCASP1_AXR3_IN vin2a_d3 vin1a_d3
E12 mcasp1_axr4 2901 240 2660 700 CFG_MCASP1_AXR4_IN vin2a_d4 vin1a_d4
F13 mcasp1_axr5 2600 840 2640 920 CFG_MCASP1_AXR5_IN vin2a_d5 vin1a_d5
C12 mcasp1_axr6 2718 240 3081 0 CFG_MCASP1_AXR6_IN vin2a_d6 vin1a_d6
D12 mcasp1_axr7 2983 240 2540 800 CFG_MCASP1_AXR7_IN vin2a_d7 vin1a_d7
J14 mcasp1_fsr 2203 240 2566 0 CFG_MCASP1_FSR_IN vin2a_d1 vin1a_d1
E15 mcasp2_aclkr 2143 240 2492 0 CFG_MCASP2_ACLKR_IN vin2a_d8 vin1a_d8
B15 mcasp2_axr0 2543 240 2905 0 CFG_MCASP2_AXR0_IN vin2a_d10 vin1a_d10
A15 mcasp2_axr1 2664 240 2730 400 CFG_MCASP2_AXR1_IN vin2a_d11 vin1a_d11
D15 mcasp2_axr4 2792 240 2750 400 CFG_MCASP2_AXR4_IN vin2a_d12 vin1a_d12
B16 mcasp2_axr5 2621 300 2983 0 CFG_MCASP2_AXR5_IN vin2a_d13 vin1a_d13
B17 mcasp2_axr6 1903 100 2086 0 CFG_MCASP2_AXR6_IN vin2a_d14 vin1a_d14
A17 mcasp2_axr7 2928 200 2670 700 CFG_MCASP2_AXR7_IN vin2a_d15 vin1a_d15
A20 mcasp2_fsr 2291 200 2654 0 CFG_MCASP2_FSR_IN vin2a_d9 vin1a_d9
C18 mcasp4_aclkx 1433 0 1540 0 CFG_MCASP4_ACLKX_IN vin2a_d16 vin1a_d16
G16 mcasp4_axr0 2500 0 2560 0 CFG_MCASP4_AXR0_IN vin2a_d18 vin1a_d18
D17 mcasp4_axr1 2379 100 2599 0 CFG_MCASP4_AXR1_IN vin2a_d19 vin1a_d19
A21 mcasp4_fsx 1500 1400 1900 1040 CFG_MCASP4_FSX_IN vin2a_d17 vin1a_d17
AA3 mcasp5_aclkx 3740 1850 3900 1700 CFG_MCASP5_ACLKX_IN vin2a_d20 vin1a_d20
AB3 mcasp5_axr0 3800 2760 3800 2800 CFG_MCASP5_AXR0_IN vin2a_d22 vin1a_d22
AA4 mcasp5_axr1 4099 2500 3900 2870 CFG_MCASP5_AXR1_IN vin2a_d23 vin1a_d23
AB9 mcasp5_fsx 3740 2100 3860 2060 CFG_MCASP5_FSX_IN vin2a_d21 vin1a_d21
B26 xref_clk2 0 0 0 0 CFG_XREF_CLK2_IN vin2a_clk0 vin1a_clk0
C23 xref_clk3 1440 0 1623 0 CFG_XREF_CLK3_IN vin2a_de0 vin1a_de0
  1. Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-7 Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.

Table 7-7 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-7 Manual Functions Mapping for VIN2A (IOSET4/5/6)

BALL BALL NAME VIP_MANUAL3 VIP_MANUAL5 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0 1 2 3 4
U3 RMII_MHZ_50_CLK 2616 1379 2798 1294 CFG_RMII_MHZ_50_CLK_IN - - - - vin2a_d11
U4 mdio_d 2558 1105 2790 954 CFG_MDIO_D_IN - - - - vin2a_d0
V1 mdio_mclk 998 463 1029 431 CFG_MDIO_MCLK_IN - - - - vin2a_clk0
U5 rgmii0_rxc 2658 862 2896 651 CFG_RGMII0_RXC_IN - - - - vin2a_d5
V5 rgmii0_rxctl 2658 1628 2844 1518 CFG_RGMII0_RXCTL_IN - - - - vin2a_d6
W2 rgmii0_rxd0 2638 1123 2856 888 CFG_RGMII0_RXD0_IN - - - - vin2a_fld0
Y2 rgmii0_rxd1 2641 1737 2804 1702 CFG_RGMII0_RXD1_IN - - - - vin2a_d9
V3 rgmii0_rxd2 2641 1676 2801 1652 CFG_RGMII0_RXD2_IN - - - - vin2a_d8
V4 rgmii0_rxd3 2644 1828 2807 1790 CFG_RGMII0_RXD3_IN - - - - vin2a_d7
W9 rgmii0_txc 2638 1454 2835 1396 CFG_RGMII0_TXC_IN - - - - vin2a_d3
V9 rgmii0_txctl 2672 1663 2831 1640 CFG_RGMII0_TXCTL_IN - - - - vin2a_d4
U6 rgmii0_txd0 2604 1442 2764 1417 CFG_RGMII0_TXD0_IN - - - - vin2a_d10
V6 rgmii0_txd1 2683 1598 2843 1600 CFG_RGMII0_TXD1_IN - - - - vin2a_vsync0
U7 rgmii0_txd2 2563 1483 2816 1344 CFG_RGMII0_TXD2_IN - - - - vin2a_hsync0
V7 rgmii0_txd3 2717 1461 2913 1310 CFG_RGMII0_TXD3_IN - - - - vin2a_de0
V2 uart3_rxd 2445 1145 2743 923 CFG_UART3_RXD_IN - - - - vin2a_d1
Y1 uart3_txd 2650 1197 2842 1080 CFG_UART3_TXD_IN - - - - vin2a_d2
E1 vin2a_clk0 0 0 0 0 CFG_VIN2A_CLK0_IN vin2a_clk0 - - - -
F2 vin2a_d0 1812 102 1936 0 CFG_VIN2A_D0_IN vin2a_d0 - - - -
F3 vin2a_d1 1701 439 2229 10 CFG_VIN2A_D1_IN vin2a_d1 - - - -
D3 vin2a_d10 1720 215 2031 0 CFG_VIN2A_D10_IN vin2a_d10 - - - -
F6 vin2a_d11 1622 0 1702 0 CFG_VIN2A_D11_IN vin2a_d11 - - - -
D5 vin2a_d12 1350 412 1819 0 CFG_VIN2A_D12_IN vin2a_d12 - - - -
C2 vin2a_d13 1613 147 1476 260 CFG_VIN2A_D13_IN vin2a_d13 - - - -
C3 vin2a_d14 1149 516 1701 0 CFG_VIN2A_D14_IN vin2a_d14 - - - -
C4 vin2a_d15 1530 450 2021 0 CFG_VIN2A_D15_IN vin2a_d15 - - - -
B2 vin2a_d16 1512 449 2044 11 CFG_VIN2A_D16_IN vin2a_d16 - vin2b_d7 - -
D6 vin2a_d17 1293 488 1839 5 CFG_VIN2A_D17_IN vin2a_d17 - vin2b_d6 - -
C5 vin2a_d18 2140 371 2494 0 CFG_VIN2A_D18_IN vin2a_d18 - vin2b_d5 - -
A3 vin2a_d19 2041 275 1699 611 CFG_VIN2A_D19_IN vin2a_d19 - vin2b_d4 - -
D1 vin2a_d2 1675 35 1736 0 CFG_VIN2A_D2_IN vin2a_d2 - - - -
B3 vin2a_d20 1972 441 2412 88 CFG_VIN2A_D20_IN vin2a_d20 - vin2b_d3 - -
B4 vin2a_d21 1957 556 2391 161 CFG_VIN2A_D21_IN vin2a_d21 - vin2b_d2 - -
B5 vin2a_d22 2011 433 2446 102 CFG_VIN2A_D22_IN vin2a_d22 - vin2b_d1 - -
A4 vin2a_d23 1962 523 2395 145 CFG_VIN2A_D23_IN vin2a_d23 - vin2b_d0 - -
E2 vin2a_d3 1457 361 1943 0 CFG_VIN2A_D3_IN vin2a_d3 - - - -
D2 vin2a_d4 1535 0 1601 0 CFG_VIN2A_D4_IN vin2a_d4 - - - -
F4 vin2a_d5 1676 271 2052 0 CFG_VIN2A_D5_IN vin2a_d5 - - - -
C1 vin2a_d6 1513 0 1571 0 CFG_VIN2A_D6_IN vin2a_d6 - - - -
E4 vin2a_d7 1616 141 1855 0 CFG_VIN2A_D7_IN vin2a_d7 - - - -
F5 vin2a_d8 1286 437 1224 618 CFG_VIN2A_D8_IN vin2a_d8 - - - -
E6 vin2a_d9 1544 265 1373 509 CFG_VIN2A_D9_IN vin2a_d9 - - - -
G2 vin2a_de0 1732 208 1949 0 CFG_VIN2A_DE0_IN vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 -
H7 vin2a_fld0 1461 562 1983 151 CFG_VIN2A_FLD0_IN vin2a_fld0 - vin2b_clk1 - -
G1 vin2a_hsync0 1877 0 1943 0 CFG_VIN2A_HSYNC0_IN vin2a_hsync0 - - vin2b_hsync1 -
G6 vin2a_vsync0 1566 0 1612 0 CFG_VIN2A_VSYNC0_IN vin2a_vsync0 - - vin2b_vsync1 -

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-8 Manual Functions Mapping for VIN2B (IOSET7/8/9) for a definition of the Manual modes.

Table 7-8 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-8 Manual Functions Mapping for VIN2B (IOSET7/8/9)

BALL BALL NAME VIP_MANUAL4 VIP_MANUAL6 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3 4
AC5 gpio6_10 2829 884 3009 892 CFG_GPIO6_10_IN - - vin2b_hsync1
AB4 gpio6_11 2648 1033 2890 1096 CFG_GPIO6_11_IN - - vin2b_vsync1
AD4 mmc3_clk 2794 1074 2997 1089 CFG_MMC3_CLK_IN - - vin2b_d7
AC4 mmc3_cmd 2789 1162 2959 1210 CFG_MMC3_CMD_IN - - vin2b_d6
AC7 mmc3_dat0 2689 1180 2897 1269 CFG_MMC3_DAT0_IN - - vin2b_d5
AC6 mmc3_dat1 2605 1219 2891 1219 CFG_MMC3_DAT1_IN - - vin2b_d4
AC9 mmc3_dat2 2616 703 2947 590 CFG_MMC3_DAT2_IN - - vin2b_d3
AC3 mmc3_dat3 2760 1235 2931 1342 CFG_MMC3_DAT3_IN - - vin2b_d2
AC8 mmc3_dat4 2757 880 2979 891 CFG_MMC3_DAT4_IN - - vin2b_d1
AD6 mmc3_dat5 2688 1177 2894 1262 CFG_MMC3_DAT5_IN - - vin2b_d0
AB8 mmc3_dat6 2638 1165 2894 1187 CFG_MMC3_DAT6_IN - - vin2b_de1
AB5 mmc3_dat7 995 182 1202 107 CFG_MMC3_DAT7_IN - - vin2b_clk1
B2 vin2a_d16 1423 0 1739 0 CFG_VIN2A_D16_IN vin2b_d7 - -
D6 vin2a_d17 1253 0 1568 0 CFG_VIN2A_D17_IN vin2b_d6 - -
C5 vin2a_d18 2080 0 2217 0 CFG_VIN2A_D18_IN vin2b_d5 - -
A3 vin2a_d19 1849 0 2029 0 CFG_VIN2A_D19_IN vin2b_d4 - -
B3 vin2a_d20 1881 50 2202 0 CFG_VIN2A_D20_IN vin2b_d3 - -
B4 vin2a_d21 1917 167 2313 0 CFG_VIN2A_D21_IN vin2b_d2 - -
B5 vin2a_d22 1955 79 2334 0 CFG_VIN2A_D22_IN vin2b_d1 - -
A4 vin2a_d23 1899 145 2288 0 CFG_VIN2A_D23_IN vin2b_d0 - -
G2 vin2a_de0 1568 261 2048 0 CFG_VIN2A_DE0_IN vin2b_fld1 vin2b_de1 -
H7 vin2a_fld0 0 0 0 0 CFG_VIN2A_FLD0_IN vin2b_clk1 - -
G1 vin2a_hsync0 1793 0 2011 0 CFG_VIN2A_HSYNC0_IN - vin2b_hsync1 -
G6 vin2a_vsync0 1382 0 1632 0 CFG_VIN2A_VSYNC0_IN - vin2b_vsync1 -

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-9 Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) for a definition of the Manual modes.

Table 7-9 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-9 Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10)

BALL BALL NAME VIP_MANUAL7 VIP_MANUAL12 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3(1) 3(1) 4(1) 4(1) 5 6(1) 6(1)
R6 gpmc_a0 3080 1792 3376 1632 CFG_GPMC_A0_IN vin1a_d16 - - vin2a_d0 - - vin1b_d0 -
T9 gpmc_a1 2958 1890 3249 1749 CFG_GPMC_A1_IN vin1a_d17 - - vin2a_d1 - - vin1b_d1 -
N9 gpmc_a10 3073 1653 3388 1433 CFG_GPMC_A10_IN vin1a_de0 - - - - - vin1b_clk1 -
P9 gpmc_a11 3014 1784 3290 1693 CFG_GPMC_A11_IN vin1a_fld0 - - vin2a_fld0 vin1a_fld0 - vin1b_de1 -
K7 gpmc_a19 1385 0 1246 0 CFG_GPMC_A19_IN - - - vin2a_d12 - - vin2b_d0 vin1b_d0
T6 gpmc_a2 3041 1960 3322 1850 CFG_GPMC_A2_IN vin1a_d18 - - vin2a_d2 - - vin1b_d2 -
M7 gpmc_a20 859 0 720 0 CFG_GPMC_A20_IN - - - vin2a_d13 - - vin2b_d1 vin1b_d1
J5 gpmc_a21 1465 0 1334 0 CFG_GPMC_A21_IN - - - vin2a_d14 - - vin2b_d2 vin1b_d2
K6 gpmc_a22 1210 0 1064 0 CFG_GPMC_A22_IN - - - vin2a_d15 - - vin2b_d3 vin1b_d3
J7 gpmc_a23 1111 0 954 0 CFG_GPMC_A23_IN - - - vin2a_fld0 - - vin2b_d4 vin1b_d4
J4 gpmc_a24 1137 0 1051 0 CFG_GPMC_A24_IN - - - - - - vin2b_d5 vin1b_d5
J6 gpmc_a25 1402 0 1283 0 CFG_GPMC_A25_IN - - - - - - vin2b_d6 vin1b_d6
H4 gpmc_a26 1298 0 1153 0 CFG_GPMC_A26_IN - - - - - - vin2b_d7 vin1b_d7
H5 gpmc_a27 934 0 870 0 CFG_GPMC_A27_IN - - - - - - vin2b_hsync1 vin1b_hsync1
T7 gpmc_a3 3019 2145 3296 2050 CFG_GPMC_A3_IN vin1a_d19 - - vin2a_d3 - - vin1b_d3 -
P6 gpmc_a4 3063 1981 3357 1829 CFG_GPMC_A4_IN vin1a_d20 - - vin2a_d4 - - vin1b_d4 -
R9 gpmc_a5 3021 1954 3304 1840 CFG_GPMC_A5_IN vin1a_d21 - - vin2a_d5 - - vin1b_d5 -
R5 gpmc_a6 3062 1716 3348 1592 CFG_GPMC_A6_IN vin1a_d22 - - vin2a_d6 - - vin1b_d6 -
P5 gpmc_a7 3260 1889 3583 1631 CFG_GPMC_A7_IN vin1a_d23 - - vin2a_d7 - - vin1b_d7 -
N7 gpmc_a8 3033 1702 3328 1547 CFG_GPMC_A8_IN vin1a_hsync0 - - - - - vin1b_hsync1 -
R4 gpmc_a9 2991 1905 3281 1766 CFG_GPMC_A9_IN vin1a_vsync0 - - - - - vin1b_vsync1 -
M6 gpmc_ad0 2907 1342 3181 1255 CFG_GPMC_AD0_IN vin1a_d0 - - - - - - -
M2 gpmc_ad1 2858 1321 3132 1234 CFG_GPMC_AD1_IN vin1a_d1 - - - - - - -
J1 gpmc_ad10 2920 1384 3223 1204 CFG_GPMC_AD10_IN vin1a_d10 - - - - - - -
J2 gpmc_ad11 2719 1310 3019 1198 CFG_GPMC_AD11_IN vin1a_d11 - - - - - - -
H1 gpmc_ad12 2845 1135 3160 917 CFG_GPMC_AD12_IN vin1a_d12 - - - - - - -
J3 gpmc_ad13 2765 1225 3045 1119 CFG_GPMC_AD13_IN vin1a_d13 - - - - - - -
H2 gpmc_ad14 2845 1150 3153 952 CFG_GPMC_AD14_IN vin1a_d14 - - - - - - -
H3 gpmc_ad15 2766 1453 3044 1355 CFG_GPMC_AD15_IN vin1a_d15 - - - - - - -
L5 gpmc_ad2 2951 1296 3226 1209 CFG_GPMC_AD2_IN vin1a_d2 - - - - - - -
M1 gpmc_ad3 2825 1154 3121 997 CFG_GPMC_AD3_IN vin1a_d3 - - - - - - -
L6 gpmc_ad4 2927 1245 3246 1014 CFG_GPMC_AD4_IN vin1a_d4 - - - - - - -
L4 gpmc_ad5 2923 1251 3217 1098 CFG_GPMC_AD5_IN vin1a_d5 - - - - - - -
L3 gpmc_ad6 2958 1342 3238 1239 CFG_GPMC_AD6_IN vin1a_d6 - - - - - - -
L2 gpmc_ad7 2900 1244 3174 1157 CFG_GPMC_AD7_IN vin1a_d7 - - - - - - -
L1 gpmc_ad8 2845 1585 3125 1482 CFG_GPMC_AD8_IN vin1a_d8 - - - - - - -
K2 gpmc_ad9 2779 1343 3086 1223 CFG_GPMC_AD9_IN vin1a_d9 - - - - - - -
N6 gpmc_ben0 1555 0 1425 0 CFG_GPMC_BEN0_IN - - - - - - vin2b_de1 vin1b_de1
M4 gpmc_ben1 1501 0 1397 0 CFG_GPMC_BEN1_IN - - - vin2b_clk1 - - vin2b_fld1 vin1b_fld1
P7 gpmc_clk 0 0 0 0 CFG_GPMC_CLK_IN - - - vin2a_hsync0 - vin2a_de0 vin2b_clk1 vin1b_clk1
H6 gpmc_cs1 1192 0 1102 0 CFG_GPMC_CS1_IN - - - vin2a_de0 - - vin2b_vsync1 vin1b_vsync1
P1 gpmc_cs3 1324 374 1466 353 CFG_GPMC_CS3_IN vin1a_clk0 - - - - - - -
D11 vout1_clk 1648 885 1762 928 CFG_VOUT1_CLK_IN - vin2a_fld0 vin1a_fld0 vin1a_fld0 - - - -
F11 vout1_d0 2197 565 2734 215 CFG_VOUT1_D0_IN - vin2a_d16 vin1a_d16 vin1a_d16 - - - -
G10 vout1_d1 2221 576 2750 230 CFG_VOUT1_D1_IN - vin2a_d17 vin1a_d17 vin1a_d17 - - - -
D7 vout1_d10 1800 863 1910 916 CFG_VOUT1_D10_IN - vin2a_d10 vin1a_d10 vin1a_d10 - - - -
D8 vout1_d11 1656 931 1780 945 CFG_VOUT1_D11_IN - vin2a_d11 vin1a_d11 vin1a_d11 - - - -
A5 vout1_d12 1719 1086 1866 1041 CFG_VOUT1_D12_IN - vin2a_d12 vin1a_d12 vin1a_d12 - - - -
C6 vout1_d13 1757 928 1851 1022 CFG_VOUT1_D13_IN - vin2a_d13 vin1a_d13 vin1a_d13 - - - -
C8 vout1_d14 2279 345 2788 0 CFG_VOUT1_D14_IN - vin2a_d14 vin1a_d14 vin1a_d14 - - - -
C7 vout1_d15 1810 874 2786 69 CFG_VOUT1_D15_IN - vin2a_d15 vin1a_d15 vin1a_d15 - - - -
B7 vout1_d16 1763 774 1880 807 CFG_VOUT1_D16_IN - vin2a_d0 vin1a_d0 vin1a_d0 - - - -
B8 vout1_d17 1695 788 1805 838 CFG_VOUT1_D17_IN - vin2a_d1 vin1a_d1 vin1a_d1 - - - -
A7 vout1_d18 1777 590 1871 684 CFG_VOUT1_D18_IN - vin2a_d2 vin1a_d2 vin1a_d2 - - - -
A8 vout1_d19 2047 22 2196 0 CFG_VOUT1_D19_IN - vin2a_d3 vin1a_d3 vin1a_d3 - - - -
F10 vout1_d2 1809 941 2759 178 CFG_VOUT1_D2_IN - vin2a_d18 vin1a_d18 vin1a_d18 - - - -
C9 vout1_d20 1676 944 1795 973 CFG_VOUT1_D20_IN - vin2a_d4 vin1a_d4 vin1a_d4 - - - -
A9 vout1_d21 1712 688 1848 670 CFG_VOUT1_D21_IN - vin2a_d5 vin1a_d5 vin1a_d5 - - - -
B9 vout1_d22 1698 557 2443 0 CFG_VOUT1_D22_IN - vin2a_d6 vin1a_d6 vin1a_d6 - - - -
A10 vout1_d23 1627 1035 1726 1116 CFG_VOUT1_D23_IN - vin2a_d7 vin1a_d7 vin1a_d7 - - - -
G11 vout1_d3 2427 429 2853 167 CFG_VOUT1_D3_IN - vin2a_d19 vin1a_d19 vin1a_d19 - - - -
E9 vout1_d4 2351 412 2845 85 CFG_VOUT1_D4_IN - vin2a_d20 vin1a_d20 vin1a_d20 - - - -
F9 vout1_d5 1634 983 1729 1076 CFG_VOUT1_D5_IN - vin2a_d21 vin1a_d21 vin1a_d21 - - - -
F8 vout1_d6 1776 880 2736 107 CFG_VOUT1_D6_IN - vin2a_d22 vin1a_d22 vin1a_d22 - - - -
E7 vout1_d7 2272 351 2757 53 CFG_VOUT1_D7_IN - vin2a_d23 vin1a_d23 vin1a_d23 - - - -
E8 vout1_d8 1724 898 1819 990 CFG_VOUT1_D8_IN - vin2a_d8 vin1a_d8 vin1a_d8 - - - -
D9 vout1_d9 2281 566 2804 195 CFG_VOUT1_D9_IN - vin2a_d9 vin1a_d9 vin1a_d9 - - - -
B10 vout1_de 1734 749 1828 842 CFG_VOUT1_DE_IN - vin2a_de0 vin1a_de0 vin1a_de0 - - - -
B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN - vin2a_clk0 vin1a_clk0 vin1a_clk0 - - - -
C11 vout1_hsync 1634 606 2399 0 CFG_VOUT1_HSYNC_IN - vin2a_hsync0 vin1a_hsync0 vin1a_hsync0 - - - -
E11 vout1_vsync 1887 0 2068 0 CFG_VOUT1_VSYNC_IN - vin2a_vsync0 vin1a_vsync0 vin1a_vsync0 - - - -
  1. Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-10 Manual Functions Mapping for VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) for a definition of the Manual modes.

Table 7-10 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-10 Manual Functions Mapping for VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9)

BALL BALL NAME VIP_MANUAL8 VIP_MANUAL13 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 4(1) 4(1) 5(1) 5(1)
R6 gpmc_a0 1891 427 2176 0 CFG_GPMC_A0_IN - vin2a_d0 vin1a_d0 - -
T9 gpmc_a1 1713 513 2109 0 CFG_GPMC_A1_IN - vin2a_d1 vin1a_d1 - -
P9 gpmc_a11 1797 317 2036 0 CFG_GPMC_A11_IN - vin2a_fld0 vin1a_fld0 - -
P4 gpmc_a12 0 0 0 0 CFG_GPMC_A12_IN - vin2a_clk0 vin1a_clk0 - -
R3 gpmc_a13 1876 391 2144 0 CFG_GPMC_A13_IN - vin2a_hsync0 vin1a_hsync0 - -
T2 gpmc_a14 1720 756 2384 38 CFG_GPMC_A14_IN - vin2a_vsync0 vin1a_vsync0 - -
U2 gpmc_a15 1502 368 1804 0 CFG_GPMC_A15_IN - vin2a_d8 vin1a_d8 - -
U1 gpmc_a16 1651 355 1902 0 CFG_GPMC_A16_IN - vin2a_d9 vin1a_d9 - -
P3 gpmc_a17 1642 338 1862 0 CFG_GPMC_A17_IN - vin2a_d10 vin1a_d10 - -
R2 gpmc_a18 1612 0 1406 0 CFG_GPMC_A18_IN - vin2a_d11 vin1a_d11 - -
K7 gpmc_a19 1463 152 1418 0 CFG_GPMC_A19_IN - vin2a_d12 vin1a_d12 - -
T6 gpmc_a2 1789 646 2310 0 CFG_GPMC_A2_IN - vin2a_d2 vin1a_d2 - -
M7 gpmc_a20 1124 0 933 0 CFG_GPMC_A20_IN - vin2a_d13 vin1a_d13 - -
J5 gpmc_a21 1491 206 1483 0 CFG_GPMC_A21_IN - vin2a_d14 vin1a_d14 - -
K6 gpmc_a22 1218 245 1254 0 CFG_GPMC_A22_IN - vin2a_d15 vin1a_d15 - -
J7 gpmc_a23 1216 0 1021 0 CFG_GPMC_A23_IN - vin2a_fld0 vin1a_fld0 - -
T7 gpmc_a3 1789 766 2451 8 CFG_GPMC_A3_IN - vin2a_d3 vin1a_d3 - -
P6 gpmc_a4 1842 646 2329 0 CFG_GPMC_A4_IN - vin2a_d4 vin1a_d4 - -
R9 gpmc_a5 1778 556 2215 0 CFG_GPMC_A5_IN - vin2a_d5 vin1a_d5 - -
R5 gpmc_a6 1783 443 2088 0 CFG_GPMC_A6_IN - vin2a_d6 vin1a_d6 - -
P5 gpmc_a7 2207 370 2393 0 CFG_GPMC_A7_IN - vin2a_d7 vin1a_d7 - -
N1 gpmc_advn_ale 1755 116 1745 0 CFG_GPMC_ADVN_ALE_IN - vin2a_vsync0 vin1a_vsync0 - -
P7 gpmc_clk 1896 351 2152 0 CFG_GPMC_CLK_IN - vin2a_hsync0 vin1a_hsync0 vin2a_de0 vin1a_de0
H6 gpmc_cs1 1337 74 1288 0 CFG_GPMC_CS1_IN - vin2a_de0 vin1a_de0 - -
D11 vout1_clk 1939 332 2486 0 CFG_VOUT1_CLK_IN vin2a_fld0 - - - -
F11 vout1_d0 2140 647 2617 386 CFG_VOUT1_D0_IN vin2a_d16 - - - -
G10 vout1_d1 2104 615 2620 314 CFG_VOUT1_D1_IN vin2a_d17 - - - -
D7 vout1_d10 2139 406 2675 85 CFG_VOUT1_D10_IN vin2a_d10 - - - -
D8 vout1_d11 1944 534 2569 125 CFG_VOUT1_D11_IN vin2a_d11 - - - -
A5 vout1_d12 1966 659 2646 154 CFG_VOUT1_D12_IN vin2a_d12 - - - -
C6 vout1_d13 2048 447 2624 87 CFG_VOUT1_D13_IN vin2a_d13 - - - -
C8 vout1_d14 2222 548 2700 286 CFG_VOUT1_D14_IN vin2a_d14 - - - -
C7 vout1_d15 2072 443 2664 67 CFG_VOUT1_D15_IN vin2a_d15 - - - -
B7 vout1_d16 2044 455 2634 82 CFG_VOUT1_D16_IN vin2a_d0 - - - -
B8 vout1_d17 1971 246 2433 0 CFG_VOUT1_D17_IN vin2a_d1 - - - -
A7 vout1_d18 2104 120 2440 0 CFG_VOUT1_D18_IN vin2a_d2 - - - -
A8 vout1_d19 1888 0 2105 0 CFG_VOUT1_D19_IN vin2a_d3 - - - -
F10 vout1_d2 2170 237 2624 0 CFG_VOUT1_D2_IN vin2a_d18 - - - -
C9 vout1_d20 1942 512 2579 91 CFG_VOUT1_D20_IN vin2a_d4 - - - -
A9 vout1_d21 1997 141 2324 0 CFG_VOUT1_D21_IN vin2a_d5 - - - -
B9 vout1_d22 1949 0 2165 0 CFG_VOUT1_D22_IN vin2a_d6 - - - -
A10 vout1_d23 1871 704 2522 269 CFG_VOUT1_D23_IN vin2a_d7 - - - -
G11 vout1_d3 2319 417 2740 191 CFG_VOUT1_D3_IN vin2a_d19 - - - -
E9 vout1_d4 2300 369 2739 137 CFG_VOUT1_D4_IN vin2a_d20 - - - -
F9 vout1_d5 1923 579 2527 191 CFG_VOUT1_D5_IN vin2a_d21 - - - -
F8 vout1_d6 2148 396 2622 138 CFG_VOUT1_D6_IN vin2a_d22 - - - -
E7 vout1_d7 2212 335 2653 110 CFG_VOUT1_D7_IN vin2a_d23 - - - -
E8 vout1_d8 1962 573 2573 178 CFG_VOUT1_D8_IN vin2a_d8 - - - -
D9 vout1_d9 2312 335 2725 138 CFG_VOUT1_D9_IN vin2a_d9 - - - -
B10 vout1_de 1973 414 2551 52 CFG_VOUT1_DE_IN vin2a_de0 - - - -
B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN vin2a_clk0 - - - -
C11 vout1_hsync 1813 261 2277 0 CFG_VOUT1_HSYNC_IN vin2a_hsync0 - - - -
E11 vout1_vsync 1665 0 1881 0 CFG_VOUT1_VSYNC_IN vin2a_vsync0 - - - -
  1. Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-11 Manual Functions Mapping for VIN1B (IOSET6/7) for a definition of the Manual modes.

Table 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-11 Manual Functions Mapping for VIN1B (IOSET6/7)

BALL BALL NAME VIP_MANUAL9 VIP_MANUAL14 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 5 6
R6 gpmc_a0 1873 702 2202 441 CFG_GPMC_A0_IN - vin1b_d0
T9 gpmc_a1 1629 772 2057 413 CFG_GPMC_A1_IN - vin1b_d1
N9 gpmc_a10 0 0 0 0 CFG_GPMC_A10_IN - vin1b_clk1
P9 gpmc_a11 1851 1011 2126 856 CFG_GPMC_A11_IN - vin1b_de1
P4 gpmc_a12 2009 601 2289 327 CFG_GPMC_A12_IN - vin1b_fld1
T6 gpmc_a2 1734 898 2131 573 CFG_GPMC_A2_IN - vin1b_d2
T7 gpmc_a3 1757 1076 2106 812 CFG_GPMC_A3_IN - vin1b_d3
P6 gpmc_a4 1794 893 2164 559 CFG_GPMC_A4_IN - vin1b_d4
R9 gpmc_a5 1726 853 2120 523 CFG_GPMC_A5_IN - vin1b_d5
R5 gpmc_a6 1792 612 2153 338 CFG_GPMC_A6_IN - vin1b_d6
P5 gpmc_a7 2117 610 2389 304 CFG_GPMC_A7_IN - vin1b_d7
N7 gpmc_a8 1758 653 2140 308 CFG_GPMC_A8_IN - vin1b_hsync1
R4 gpmc_a9 1705 899 2067 646 CFG_GPMC_A9_IN - vin1b_vsync1
U4 mdio_d 1945 671 2265 414 CFG_MDIO_D_IN vin1b_d0 -
V1 mdio_mclk 255 119 337 0 CFG_MDIO_MCLK_IN vin1b_clk1 -
U5 rgmii0_rxc 2057 909 2341 646 CFG_RGMII0_RXC_IN vin1b_d5 -
V5 rgmii0_rxctl 2121 1139 2323 988 CFG_RGMII0_RXCTL_IN vin1b_d6 -
W2 rgmii0_rxd0 2070 655 2336 340 CFG_RGMII0_RXD0_IN vin1b_fld1 -
V4 rgmii0_rxd3 2092 1357 2306 1216 CFG_RGMII0_RXD3_IN vin1b_d7 -
W9 rgmii0_txc 2088 1205 2328 1079 CFG_RGMII0_TXC_IN vin1b_d3 -
V9 rgmii0_txctl 2143 1383 2312 1311 CFG_RGMII0_TXCTL_IN vin1b_d4 -
V6 rgmii0_txd1 2078 1189 2324 1065 CFG_RGMII0_TXD1_IN vin1b_vsync1 -
U7 rgmii0_txd2 1928 1125 2306 763 CFG_RGMII0_TXD2_IN vin1b_hsync1 -
V7 rgmii0_txd3 2255 971 2401 846 CFG_RGMII0_TXD3_IN vin1b_de1 -
V2 uart3_rxd 1829 747 2220 400 CFG_UART3_RXD_IN vin1b_d1 -
Y1 uart3_txd 2030 837 2324 568 CFG_UART3_TXD_IN vin1b_d2 -

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-12 Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET2/11) for a definition of the Manual modes.

Table 7-12 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-12 Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET2/11)

BALL BALL NAME VIP_MANUAL10 VIP_MANUAL11 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4(1) 4(1) 6(1) 6(1)
K7 gpmc_a19 1600 943 2023 477 CFG_GPMC_A19_IN - - vin2b_d0 vin1b_d0
M7 gpmc_a20 1440 621 1875 136 CFG_GPMC_A20_IN - - vin2b_d1 vin1b_d1
J5 gpmc_a21 1602 1066 2021 604 CFG_GPMC_A21_IN - - vin2b_d2 vin1b_d2
K6 gpmc_a22 1395 983 1822 519 CFG_GPMC_A22_IN - - vin2b_d3 vin1b_d3
J7 gpmc_a23 1571 716 2045 200 CFG_GPMC_A23_IN - - vin2b_d4 vin1b_d4
J4 gpmc_a24 1463 832 1893 396 CFG_GPMC_A24_IN - - vin2b_d5 vin1b_d5
J6 gpmc_a25 1426 1166 1842 732 CFG_GPMC_A25_IN - - vin2b_d6 vin1b_d6
H4 gpmc_a26 1362 1094 1797 584 CFG_GPMC_A26_IN - - vin2b_d7 vin1b_d7
H5 gpmc_a27 1283 809 1760 338 CFG_GPMC_A27_IN - - vin2b_hsync1 vin1b_hsync1
N6 gpmc_ben0 1978 780 2327 389 CFG_GPMC_BEN0_IN - - vin2b_de1 vin1b_de1
M4 gpmc_ben1 0 0 0 0 CFG_GPMC_BEN1_IN vin2b_clk1 vin1b_clk1 vin2b_fld1 vin1b_fld1
H6 gpmc_cs1 1411 982 1857 536 CFG_GPMC_CS1_IN - - vin2b_vsync1 vin1b_vsync1
  1. Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-13 Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.

Table 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-13 Manual Functions Mapping for VIN1A (IOSET8/9/10)

BALL BALL NAME VIP_MANUAL15 VIP_MANUAL16 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 7 9
AC5 gpio6_10 2131 2198 2170 2180 CFG_GPIO6_10_IN - vin1a_clk0
AB4 gpio6_11 3720 2732 4106 2448 CFG_GPIO6_11_IN - vin1a_de0
C14 mcasp1_aclkx 2447 0 3042 0 CFG_MCASP1_ACLKX_IN vin1a_fld0 -
G12 mcasp1_axr0 3061 0 3380 292 CFG_MCASP1_AXR0_IN vin1a_vsync0 -
F12 mcasp1_axr1 3113 0 3396 304 CFG_MCASP1_AXR1_IN vin1a_hsync0 -
B13 mcasp1_axr10 2803 0 3362 0 CFG_MCASP1_AXR10_IN vin1a_d13 -
A12 mcasp1_axr11 3292 0 3357 546 CFG_MCASP1_AXR11_IN vin1a_d12 -
E14 mcasp1_axr12 2854 0 3145 320 CFG_MCASP1_AXR12_IN vin1a_d11 -
A13 mcasp1_axr13 2813 0 3229 196 CFG_MCASP1_AXR13_IN vin1a_d10 -
G14 mcasp1_axr14 2471 0 3053 0 CFG_MCASP1_AXR14_IN vin1a_d9 -
F14 mcasp1_axr15 2815 0 3225 201 CFG_MCASP1_AXR15_IN vin1a_d8 -
B12 mcasp1_axr8 2965 0 3427 83 CFG_MCASP1_AXR8_IN vin1a_d15 -
A11 mcasp1_axr9 3082 0 3253 440 CFG_MCASP1_AXR9_IN vin1a_d14 -
D14 mcasp1_fsx 2898 0 3368 139 CFG_MCASP1_FSX_IN vin1a_de0 -
A19 mcasp2_aclkx 2413 0 2972 0 CFG_MCASP2_ACLKX_IN vin1a_d7 -
C15 mcasp2_axr2 2478 0 3062 0 CFG_MCASP2_AXR2_IN vin1a_d5 -
A16 mcasp2_axr3 2806 0 3175 242 CFG_MCASP2_AXR3_IN vin1a_d4 -
A18 mcasp2_fsx 2861 78 2936 599 CFG_MCASP2_FSX_IN vin1a_d6 -
B18 mcasp3_aclkx 1583 0 1878 0 CFG_MCASP3_ACLKX_IN vin1a_d3 -
B19 mcasp3_axr0 2873 0 3109 375 CFG_MCASP3_AXR0_IN vin1a_d1 -
C17 mcasp3_axr1 1625 1400 2072 1023 CFG_MCASP3_AXR1_IN vin1a_d0 vin1a_fld0
F15 mcasp3_fsx 2792 0 3146 257 CFG_MCASP3_FSX_IN vin1a_d2 -
C18 mcasp4_aclkx 1547 268 1776 0 CFG_MCASP4_ACLKX_IN - vin1a_d15
G16 mcasp4_axr0 2362 587 2815 193 CFG_MCASP4_AXR0_IN - vin1a_d13
D17 mcasp4_axr1 2326 667 2769 304 CFG_MCASP4_AXR1_IN - vin1a_d12
A21 mcasp4_fsx 924 2573 1338 2219 CFG_MCASP4_FSX_IN - vin1a_d14
AA3 mcasp5_aclkx 3731 2106 4130 1708 CFG_MCASP5_ACLKX_IN - vin1a_d11
AB3 mcasp5_axr0 3800 3013 4159 2776 CFG_MCASP5_AXR0_IN - vin1a_d9
AA4 mcasp5_axr1 3828 2951 4179 2733 CFG_MCASP5_AXR1_IN - vin1a_d8
AB9 mcasp5_fsx 3675 2447 4074 2142 CFG_MCASP5_FSX_IN - vin1a_d10
AD4 mmc3_clk 3907 2744 4260 2450 CFG_MMC3_CLK_IN - vin1a_d7
AC4 mmc3_cmd 3892 2768 4242 2470 CFG_MMC3_CMD_IN - vin1a_d6
AC7 mmc3_dat0 3786 2765 4156 2522 CFG_MMC3_DAT0_IN - vin1a_d5
AC6 mmc3_dat1 3673 2961 4053 2667 CFG_MMC3_DAT1_IN - vin1a_d4
AC9 mmc3_dat2 3818 2447 4209 2096 CFG_MMC3_DAT2_IN - vin1a_d3
AC3 mmc3_dat3 3902 2903 4259 2672 CFG_MMC3_DAT3_IN - vin1a_d2
AC8 mmc3_dat4 3905 2622 4259 2342 CFG_MMC3_DAT4_IN - vin1a_d1
AD6 mmc3_dat5 3807 2824 4167 2595 CFG_MMC3_DAT5_IN - vin1a_d0
AB8 mmc3_dat6 3724 2818 4123 2491 CFG_MMC3_DAT6_IN - vin1a_hsync0
AB5 mmc3_dat7 3775 2481 4159 2161 CFG_MMC3_DAT7_IN - vin1a_vsync0
D18 xref_clk0 1971 0 2472 0 CFG_XREF_CLK0_IN vin1a_d0 -
E17 xref_clk1 0 192 0 603 CFG_XREF_CLK1_IN vin1a_clk0 -

Display Subsystem - Video Output Ports

Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI Video Output 2 and DPI Video Output 3.

NOTE

The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.

Every VOUT interface consists of:

  • 24-bit data bus (data[23:0])
  • Horizontal synchronization signal (HSYNC)
  • Vertical synchronization signal (VSYNC)
  • Data enable (DE)
  • Field ID (FID)
  • Pixel clock (CLK)

NOTE

For more information, see the Display Subsystem chapter of the Device TRM.

NOTE

VOUT1, VOUT2 and VOUT3 only qualified for use at 1.8V.

CAUTION

The I/O Timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 7-16.

CAUTION

The I/O Timings provided in this section are valid only for some DSS usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

CAUTION

All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).

Table 7-14, Table 7-15 and Figure 7-6 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 7-14 DPI Video Output i (i = 1..3) Default Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
11.76(3) ns
DPI1/3 in 3.3V mode 13.33(3) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 -2.5 2.5 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 -2.5 2.5 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (vin2a_fld0 clock reference) -2.5 2.5 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (vin2a_fld0 clock reference) -2.5 2.5 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (xref_clk2 clock reference) -2.5 2.5 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (xref_clk2 clock reference) -2.5 2.5 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI3 -2.5 2.5 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI3 -2.5 2.5 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 7-15 DPI Video Output i (i = 1..3) Alternate Switching Characteristics(2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk DPI1/2/3 in 1.8-V mode
DPI2 in 3.3V mode
6.06(3) ns
DPI1/3 in 3.3-V mode 13.33(3) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P * 0.5 – 1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P * 0.5 – 1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI1 1.02 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI1 1.02 4.55 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (vin2a_fld0 clock reference) 1.02 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (vin2a_fld0 clock reference) 1.02 4.55 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI2 (xref_clk2 clock reference) 1.02 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI2 (xref_clk2 clock reference) 1.02 4.55 ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid DPI3 1.02 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid DPI3 1.02 4.55 ns
  1. P = output vouti_clk period in ns.
  2. All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
  3. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
AM5718-HIREL SPRS906_TIMING_DSS_01.gif Figure 7-6 DPI Video Output(1)(2)(3)
  1. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
  2. The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
  3. The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.

In Table 7-16 are presented the specific groupings of signals (IOSET) for use with VOUT2.

Table 7-16 VOUT2 IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
vout2_d23 F2 4 AA4 6
vout2_d22 F3 4 AB3 6
vout2_d21 D1 4 AB9 6
vout2_d20 E2 4 AA3 6
vout2_d19 D2 4 D17 6
vout2_d18 F4 4 G16 6
vout2_d17 C1 4 A21 6
vout2_d16 E4 4 C18 6
vout2_d15 F5 4 A17 6
vout2_d14 E6 4 B17 6
vout2_d13 D3 4 B16 6
vout2_d12 F6 4 D15 6
vout2_d11 D5 4 A15 6
vout2_d10 C2 4 B15 6
vout2_d9 C3 4 A20 6
vout2_d8 C4 4 E15 6
vout2_d7 B2 4 D12 6
vout2_d6 D6 4 C12 6
vout2_d5 C5 4 F13 6
vout2_d4 A3 4 E12 6
vout2_d3 B3 4 J11 6
vout2_d2 B4 4 G13 6
vout2_d1 B5 4 J14 6
vout2_d0 A4 4 B14 6
vout2_vsync G6 4 F20 6
vout2_hsync G1 4 E21 6
vout2_clk H7 4 B26 6
vout2_fld E1 4 F21 6
vout2_de G2 4 C23 6

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

Virtual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-17 Virtual Functions Mapping for VOUT1 for a definition of the Virtual modes.

Table 7-17 presents the values for DELAYMODE bitfield.

Table 7-17 Virtual Functions Mapping for DSS VOUT1

BALL BALL NAME Delay Mode Value MUXMODE
DSS_VIRTUAL1 0 3
H3 gpmc_ad15 14 vout3_d15
D9 vout1_d9 15 vout1_d9
N7 gpmc_a8 15 vout3_hsync
L6 gpmc_ad4 14 vout3_d4
E8 vout1_d8 15 vout1_d8
M6 gpmc_ad0 14 vout3_d0
F9 vout1_d5 15 vout1_d5
J3 gpmc_ad13 14 vout3_d13
T6 gpmc_a2 15 vout3_d18
M2 gpmc_ad1 14 vout3_d1
P6 gpmc_a4 15 vout3_d20
B10 vout1_de 15 vout1_de
B7 vout1_d16 15 vout1_d16
R5 gpmc_a6 15 vout3_d22
A9 vout1_d21 15 vout1_d21
H2 gpmc_ad14 14 vout3_d14
T9 gpmc_a1 15 vout3_d17
E7 vout1_d7 15 vout1_d7
C11 vout1_hsync 15 vout1_hsync
D11 vout1_clk 15 vout1_clk
P1 gpmc_cs3 15 vout3_clk
B9 vout1_d22 15 vout1_d22
G11 vout1_d3 15 vout1_d3
R4 gpmc_a9 15 vout3_vsync
D8 vout1_d11 15 vout1_d11
J2 gpmc_ad11 14 vout3_d11
L3 gpmc_ad6 14 vout3_d6
D7 vout1_d10 15 vout1_d10
L5 gpmc_ad2 14 vout3_d2
F10 vout1_d2 15 vout1_d2
M1 gpmc_ad3 14 vout3_d3
P5 gpmc_a7 15 vout3_d23
T7 gpmc_a3 15 vout3_d19
A7 vout1_d18 15 vout1_d18
C7 vout1_d15 15 vout1_d15
J1 gpmc_ad10 14 vout3_d10
L2 gpmc_ad7 14 vout3_d7
N9 gpmc_a10 15 vout3_de
F11 vout1_d0 15 vout1_d0
G10 vout1_d1 15 vout1_d1
R9 gpmc_a5 15 vout3_d21
L1 gpmc_ad8 14 vout3_d8
F8 vout1_d6 15 vout1_d6
L4 gpmc_ad5 14 vout3_d5
A10 vout1_d23 15 vout1_d23
E11 vout1_vsync 15 vout1_vsync
C9 vout1_d20 15 vout1_d20
R6 gpmc_a0 15 vout3_d16
A8 vout1_d19 15 vout1_d19
E9 vout1_d4 15 vout1_d4
H1 gpmc_ad12 14 vout3_d12
B11 vout1_fld 15 vout1_fld
P9 gpmc_a11 15 vout3_fld
K2 gpmc_ad9 14 vout3_d9
C6 vout1_d13 15 vout1_d13
B8 vout1_d17 15 vout1_d17
A5 vout1_d12 15 vout1_d12
C8 vout1_d14 15 vout1_d14

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-18 Manual Functions Mapping for DSS VOUT1 for a definition of the Manual modes.

Table 7-18 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-18 Manual Functions Mapping for DSS VOUT1

BALL BALL NAME VOUT1_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 0
D11 vout1_clk 0 212 CFG_VOUT1_CLK_OUT vout1_clk
F11 vout1_d0 2502 0 CFG_VOUT1_D0_OUT vout1_d0
G10 vout1_d1 2402 0 CFG_VOUT1_D1_OUT vout1_d1
D7 vout1_d10 2147 0 CFG_VOUT1_D10_OUT vout1_d10
D8 vout1_d11 2249 0 CFG_VOUT1_D11_OUT vout1_d11
A5 vout1_d12 2410 0 CFG_VOUT1_D12_OUT vout1_d12
C6 vout1_d13 2129 0 CFG_VOUT1_D13_OUT vout1_d13
C8 vout1_d14 2279 0 CFG_VOUT1_D14_OUT vout1_d14
C7 vout1_d15 2266 23 CFG_VOUT1_D15_OUT vout1_d15
B7 vout1_d16 1798 0 CFG_VOUT1_D16_OUT vout1_d16
B8 vout1_d17 2243 0 CFG_VOUT1_D17_OUT vout1_d17
A7 vout1_d18 2127 0 CFG_VOUT1_D18_OUT vout1_d18
A8 vout1_d19 2096 0 CFG_VOUT1_D19_OUT vout1_d19
F10 vout1_d2 2375 0 CFG_VOUT1_D2_OUT vout1_d2
C9 vout1_d20 2105 0 CFG_VOUT1_D20_OUT vout1_d20
A9 vout1_d21 2120 0 CFG_VOUT1_D21_OUT vout1_d21
B9 vout1_d22 2013 65 CFG_VOUT1_D22_OUT vout1_d22
A10 vout1_d23 1887 0 CFG_VOUT1_D23_OUT vout1_d23
G11 vout1_d3 2429 0 CFG_VOUT1_D3_OUT vout1_d3
E9 vout1_d4 2639 0 CFG_VOUT1_D4_OUT vout1_d4
F9 vout1_d5 2319 0 CFG_VOUT1_D5_OUT vout1_d5
F8 vout1_d6 2227 0 CFG_VOUT1_D6_OUT vout1_d6
E7 vout1_d7 2309 0 CFG_VOUT1_D7_OUT vout1_d7
E8 vout1_d8 1999 0 CFG_VOUT1_D8_OUT vout1_d8
D9 vout1_d9 2276 0 CFG_VOUT1_D9_OUT vout1_d9
B10 vout1_de 1933 0 CFG_VOUT1_DE_OUT vout1_de
B11 vout1_fld 1825 0 CFG_VOUT1_FLD_OUT vout1_fld
C11 vout1_hsync 1741 13 CFG_VOUT1_HSYNC_OUT vout1_hsync
E11 vout1_vsync 2338 0 CFG_VOUT1_VSYNC_OUT vout1_vsync

Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-19 Manual Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.

Table 7-19 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-19 Manual Functions Mapping for DSS VOUT2 IOSET1

BALL BALL NAME VOUT2_IOSET1_MANUAL1 VOUT2_IOSET1_MANUAL2 VOUT2_IOSET1_MANUAL3 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4
E1 vin2a_clk0 2571 0 1059 0 1025 0 CFG_VIN2A_CLK0_OUT vout2_fld
F2 vin2a_d0 2124 0 589 0 577 0 CFG_VIN2A_D0_OUT vout2_d23
F3 vin2a_d1 2103 0 568 0 557 0 CFG_VIN2A_D1_OUT vout2_d22
D3 vin2a_d10 2091 0 557 0 545 0 CFG_VIN2A_D10_OUT vout2_d13
F6 vin2a_d11 2142 0 608 0 596 0 CFG_VIN2A_D11_OUT vout2_d12
D5 vin2a_d12 2920 385 1816 255 1783 276 CFG_VIN2A_D12_OUT vout2_d11
C2 vin2a_d13 2776 322 1872 192 1838 213 CFG_VIN2A_D13_OUT vout2_d10
C3 vin2a_d14 2904 0 1769 0 1757 0 CFG_VIN2A_D14_OUT vout2_d9
C4 vin2a_d15 2670 257 1665 127 1632 148 CFG_VIN2A_D15_OUT vout2_d8
B2 vin2a_d16 2814 155 1908 31 1878 43 CFG_VIN2A_D16_OUT vout2_d7
D6 vin2a_d17 3002 199 1897 69 1865 89 CFG_VIN2A_D17_OUT vout2_d6
C5 vin2a_d18 1893 0 358 0 347 0 CFG_VIN2A_D18_OUT vout2_d5
A3 vin2a_d19 1698 0 163 0 151 0 CFG_VIN2A_D19_OUT vout2_d4
D1 vin2a_d2 2193 0 658 0 646 0 CFG_VIN2A_D2_OUT vout2_d21
B3 vin2a_d20 1736 0 202 0 190 0 CFG_VIN2A_D20_OUT vout2_d3
B4 vin2a_d21 1636 0 101 0 89 0 CFG_VIN2A_D21_OUT vout2_d2
B5 vin2a_d22 1628 0 93 0 81 0 CFG_VIN2A_D22_OUT vout2_d1
A4 vin2a_d23 1538 0 0 0 0 0 CFG_VIN2A_D23_OUT vout2_d0
E2 vin2a_d3 1997 0 462 0 450 0 CFG_VIN2A_D3_OUT vout2_d20
D2 vin2a_d4 2528 0 993 0 982 0 CFG_VIN2A_D4_OUT vout2_d19
F4 vin2a_d5 2038 0 503 0 492 0 CFG_VIN2A_D5_OUT vout2_d18
C1 vin2a_d6 1746 0 211 0 200 0 CFG_VIN2A_D6_OUT vout2_d17
E4 vin2a_d7 2213 0 678 0 666 0 CFG_VIN2A_D7_OUT vout2_d16
F5 vin2a_d8 2268 0 733 0 721 0 CFG_VIN2A_D8_OUT vout2_d15
E6 vin2a_d9 2170 0 635 0 623 0 CFG_VIN2A_D9_OUT vout2_d14
G2 vin2a_de0 2102 0 568 0 556 0 CFG_VIN2A_DE0_OUT vout2_de
H7 vin2a_fld0 0 983 1398 1185 1385 1202 CFG_VIN2A_FLD0_OUT vout2_clk
G1 vin2a_hsync0 2482 0 974 0 936 0 CFG_VIN2A_HSYNC0_OUT vout2_hsync
G6 vin2a_vsync0 2296 0 784 0 750 0 CFG_VIN2A_VSYNC0_OUT vout2_vsync

Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-20 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual modes.

Table 7-20 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-20 Manual Functions Mapping for DSS VOUT2 IOSET2

BALL BALL NAME VOUT2_IOSET2_MANUAL1 VOUT2_IOSET2_MANUAL2 VOUT2_IOSET2_MANUAL3 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 6
E21 gpio6_14 1983 0 79 0 68 0 CFG_GPIO6_14_OUT vout2_hsync
F20 gpio6_15 2159 0 158 0 148 0 CFG_GPIO6_15_OUT vout2_vsync
F21 gpio6_16 1864 0 0 0 0 0 CFG_GPIO6_16_OUT vout2_fld
B14 mcasp1_aclkr 2614 0 1255 0 1270 0 CFG_MCASP1_ACLKR_OUT vout2_d0
G13 mcasp1_axr2 2705 0 1350 0 1360 0 CFG_MCASP1_AXR2_OUT vout2_d2
J11 mcasp1_axr3 2865 0 1210 0 1219 0 CFG_MCASP1_AXR3_OUT vout2_d3
E12 mcasp1_axr4 2759 0 1404 0 1413 0 CFG_MCASP1_AXR4_OUT vout2_d4
F13 mcasp1_axr5 2980 0 1325 0 1335 0 CFG_MCASP1_AXR5_OUT vout2_d5
C12 mcasp1_axr6 2634 0 1275 0 1289 0 CFG_MCASP1_AXR6_OUT vout2_d6
D12 mcasp1_axr7 2658 0 1302 0 1311 0 CFG_MCASP1_AXR7_OUT vout2_d7
J14 mcasp1_fsr 2818 0 1163 0 1172 0 CFG_MCASP1_FSR_OUT vout2_d1
E15 mcasp2_aclkr 2728 0 1373 0 1382 0 CFG_MCASP2_ACLKR_OUT vout2_d8
B15 mcasp2_axr0 2513 0 319 534 308 560 CFG_MCASP2_AXR0_OUT vout2_d10
A15 mcasp2_axr1 2712 0 1357 0 1366 0 CFG_MCASP2_AXR1_OUT vout2_d11
D15 mcasp2_axr4 2529 0 1169 0 1184 0 CFG_MCASP2_AXR4_OUT vout2_d12
B16 mcasp2_axr5 2376 0 543 478 1029 0 CFG_MCASP2_AXR5_OUT vout2_d13
B17 mcasp2_axr6 2620 0 1265 0 1274 0 CFG_MCASP2_AXR6_OUT vout2_d14
A17 mcasp2_axr7 2492 0 354 483 845 0 CFG_MCASP2_AXR7_OUT vout2_d15
A20 mcasp2_fsr 2358 0 12 487 513 0 CFG_MCASP2_FSR_OUT vout2_d9
C18 mcasp4_aclkx 2524 0 1165 0 1179 0 CFG_MCASP4_ACLKX_OUT vout2_d16
G16 mcasp4_axr0 2578 0 797 0 806 0 CFG_MCASP4_AXR0_OUT vout2_d18
D17 mcasp4_axr1 2253 0 750 0 759 0 CFG_MCASP4_AXR1_OUT vout2_d19
A21 mcasp4_fsx 2478 0 823 0 832 0 CFG_MCASP4_FSX_OUT vout2_d17
AA3 mcasp5_aclkx 4672 1737 3256 1798 3226 1837 CFG_MCASP5_ACLKX_OUT vout2_d20
AB3 mcasp5_axr0 4642 1286 3226 1347 3196 1386 CFG_MCASP5_AXR0_OUT vout2_d22
AA4 mcasp5_axr1 4625 725 3209 786 3179 825 CFG_MCASP5_AXR1_OUT vout2_d23
AB9 mcasp5_fsx 4565 1062 3149 1123 3119 1162 CFG_MCASP5_FSX_OUT vout2_d21
B26 xref_clk2 0 49 1359 466 1341 512 CFG_XREF_CLK2_OUT vout2_clk
C23 xref_clk3 1947 0 36 0 45 0 CFG_XREF_CLK3_OUT vout2_de

Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT3. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-21 Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.

Table 7-21 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-21 Manual Functions Mapping for DSS VOUT3

BALL BALL NAME VOUT3_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 3
R6 gpmc_a0 2395 0 CFG_GPMC_A0_OUT vout3_d16
T9 gpmc_a1 2412 0 CFG_GPMC_A1_OUT vout3_d17
N9 gpmc_a10 2473 0 CFG_GPMC_A10_OUT vout3_de
P9 gpmc_a11 2906 0 CFG_GPMC_A11_OUT vout3_fld
T6 gpmc_a2 2360 0 CFG_GPMC_A2_OUT vout3_d18
T7 gpmc_a3 2391 0 CFG_GPMC_A3_OUT vout3_d19
P6 gpmc_a4 2626 0 CFG_GPMC_A4_OUT vout3_d20
R9 gpmc_a5 2338 0 CFG_GPMC_A5_OUT vout3_d21
R5 gpmc_a6 2374 0 CFG_GPMC_A6_OUT vout3_d22
P5 gpmc_a7 2432 0 CFG_GPMC_A7_OUT vout3_d23
N7 gpmc_a8 3155 0 CFG_GPMC_A8_OUT vout3_hsync
R4 gpmc_a9 2309 0 CFG_GPMC_A9_OUT vout3_vsync
M6 gpmc_ad0 2360 0 CFG_GPMC_AD0_OUT vout3_d0
M2 gpmc_ad1 2420 0 CFG_GPMC_AD1_OUT vout3_d1
J1 gpmc_ad10 2235 0 CFG_GPMC_AD10_OUT vout3_d10
J2 gpmc_ad11 2253 0 CFG_GPMC_AD11_OUT vout3_d11
H1 gpmc_ad12 1949 427 CFG_GPMC_AD12_OUT vout3_d12
J3 gpmc_ad13 2318 0 CFG_GPMC_AD13_OUT vout3_d13
H2 gpmc_ad14 2123 0 CFG_GPMC_AD14_OUT vout3_d14
H3 gpmc_ad15 2195 29 CFG_GPMC_AD15_OUT vout3_d15
L5 gpmc_ad2 2617 0 CFG_GPMC_AD2_OUT vout3_d2
M1 gpmc_ad3 2350 0 CFG_GPMC_AD3_OUT vout3_d3
L6 gpmc_ad4 2324 0 CFG_GPMC_AD4_OUT vout3_d4
L4 gpmc_ad5 2371 0 CFG_GPMC_AD5_OUT vout3_d5
L3 gpmc_ad6 2231 0 CFG_GPMC_AD6_OUT vout3_d6
L2 gpmc_ad7 2440 0 CFG_GPMC_AD7_OUT vout3_d7
L1 gpmc_ad8 2479 0 CFG_GPMC_AD8_OUT vout3_d8
K2 gpmc_ad9 2355 0 CFG_GPMC_AD9_OUT vout3_d9
P1 gpmc_cs3 0 641 CFG_GPMC_CS3_OUT vout3_clk

Display Subsystem - High-Definition Multimedia Interface (HDMI)

The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p @60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is supported (differential).

NOTE

For more information, see the High-Definition Multimedia Interface chapter of the device TRM

Camera Serial Interface 2 CAL bridge (CSI2)

NOTE

For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the device TRM

The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external image sensor, data from memory. The CAL is a key component for the following multimedia applications: camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces (primary and secondary):

  • The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with four data lanes.
  • The secondary serial interface (CSI2 Port B) is compliant with MIPI CSI-2 protocol with two data lanes.

CSI-2 MIPI D-PHY-1.5 V and 1.8 V

The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2 specification v1.00, with 4 data differential lanes plus 1 clock differential lane in synchronous mode, double data rate:

  • 1.5 Gbps (750 MHz) @OPP_NOM for each lane.

The CSI-2 port B is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2 specification v1.00, with 2 data lanes plus 1 clock lane (differential) in synchronous mode, double data rate:

  • 1.5 Gbps (750 MHz) @OPP_NOM for each lane, in synchronous mode.

External Memory Interface (EMIF)

The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard compliant DDR3 and DDR3L SDRAM devices with the following features:

  • 16-bit or 32-bit data path to external SDRAM memory
  • Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices
  • One interface with associated DDR3/DDR3L PHYs

NOTE

For more information, see the EMIF Controller section of the Device TRM.

General-Purpose Memory Controller (GPMC)

The GPMC is the unified memory controller that interfaces external memory devices such as:

  • Asynchronous SRAM-like memories and ASIC devices
  • Asynchronous page mode and synchronous burst NOR flash
  • NAND flash

NOTE

For more information, see the General-Purpose Memory Controller section of the Device TRM.

GPMC/NOR Flash Interface Synchronous Timing

CAUTION

The I/O Timings provided in this section are valid only for some GPMC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-22 and Table 7-23 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-7, Figure 7-8, Figure 7-9, Figure 7-10, Figure 7-11 and Figure 7-12).

Table 7-22 GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F12 tsu(dV-clkH) Setup time, read gpmc_ad[15:0] valid before gpmc_clk high 3 ns
F13 th(clkH-dV) Hold time, read gpmc_ad[15:0] valid after gpmc_clk high 1.1 ns
F21 tsu(waitV-clkH) Setup time, gpmc_wait[1:0] valid before gpmc_clk high 2.5 ns
F22 th(clkH-waitV) Hold Time, gpmc_wait[1:0] valid after gpmc_clk high 1.3 ns

NOTE

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the Device TRM.

Table 7-23 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F0 tc(clk) Cycle time, output clock gpmc_clk period 11.3 ns
F2 td(clkH-nCSV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition F – 1.7 (7) F + 5.58 (7) ns
F3 td(clkH-nCSIV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid E – 1.7 (6) E + 4.2 (6) ns
F4 td(ADDV-clk) Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge B – 1.8 (3) B + 4.3 (3) ns
F5 td(clkH-ADDIV) Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid –1.8 ns
F6 td(nBEV-clk) Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge B – 4.3 (3) B + 1.5 (3) ns
F7 td(clkH-nBEIV) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid D – 1.5 (5) D + 4.3 (5) ns
F8 td(clkH-nADV) Delay time, gpmc_clk rising edge to gpmc_advn_ale transition G – 1.3 (8) G + 4.2 (8) ns
F9 td(clkH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid D – 1.3 (5) G + 4.2 (5) ns
F10 td(clkH-nOE) Delay time, gpmc_clk rising edge to gpmc_oen_ren transition H – 1.0 (9) H + 3.2 (9) ns
F11 td(clkH-nOEIV) Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid E – 1.0 (6) E + 3.2 (6) ns
F14 td(clkH-nWE) Delay time, gpmc_clk rising edge to gpmc_wen transition I – 0.9 (10) I + 4.2 (10) ns
F15 td(clkH-Data) Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition J – 2.1 (11) J + 4.6 (11) ns
F17 td(clkH-nBE) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition J – 1.5 (11) J + 4.3 (11) ns
F18 tw(nCSV) Pulse duration, gpmc_cs[7:0] low A (2) ns
F19 tw(nBEV) Pulse duration, gpmc_ben[1:0] low C (4) ns
F20 tw(nADVV) Pulse duration, gpmc_advn_ale low K (12) ns
F23 td(CLK-GPIO) Delay time, gpmc_clk transition to gpio6_16 transition 0.5 7.5 ns

Table 7-24 GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate(1)

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F12 tsu(dV-clkH) Setup time, read gpmc_ad[15:0] valid before gpmc_clk high 2.9 ns
F13 th(clkH-dV) Hold time, read gpmc_ad[15:0] valid after gpmc_clk high 2 ns
F21 tsu(waitV-clkH) Setup time, gpmc_wait[1:0] valid before gpmc_clk high 2.5 ns
F22 th(clkH-waitV) Hold Time, gpmc_wait[1:0] valid after gpmc_clk high 2.1 ns
  1. Total GPMC load on any signal at 3.3 V must not exceed 10 pF.

Table 7-25 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate(1)

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F0 tc(clk) Cycle time, output clock gpmc_clk period (13) 15.04 ns
F2 td(clkH-nCSV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition F + 0.6 (7) F + 7.0 (7) ns
F3 td(clkH-nCSIV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid E + 0.6 (6) E + 7.0 (6) ns
F4 td(ADDV-clk) Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge B – 0.6 (3) B + 7.0 (3) ns
F5 td(clkH-ADDIV) Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid –0.7 ns
F6 td(nBEV-clk) Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge B – 7.0 B + 0.4 ns
F7 td(clkH-nBEIV) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid D – 0.4 D + 7.0 ns
F8 td(clkH-nADV) Delay time, gpmc_clk rising edge to gpmc_advn_ale transition G + 0.7 (8) G + 6.1 (8) ns
F9 td(clkH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid D + 0.7 (5) D + 6.1 (5) ns
F10 td(clkH-nOE) Delay time, gpmc_clk rising edge to gpmc_oen_ren transition H + 0.7 (9) H + 5.1 (9) ns
F11 td(clkH-nOEIV) Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid E + 0.7 (6) E + 5.1 (6) ns
F14 td(clkH-nWE) Delay time, gpmc_clk rising edge to gpmc_wen transition I + 0.7 (10) I + 6.1 (10) ns
F15 td(clkH-Data) Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition J – 0.4 (11) J + 4.9 (11) ns
F17 td(clkH-nBE) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition J – 0.4 (11) J + 4.9 (11) ns
F18 tw(nCSV) Pulse duration, gpmc_cs[7:0] low A (2) ns
F19 tw(nBEV) Pulse duration, gpmc_ben[1:0] low C (4) ns
F20 tw(nADVV) Pulse duration, gpmc_advn_ale low K (12) ns
F23 td(CLK-GPIO) Delay time, gpmc_clk transition to gpio6_16.clkout1 transition (14) 0.5 7.5 ns
  1. Total GPMC load on any signal at 3.3V must not exceed 10pF.
  2. For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
    For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
    For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period with n the page burst access number.
  3. B = ClkActivationTime * GPMC_FCLK
  4. For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst read: C = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For Burst write: C = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n the page burst access number.
  5. For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
  6. For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
  7. For nCS falling edge (CS activated):
    Case GpmcFCLKDivider = 0 :
    F = 0.5 * CSExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1:
    F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
    F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
    F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
    F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
    F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
    F = (3 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
  8. For ADV falling edge (ADV activated):
    Case GpmcFCLKDivider = 0 :
    G = 0.5 * ADVExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
    G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
    For ADV rising edge (ADV desactivated) in Reading mode:
    Case GpmcFCLKDivider = 0:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 4)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 4)
    G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 4)
    G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 3) is a multiple of 4)
    For ADV rising edge (ADV desactivated) in Writing mode:
    Case GpmcFCLKDivider = 0:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 4)
    G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 4)
    G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 4)
    G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 3) is a multiple of 4)
  9. For OE falling edge (OE activated):
    Case GpmcFCLKDivider = 0:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    - H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)
    - H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
    - H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
    - H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
    - H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
    - H = (3 + 0.5 * OEExtraDelay)) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
    For OE rising edge (OE desactivated):
    Case GpmcFCLKDivider = 0:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    - H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)
    - H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
    - H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 4)
    - H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 4)
    - H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 4)
    - H = (3 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 3) is a multiple of 4)
  10. For WE falling edge (WE activated):
    Case GpmcFCLKDivider = 0:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    - I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)
    - I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
    - I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
    - I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
    - I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
    - I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
    For WE rising edge (WE desactivated):
    Case GpmcFCLKDivider = 0:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    - I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)
    - I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
    - I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
    - I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
    - I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
    - I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
  11. J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
  12. For read:
    K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
  13. The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx configuration register bit fields GpmcFCLKDivider
  14. gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK), CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
  15. CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay mode is not timed.
AM5718-HIREL SPRS906_TIMING_GPMC_01.gif Figure 7-7 GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)

  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
AM5718-HIREL SPRS906_TIMING_GPMC_02.gif Figure 7-8 GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)

  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
AM5718-HIREL SPRS906_TIMING_GPMC_03.gif Figure 7-9 GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
  1. In gpmc_csi, i= 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
AM5718-HIREL SPRS906_TIMING_GPMC_04.gif Figure 7-10 GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
AM5718-HIREL SPRS906_TIMING_GPMC_05.gif Figure 7-11 GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
  1. In “gpmc_csi”, i = 0 to 7.
  2. In “gpmc_waitj”, j = 0 to 1.
AM5718-HIREL SPRS906_TIMING_GPMC_06.gif Figure 7-12 GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits - (GpmcFCLKDivider = 0)(1)(2)
  1. In “gpmc_csi”, i = 1 to 7.
  2. In “gpmc_waitj”, j = 0 to 1.

GPMC/NOR Flash Interface Asynchronous Timing

CAUTION

The I/O Timings provided in this section are valid only for some GPMC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-26 and Table 7-27 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-13, Figure 7-14, Figure 7-15, Figure 7-16, Figure 7-17 and Figure 7-18).

Table 7-26 GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
FA5 tacc(DAT) Data Maximum Access Time (GPMC_FCLK cycles) H (1) cycles
FA20 tacc1-pgmode(DAT) Page Mode Successive Data Maximum Access Time (GPMC_FCLK cycles) P (2) cycles
FA21 tacc2-pgmode(DAT) Page Mode First Data Maximum Access Time (GPMC_FCLK cycles) H (1) cycles
- tsu(DV-OEH) Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high 1.9 ns
- th(OEH-DV) Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high 1 ns
  1. H = Access Time * (TimeParaGranularity + 1)
  2. P = PageBurstAccessTime * (TimeParaGranularity + 1)

Table 7-27 GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
- tr(DO) Rising time, gpmc_ad[15:0] output data 0.447 4.067 ns
- tf(DO) Fallling time, gpmc_ad[15:0] output data 0.43 4.463 ns
FA0 tw(nBEV) Pulse duration, gpmc_ben[1:0] valid time N (1) ns
FA1 tw(nCSV) Pulse duration, gpmc_cs[7:0] low A (2) ns
FA3 td(nCSV-nADVIV) Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid B - 2 (3) B + 4 (3) ns
FA4 td(nCSV-nOEIV) Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read) C - 2 (4) C + 4 (4) ns
FA9 td(AV-nCSV) Delay time, address bus valid to gpmc_cs[7:0] valid J - 2 (5) J + 4 (5) ns
FA10 td(nBEV-nCSV) Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid J - 2 (5) J + 4 (5) ns
FA12 td(nCSV-nADVV) Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid K - 2 (6) K + 4 (6) ns
FA13 td(nCSV-nOEV) Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid L - 2 (7) L + 4 (7) ns
FA16 tw(AIV) Pulse duration, address invalid between 2 successive R/W accesses G (8) ns
FA18 td(nCSV-nOEIV) Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read) I - 2 (9) I + 4 (9) ns
FA20 tw(AV) Pulse duration, address valid : 2nd, 3rd and 4th accesses D (10) ns
FA25 td(nCSV-nWEV) Delay time, gpmc_cs[7:0] valid to gpmc_wen valid E - 2 (11) E + 4 (11) ns
FA27 td(nCSV-nWEIV) Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid F - 2 (12) F + 4 (12) ns
FA28 td(nWEV-DV) Delay time, gpmc_ wen valid to data bus valid 2 ns
FA29 td(DV-nCSV) Delay time, data bus valid to gpmc_cs[7:0] valid J - 2 (5) J + 4 (5) ns
FA37 td(nOEV-AIV) Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus phase end 2 ns
  1. For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
    For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
  2. For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
  3. For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
    For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
  4. C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
  5. J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
  6. K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
  7. L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
  8. G = Cycle2CycleDelay * GPMC_FCLK * (TimeParaGranularity +1)
  9. I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
  10. D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
  11. E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
  12. F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
AM5718-HIREL SPRS906_TIMING_GPMC_07.gif Figure 7-13 GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
  1. In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
  2. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
  3. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
  4. The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.
AM5718-HIREL SPRS906_TIMING_GPMC_08.gif Figure 7-14 GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)
  1. In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
  2. FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value should be stored inside AccessTime register bits field
  3. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
  4. The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.
AM5718-HIREL SPRS906_TIMING_GPMC_09.gif Figure 7-15 GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)
  1. In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
  2. FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime register bits field.
  3. FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
  4. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
  5. The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.
AM5718-HIREL SPRS906_TIMING_GPMC_10.gif Figure 7-16 GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)
  1. In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
  2. The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.
AM5718-HIREL SPRS906_TIMING_GPMC_11.gif Figure 7-17 GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
  1. In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
  2. FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value should be stored inside AccessTime register bits field.
  3. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
  4. The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.
AM5718-HIREL SPRS906_TIMING_GPMC_12.gif Figure 7-18 GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)
  1. In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
  2. The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.

GPMC/NAND Flash Interface Asynchronous Timing

CAUTION

The I/O Timings provided in this section are valid only for some GPMC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-28 and Table 7-29 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-19, Figure 7-20, Figure 7-21 and Figure 7-22).

Table 7-28 GPMC/NAND Flash Interface Timing Requirements

NO. PARAMETER DESCRIPTION MIN MAX UNIT
GNF12 tacc(DAT) Data maximum access time (GPMC_FCLK Cycles) J (1) cycles
- tsu(DV-OEH) Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high 1.9 ns
- th(OEH-DV) Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high 1 ns
  1. J = AccessTime * (TimeParaGranularity + 1)

Table 7-29 GPMC/NAND Flash Interface Switching Characteristics

NO. PARAMETER DESCRIPTION MIN MAX UNIT
- tr(DO) Rising time, gpmc_ad[15:0] output data 0.447 4.067 ns
- tf(DO) Fallling time, gpmc_ad[15:0] output data 0.43 4.463 ns
GNF0 tw(nWEV) Pulse duration, gpmc_wen valid time A (1) ns
GNF1 td(nCSV-nWEV) Delay time, gpmc_cs[7:0] valid to gpmc_wen valid B - 2 (2) B + 4 (2) ns
GNF2 td(CLEH-nWEV) Delay time, gpmc_ben[1:0] high to gpmc_wen valid C - 2 (3) C + 4 (3) ns
GNF3 td(nWEV-DV) Delay time, gpmc_ad[15:0] valid to gpmc_wen valid D - 2 (4) D + 4 (4) ns
GNF4 td(nWEIV-DIV) Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid E - 2 (5) E + 4 (5) ns
GNF5 td(nWEIV-CLEIV) Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid F - 2 (6) F + 4 (6) ns
GNF6 td(nWEIV-nCSIV) Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid G - 2 (7) G + 4 (7) ns
GNF7 td(ALEH-nWEV) Delay time, gpmc_advn_ale high to gpmc_wen valid C - 2 (3) C + 4 (3) ns
GNF8 td(nWEIV-ALEIV) Delay time, gpmc_wen invalid to gpmc_advn_ale invalid F - 2 (6) F + 4 (6) ns
GNF9 tc(nWE) Cycle time, write cycle time H (8) ns
GNF10 td(nCSV-nOEV) Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid I - 2 (9) I + 4 (9) ns
GNF13 tw(nOEV) Pulse duration, gpmc_oen_ren valid time K (10) ns
GNF14 tc(nOE) Cycle time, read cycle time L (11) ns
GNF15 td(nOEIV-nCSIV) Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid M - 2 (12) M + 4 (12) ns
  1. A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
  2. B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
  3. C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK
  4. D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
  5. E = (WrCycleTime - WEOffTime * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
  6. F = (ADVWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay ) * GPMC_FCLK
  7. G = (CSWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay ) * GPMC_FCLK
  8. H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
  9. I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
  10. K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
  11. L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
  12. M = (CSRdOffTime - OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ) * GPMC_FCLK
AM5718-HIREL SPRS906_TIMING_GPMC_13.gif Figure 7-19 GPMC / NAND Flash - Command Latch Cycle Timing(1)
  1. In gpmc_csi, i = 0 to 7.
AM5718-HIREL SPRS906_TIMING_GPMC_14.gif Figure 7-20 GPMC / NAND Flash - Address Latch Cycle Timing(1)
  1. In gpmc_csi, i = 0 to 7.
AM5718-HIREL SPRS906_TIMING_GPMC_15.gif Figure 7-21 GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
  1. GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
  2. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
  3. In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
AM5718-HIREL SPRS906_TIMING_GPMC_16.gif Figure 7-22 GPMC / NAND Flash - Data Write Cycle Timing(1)
  1. In gpmc_csi, i = 0 to 7.

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

Virtual IO Timings Modes must be used to guaranteed some IO timings for GPMC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-30 Virtual Functions Mapping for GPMC for a definition of the Virtual modes.

Table 7-30 presents the values for DELAYMODE bitfield.

Table 7-30 Virtual Functions Mapping for GPMC

BALL BALL NAME Delay Mode Value MUXMODE
GPMC_VIRTUAL1 0 1 2 3 5 6 14(1) 14(1)
N1 gpmc_advn_ale 15 gpmc_advn_ale gpmc_cs6 gpmc_wait1 gpmc_a2 gpmc_a23
H3 gpmc_ad15 13 gpmc_ad15
L3 gpmc_ad6 13 gpmc_ad6
L5 gpmc_ad2 13 gpmc_ad2
E6 vin2a_d9 9 gpmc_a25
M3 gpmc_wen 15 gpmc_wen
H2 gpmc_ad14 13 gpmc_ad14
R3 gpmc_a13 15 gpmc_a13
N7 gpmc_a8 14 gpmc_a8
T2 gpmc_a14 15 gpmc_a14
L6 gpmc_ad4 13 gpmc_ad4
H4 gpmc_a26 15 gpmc_a26 gpmc_a20
M6 gpmc_ad0 13 gpmc_ad0
N2 gpmc_wait0 15 gpmc_wait0
F6 vin2a_d11 9 gpmc_a23
M2 gpmc_ad1 13 gpmc_ad1
J3 gpmc_ad13 13 gpmc_ad13
T6 gpmc_a2 14 gpmc_a2
L4 gpmc_ad5 13 gpmc_ad5
F5 vin2a_d8 9 gpmc_a26
T1 gpmc_cs0 15 gpmc_cs0
G1 vin2a_hsync0 9 gpmc_a27
P6 gpmc_a4 14 gpmc_a4
N6 gpmc_ben0 15 gpmc_ben0 gpmc_cs4
R5 gpmc_a6 14 gpmc_a6
U2 gpmc_a15 15 gpmc_a15
J2 gpmc_ad11 13 gpmc_ad11
U1 gpmc_a16 15 gpmc_a16
T9 gpmc_a1 14 gpmc_a1
J4 gpmc_a24 15 gpmc_a24 gpmc_a18
J7 gpmc_a23 15 gpmc_a23 gpmc_a17
L1 gpmc_ad8 13 gpmc_ad8
J1 gpmc_ad10 13 gpmc_ad10
H1 gpmc_ad12 13 gpmc_ad12
M7 gpmc_a20 15 gpmc_a20 gpmc_a14
D3 vin2a_d10 9 gpmc_a24
P1 gpmc_cs3 14 gpmc_cs3 gpmc_a1
M5 gpmc_oen_ren 15 gpmc_oen_ren
R4 gpmc_a9 14 gpmc_a9
H6 gpmc_cs1 15 gpmc_cs1 gpmc_a22
M1 gpmc_ad3 13 gpmc_ad3
L2 gpmc_ad7 13 gpmc_ad7
P5 gpmc_a7 14 gpmc_a7
T7 gpmc_a3 14 gpmc_a3
M4 gpmc_ben1 15 gpmc_ben1 gpmc_cs5 gpmc_a3
P7 gpmc_clk 15 gpmc_clk gpmc_cs7 gpmc_wait1
K6 gpmc_a22 15 gpmc_a22 gpmc_a16
P2 gpmc_cs2 15 gpmc_cs2
H7 vin2a_fld0 11 gpmc_a27 gpmc_a18
N9 gpmc_a10 14 gpmc_a10
P4 gpmc_a12 15 gpmc_a12 gpmc_a0
P3 gpmc_a17 15 gpmc_a17
R9 gpmc_a5 14 gpmc_a5
J5 gpmc_a21 15 gpmc_a21 gpmc_a15
H5 gpmc_a27 15 gpmc_a27 gpmc_a21
K2 gpmc_ad9 13 gpmc_ad9
K7 gpmc_a19 15 gpmc_a19 gpmc_a13
J6 gpmc_a25 15 gpmc_a25 gpmc_a19
R6 gpmc_a0 14 gpmc_a0
E1 vin2a_clk0 11 gpmc_a27 gpmc_a17
R2 gpmc_a18 15 gpmc_a18
P9 gpmc_a11 14 gpmc_a11
  1. Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Timers

The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz synchronized timer (COUNTER_32K) that have the following features:

  • Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM) signal
  • Interrupts generated on overflow, compare, and capture
  • Free-running 32-bit upward counter
  • Supported modes:
    • Compare and capture modes
    • Auto-reload mode
    • Start-stop mode
  • On-the-fly read/write register (while counting)

The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following features:

  • Free-running 32-bit upward counter
  • On-the-fly read/write register (while counting)
  • Reset upon occurrence of a timer overflow condition

The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU watchdog timer.

The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop.

NOTE

For additional information on the Timer Module, see the Device TRM.

Inter-Integrated Circuit Interface (I2C)

The device includes 5 inter-integrated circuit (I2C) modules which provide an interface to other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through the I2C module.

NOTE

Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is not supported.

NOTE

Inter-integrated circuit i (i=1 to 5) module is also referred to as I2Ci.

NOTE

For more information, see the Multimaster High-Speed I2C Controller section of the Device TRM.

Table 7-31, Table 7-32 and Figure 7-23 assume testing over the recommended operating conditions and electrical characteristic conditions below.

Table 7-31 Timing Requirements for I2C Input Timings(1)

NO. PARAMETER DESCRIPTION STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 µs
2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs
3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(2) ns
7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0(3) 3.45(4) 0(3) 0.9(4) µs
8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (5) 300(3) ns
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (5) 300(3) ns
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (5) 300(3) ns
12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (5) 300(3) ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
15 Cb (5) Capacitive load for each bus line 400 400 pF
  1. The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
  2. A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
  3. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
  4. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
  5. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Table 7-32 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)(1)

NO. PARAMETER DESCRIPTION Cb = 100 pF MAX Cb = 400 pF (2) UNIT
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 0.294 0.588 µs
2 tsu(SCLH-SDAL) Set-up time, SCL high before SDA low (for a repeated START condition) 160 160 ns
3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a repeated START condition) 160 160 ns
4 tw(SCLL) LOW period of the SCLH clock 160 320 ns
5 tw(SCLH) HIGH period of the SCLH clock 60 120 ns
6 tsu(SDAV-SCLH) Setup time, SDA valid vefore SCL high 10 10 ns
7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0 (3) 70 0 (3) 150 ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for a STOP condition) 160 160 ns
14 tw(SP) Pulse duration, spike (must be suppressed) 0 10 0 10 ns
15 Cb (2) Capacitive load for SDAH and SCLH lines 100 400 pF
16 Cb Capacitive load for SDAH + SDA line and SCLH + SCL line 400 400 pF
  1. I2C HS-Mode is only supported on I2C3/4/5. I2C HS-Mode is not supported on I2C1/2.
  2. For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
  3. A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
AM5718-HIREL SPRS906_TIMING_I2C_01.gif Figure 7-23 I2C Receive Timing

Table 7-33 and Figure 7-24 assume testing over the recommended operating conditions and electrical characteristic conditions below.

Table 7-33 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)

NO. PARAMETER DESCRIPTION STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 µs
17 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs
18 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 ns
22 th(SCLL-SDAV) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45 0 0.9 µs
23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (1) (3) 300(3) ns
25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (1) (3) 300(3) ns
26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (1) (3) 300(3) ns
27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (1) (3) 300(3) ns
28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
29 Cp Capacitance for each I2C pin 10 10 pF
  1. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
  2. Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
  3. These timings apply only to I2C1 and I2C2. I2C3, I2C4, and I2C5 use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model.

NOTE

I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic-1.

AM5718-HIREL SPRS906_TIMING_I2C_02.gif Figure 7-24 I2C Transmit Timing

HDQ / 1-Wire Interface (HDQ1W)

The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to communicate between the master and the slave. The protocols employ an asynchronous return to one mechanism where, after any command, the line is pulled high.

NOTE

For more information, see the HDQ / 1-Wire section of the Device TRM.

HDQ / 1-Wire - HDQ Mode

Table 7-34 and Table 7-35 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-25, Figure 7-26, Figure 7-27 and Figure 7-28).

Table 7-34 HDQ/1-Wire Timing Requirements-HDQ Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 tCYCH Read bit window timing 190 250 µs
2 tHW1 Read one data valid after HDQ low 32(2) 66(2) µs
3 tHW0 Read zero data hold after HDQ low 70(2) 145(2) µs
4 tRSPS Response time from HDQ slave device(1) 190 320 µs
  1. Defined by software.
  2. If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see "HDQ / 1-Wire Switching Characteristics - HDQ Mode" and the HDQ/1-Wire chapter of the TRM.

Table 7-35 HDQ / 1-Wire Switching Characteristics - HDQ Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
5 tB Break timing 190 µs
6 tBR Break recovery time 40 µs
7 tCYCD Write bit windows timing 190 µs
8 tDW1 Write one data valid after HDQ low 0.5 50 µs
9 tDW0 Write zero data hold after HDQ low 86 145 µs
AM5718-HIREL SPRS906_TIMING_HDQ1W_01.gif Figure 7-25 HDQ Break and Break Recovery Timing - HDQ Interface Writing to Slave
AM5718-HIREL SPRS906_TIMING_HDQ1W_02.gif Figure 7-26 Device HDQ Interface Bit Read Timing (Data)
AM5718-HIREL SPRS906_TIMING_HDQ1W_03.gif Figure 7-27 Device HDQ Interface Bit Write Timing (Command / Address or Data)
AM5718-HIREL SPRS906_TIMING_HDQ1W_04.gif Figure 7-28 HDQ Communication Timing

HDQ/1-Wire-1-Wire Mode

Table 7-36 and Table 7-37 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-29, Figure 7-30 and Figure 7-31).

Table 7-36 HDQ / 1-Wire Timing Requirements - 1-Wire Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
10 tPDH Presence pulse delay high 15 60 µs
11 tPDL Presence pulse delay low 60 240 µs
12 tRDV Read data valid time tLOWR 15 µs
13 tREL Read data release time 0 45 µs

Table 7-37 HDQ / 1-Wire Switching Characteristics - 1-Wire Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
14 tRSTL Reset time low 480 960 µs
15 tRSTH Reset time high 480 µs
16 tSLOT Bit cycle time 60 120 µs
17 tLOW1 Write bit-one time 1 15 µs
18 tLOW0 Write bit-zero time(2) 60 120 µs
19 tREC Recovery time 1 µs
20 tLOWR Read bit strobe time(1) 1 15 µs
  1. tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
  2. tLOWR must be less than tSLOT.
AM5718-HIREL SPRS906_TIMING_HDQ1W_05.gif Figure 7-29 1-Wire-Break (Reset)
AM5718-HIREL SPRS906_TIMING_HDQ1W_06.gif Figure 7-30 1-Wire-Read Bit (Data)
AM5718-HIREL SPRS906_TIMING_HDQ1W_07.gif Figure 7-31 1-Wire-Write Bit-One Timing (Command / Address or Data)

Universal Asynchronous Receiver Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one UART supports IrDA features. Each UART can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices

The UARTi (where i = 1 to 10) include the following features:

  • 16C750 compatibility
  • 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
  • Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed functional clock of 48 MHz or 192 MHz
  • Break character detection and generation
  • Configurable data format:
    • Data bit: 5, 6, 7, or 8 bits
    • Parity bit: Even, odd, none
    • Stop-bit: 1, 1.5, 2 bit(s)
  • Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
  • Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
  • Only UART3 supports IrDA

NOTE

For more information, see the UART section of the Device TRM.

Table 7-38, Table 7-39 and Figure 7-32 assume testing over the recommended operating conditions and electrical characteristic conditions below.

Table 7-38 Timing Requirements for UART

NO. PARAMETER DESCRIPTION MIN MAX UNIT
4 tw(RX) Pulse width, receive data bit, 15/30/100pF high or low 0.96U(1) 1.05U(1) ns
5 tw(CTS) Pulse width, receive start bit, 15/30/100pF high or low 0.96U(1) 1.05U(1) ns
td(RTS-TX) Delay time, transmit start bit to transmit data P(2) ns
td(CTS-TX) Delay time, receive start bit to transmit data P(2) ns
  1. U = UART baud time = 1/programmed baud rate
  2. P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).

Table 7-39 Switching Characteristics Over Recommended Operating Conditions for UART

NO. PARAMETER DESCRIPTION MIN MAX UNIT
f(baud) Maximum programmable baud rate 15 pF 12 MHz
30 pF 0.23
100 pF 0.115
2 tw(TX) Pulse width, transmit data bit, 15/30/100 pF high or low U - 2(1) U + 2(1) ns
3 tw(RTS) Pulse width, transmit start bit, 15/30/100 pF high or low U - 2(1) U + 2(1) ns
  1. U = UART baud time = 1/programmed baud rate
AM5718-HIREL SPRS906_TIMING_UART_01.gif Figure 7-32 UART Timing

Multichannel Serial Peripheral Interface (McSPI)

The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip selects) and are able to work as both master and slave.


The McSPI modules include the following main features:

  • Serial clock with programmable frequency, polarity, and phase for each channel
  • Wide selection of SPI word lengths, ranging from 4 to 32 bits
  • Up to four master channels, or single channel in slave mode
  • Master multichannel mode:
    • Full duplex/half duplex
    • Transmit-only/receive-only/transmit-and-receive modes
    • Flexible input/output (I/O) port controls per channel
    • Programmable clock granularity
    • SPI configuration per channel. This means, clock definition, polarity enabling and word width
  • Power management through wake-up capabilities
  • Programmable timing control between chip select and external clock generation
  • Built-in FIFO available for a single channel.
  • Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.

NOTE

For more information, see the Serial Communication Interface section of the device TRM.

NOTE

The McSPIm module (m = 1 to 4) is also referred to as SPIm.

CAUTION

The I/O timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETS are defined in Table 7-42.

Table 7-40, Figure 7-33 and Figure 7-34 present Timing Requirements for McSPI - Master Mode.

Table 7-40 Timing Requirements for SPI - Master Mode (1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SM1 tc(SPICLK) Cycle time, spi_sclk (1) (2) SPI1/2/3/4 20.8 (3) ns
SM2 tw(SPICLKL) Typical Pulse duration, spi_sclk low (1) 0.5*P-1 (4) ns
SM3 tw(SPICLKH) Typical Pulse duration, spi_sclk high (1) 0.5*P-1 (4) ns
SM4 tsu(MISO-SPICLK) Setup time, spi_d[x] valid before spi_sclk active edge (1) 3.5 ns
SM5 th(SPICLK-MISO) Hold time, spi_d[x] valid after spi_sclk active edge (1) 3.7 ns
SM6 td(SPICLK-SIMO) Delay time, spi_sclk active edge to spi_d[x] transition (1) SPI1 -3.57 4.1 ns
SPI2 -3.9 3.6 ns
SPI3 -4.9 4.7
SPI4 -4.3 4.5
SM7 td(CS-SIMO) Delay time, spi_cs[x] active edge to spi_d[x] transition 5 ns
SM8 td(CS-SPICLK) Delay time, spi_cs[x] active to spi_sclk first edge (1) MASTER_PHA0 (5) B-4.2 (6) ns
MASTER_PHA1 (5) A-4.2 (7) ns
SM9 td(SPICLK-CS) Delay time, spi_sclk last edge to spi_cs[x] inactive (1) MASTER_PHA0 (5) A-4.2 (7) ns
MASTER_PHA1 (5) B-4.2 (6) ns
  1. This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
  2. Related to the SPI_CLK maximum frequency.
  3. 20.8ns cycle time = 48MHz
  4. P = SPICLK period.
  5. SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
  6. B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
  7. When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
AM5718-HIREL SPRS906_TIMING_McSPI_01.gif Figure 7-33 McSPI - Master Mode Transmit
AM5718-HIREL SPRS906_TIMING_McSPI_02.gif Figure 7-34 McSPI - Master Mode Receive

Table 7-41, Figure 7-35 and Figure 7-36 present Timing Requirements for McSPI - Slave Mode.

Table 7-41 Timing Requirements for SPI - Slave Mode

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SS1 (1) tc(SPICLK) Cycle time, spi_sclk 62.5 (2) (3) ns
SS2 (1) tw(SPICLKL) Typical Pulse duration, spi_sclk low 0.45*P (4) ns
SS3 (1) tw(SPICLKH) Typical Pulse duration, spi_sclk high 0.45*P (4) ns
SS4 (1) tsu(SIMO-SPICLK) Setup time, spi_d[x] valid before spi_sclk active edge 5 ns
SS5 (1) th(SPICLK-SIMO) Hold time, spi_d[x] valid after spi_sclk active edge 5 ns
SS6 (1) td(SPICLK-SOMI) Delay time, spi_sclk active edge to mcspi_somi transition SPI1/2/3 2 26.6 ns
SPI4 2 20.1 ns
SS7 (5) td(CS-SOMI) Delay time, spi_cs[x] active edge to mcspi_somi transition 20.95 ns
SS8 (1) tsu(CS-SPICLK) Setup time, spi_cs[x] valid before spi_sclk first edge 5 ns
SS9 (1) th(SPICLK-CS) Hold time, spi_cs[x] valid after spi_sclk last edge SPI1/2 5 ns
SPI3 7.5 ns
SPI4 6 ns
  1. This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
  2. When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
  3. 62.5ns Cycle time = 16 MHz
  4. P = SPICLK period.
  5. PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
AM5718-HIREL SPRS906_TIMING_McSPI_03.gif Figure 7-35 McSPI - Slave Mode Transmit
AM5718-HIREL SPRS906_TIMING_McSPI_04.gif Figure 7-36 McSPI - Slave Mode Receive

In Table 7-42 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.

Table 7-42 McSPI3/4 IOSETs

SIGNALS IOSET1 IOSET2 IOSET3 IOSET4 IOSET5
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
McSPI3
spi3_cs0 D11 8 V9 7 A12 3 D17 2 AC9 1
spi3_cs1 B11 8 AC3 1 E14 3 B11 8 AC3 1
spi3_cs2 F11 8 F11 8 F11 8
spi3_cs3 A10 8 A10 8 A10 8
spi3_d0 C11 8 W9 7 B13 3 G16 2 AC6 1
spi3_d1 B10 8 Y1 7 A11 3 A21 2 AC7 1
spi3_sclk E11 8 V2 7 B12 3 C18 2 AC4 1
McSPI4
spi4_cs0 P9 8 F3 8 U6 7 AA4 2 AB5 1
spi4_cs1 P4 8 P4 8 Y1 8 Y1 8 Y1 8
spi4_cs2 R3 8 R3 8 W9 8 W9 8 W9 8
spi4_cs3 T2 8 T2 8 V9 8 V9 8 V9 8
spi4_d0 N9 8 F2 8 V6 7 AB3 2 AB8 1
spi4_d1 R4 8 G6 8 U7 7 AB9 2 AD6 1
spi4_sclk N7 8 G1 8 V7 7 AA3 2 AC8 1

Quad Serial Peripheral Interface (QSPI)

The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.

General SPI features:

  • Programmable clock divider
  • Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
  • 4 external chip select signals
  • Support for 3-, 4- or 6-pin SPI interface
  • Programmable CS_N to DOUT delay from 0 to 3 DCLKs
  • Programmable signal polarities
  • Programmable active clock edge
  • Software controllable interface allowing for any type of SPI transfer

NOTE

For more information, see the Quad Serial Peripheral Interface section of the Device TRM.

CAUTION

The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode 3).

CAUTION

The I/O Timings provided in this section are valid only for some QSPI usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-43 and Table 7-44 Present Timing and Switching Characteristics for Quad SPI Interface.

Table 7-43 Switching Characteristics for QSPI

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
Q1 tc(SCLK) Cycle time, sclk Default Timing Mode, Clock Mode 0 11.71 ns
Default Timing Mode, Clock Mode 3 20.8 ns
Q2 tw(SCLKL) Pulse duration, sclk low Y*P-1 (1) ns
Q3 tw(SCLKH) Pulse duration, sclk high Y*P-1 (1) ns
Q4 td(CS-SCLK) Delay time, sclk falling edge to cs active edge, CS3:0 Default Timing Mode -M*P-1.6 (2) (3) -M*P+2.6 (2) (3) ns
Q5 td(SCLK-CS) Delay time, sclk falling edge to cs inactive edge, CS3:0 Default Timing Mode N*P-1.6 (2) (3) N*P+2.6 (2) (3) ns
Q6 td(SCLK-D0) Delay time, sclk falling edge to d[0] transition Default Timing Mode -1.6 2.6 ns
Q7 tena(CS-D0LZ) Enable time, cs active edge to d[0] driven (lo-z) -P-3.5 -P+2.5 ns
Q8 tdis(CS-D0Z) Disable time, cs active edge to d[0] tri-stated (hi-z) -P-2.5 -P+2.0 ns
Q9 td(SCLK-D0) Delay time, sclk first falling edge to first d[0] transition PHA=0 Only, Default Timing Mode -1.6 2.6 ns
  1. The Y parameter is defined as follows:
    If DCLK_DIV is 0 or ODD then, Y equals 0.5.
    If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
    For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
  2. P = SCLK period.
  3. M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
    M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
    N = 2 when Clock Mode 0.
    N = 3 when Clock Mode 3.
AM5718-HIREL SPRS906_TIMING_QSPI1_01.gif Figure 7-37 QSPI Read (Clock Mode 3)
AM5718-HIREL SPRS906_TIMING_QSPI1_02.gif Figure 7-38 QSPI Read (Clock Mode 0)

CAUTION

The I/O Timings provided in this section are valid only for some QSPI usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-44 Timing Requirements for QSPI(3)(2)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
Q2 tsu(D-RTCLK) Setup time, d[3:0] valid before falling rtclk edge Default Timing Mode, Clock Mode 0 4.6 ns
tsu(D-SCLK) Setup time, d[3:0] valid before falling sclk edge Default Timing Mode, Clock Mode 3 12.3 ns
Q13 th(RTCLK-D) Hold time, d[3:0] valid after falling rtclk edge Default Timing Mode, Clock Mode 0 -0.1 ns
th(SCLK-D) Hold time, d[3:0] valid after falling sclk edge Default Timing Mode, Clock Mode 3 0.1 ns
Q14 tsu(D-SCLK) Setup time, final d[3:0] bit valid before final falling sclk edge Default Timing Mode, Clock Mode 3 12.3-P (1) ns
Q15 th(SCLK-D) Hold time, final d[3:0] bit valid after final falling sclk edge Default Timing Mode, Clock Mode 3 0.1+P (1) ns
  1. P = SCLK period.
  2. Clock Modes 1 and 2 are not supported.
  3. The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that launch data on the falling edge in Clock Modes 0 and 3.
AM5718-HIREL SPRS906_TIMING_QSPI1_03.gif Figure 7-39 QSPI Write (Clock Mode 3)
AM5718-HIREL SPRS906_TIMING_QSPI1_04.gif Figure 7-40 QSPI Write (Clock Mode 0)

CAUTION

The I/O Timings provided in this section are valid only for some QSPI usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module chapter in the Device TRM.

Manual IO Timings Modes must be used to guaranteed some IO timings for QSPI. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-45 Manual Functions Mapping for QSPI for a definition of the Manual modes.

Table 7-45 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-45 Manual Functions Mapping for QSPI

BALL BALL NAME QSPI1_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 1
T7 gpmc_a3 0 0 CFG_GPMC_A3_OUT qspi1_cs2
P6 gpmc_a4 0 0 CFG_GPMC_A4_OUT qspi1_cs3
R3 gpmc_a13 0 0 CFG_GPMC_A13_IN qspi1_rtclk
T2 gpmc_a14 2247 1186 CFG_GPMC_A14_IN qspi1_d3
U2 gpmc_a15 2176 1197 CFG_GPMC_A15_IN qspi1_d2
U1 gpmc_a16 2229 1268 CFG_GPMC_A16_IN qspi1_d0
U1 gpmc_a16 0 0 CFG_GPMC_A16_OUT qspi1_d0
P3 gpmc_a17 2251 1217 CFG_GPMC_A17_IN qspi1_d1
R2 gpmc_a18 0 0 CFG_GPMC_A18_OUT qspi1_sclk
P2 gpmc_cs2 0 0 CFG_GPMC_CS2_OUT qspi1_cs0
P1 gpmc_cs3 0 0 CFG_GPMC_CS3_OUT qspi1_cs1

Multichannel Audio Serial Port (McASP)

The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

The device have integrated 8 McASP modules (McASP1-McASP8) with:

  • McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
  • McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain
  • The McASP1 is instantiated in IPU power domain
  • McASP2 through McASP8 are part of the L4_PER2 peripheral power domain

NOTE

For more information, see the Serial Communication Interface section of the Device TRM.

CAUTION

The I/O Timings provided in this section are valid only for some McASP usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-46, Table 7-47, Table 7-48 and Figure 7-41 present Timing Requirements for McASP1 to McASP8.

Table 7-46 Timing Requirements for McASP1(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
1 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns
2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.35P (2) ns
3 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
4 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5R – 3 (3) ns
5 tsu(AFSRX-ACLK) Setup time, AFSR/X input valid before ACLKR/X ACLKR/X int 20.5 ns
ACLKR/X ext in
ACLKR/X ext out
4 ns
6 th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X ACLKR/X int –1 ns
ACLKR/X ext in
ACLKR/X ext out
1.7 ns
7 tsu(AXR-ACLK) Setup time, AXR input valid before ACLKR/X ACLKR/X int 21.6 ns
ACLKR/X ext in
ACLKR/X ext out
11.5 ns
8 th(ACLK-AXR) Hold time, AXR input valid after ACLKR/X ACLKR/X int –1 ns
ACLKR/X ext in
ACLKR/X ext out
2.34 ns
  1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
    ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
    ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
    ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
    ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
    ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
  2. P = AHCLKR/X period in ns.
  3. R = ACLKR/X period in ns.

Table 7-47 Timing Requirements for McASP2(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
1 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns
2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.35P (2) ns
3 tc(ACLKRX) Cycle time, ACLKR/X Any Other Conditions 20 ns
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M" Virtual IO Timing Modes
12.5 ns
4 tw(ACLKRX) Pulse duration, ACLKR/X high or low Any Other Conditions 0.5R – 3 (3) ns
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M" Virtual IO Timing Modes
0.38R (3) ns
5 tsu(AFSRX-ACLK) Setup time, AFSR/X input valid before ACLKR/X ACLKR/X int 20.3 ns
ACLKR/X ext in
ACLKR/X ext out
4.5 ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes
3 ns
6 th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X ACLKR/X int –1 ns
ACLKR/X ext in
ACLKR/X ext out
1.8 ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes
3 ns
7 tsu(AXR-ACLK) Setup time, AXR input valid before ACLKR/X ACLKR/X int 21.1 ns
ACLKR/X ext in
ACLKR/X ext out
4.5 ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes
3 ns
8 th(ACLK-AXR) Hold time, AXR input valid after ACLKR/X ACLKR/X int –1 ns
ACLKR/X ext in
ACLKR/X ext out
1.8 ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes
3 ns
  1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
    ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
    ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
    ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
    ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
    ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
  2. P = AHCLKR/X period in ns.
  3. R = ACLKR/X period in ns.

Table 7-48 Timing Requirements for McASP3/4/5/6/7/8(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
1 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns
2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.35P (2) ns
3 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
4 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5R – 3 (3) ns
5 tsu(AFSRX-ACLK) Setup time, AFSR/X input valid before ACLKR/X ACLKR/X int 19.7 ns
ACLKR/X ext in
ACLKR/X ext out
5.6 ns
6 th(ACLK-AFSRX) Hold time, AFSR/X input valid after ACLKR/X ACLKR/X int –1.1 ns
ACLKR/X ext in
ACLKR/X ext out
3.33 ns
tsu(AXR-ACLK) Setup time, AXR input valid before ACLKX ACLKX int (ASYNC=0) 20.3 ns
ACLKR/X ext in
ACLKR/X ext out
5.1 ns
8 th(ACLK-AXR) Hold time, AXR input valid after ACLKX ACLKX int (ASYNC=0) –0.8 ns
ACLKR/X ext in
ACLKR/X ext out
3.33 ns
  1. ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1 (NOT SUPPORTED)
    ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
    ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
    ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
    ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
    ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
  2. P = AHCLKR/X period in ns.
  3. R = ACLKR/X period in ns.
AM5718-HIREL SPRS906_TIMING_McASP_01.gif
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
Figure 7-41 McASP Input Timing

Table 7-49, Table 7-50, Table 7-51 and Figure 7-42 present Switching Characteristics Over Recommended Operating Conditions for McASP1 to McASP8.

Table 7-49 Switching Characteristics Over Recommended Operating Conditions for McASP1(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
9 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns
10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.5P - 2.5 (2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5P - 2.5 (3) ns
13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int -0.9 6 ns
ACLKR/X ext in
ACLKR/X ext out
2 23.1 ns
14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int -1.4 6 ns
ACLKR/X ext in
ACLKR/X ext out
2 24.2 ns

Table 7-50 Switching Characteristics Over Recommended Operating Conditions for McASP2 (1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
9 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns
10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.5P - 2.5 (2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5P - 2.5 (3) ns
13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int -1 6 ns
ACLKR/X ext in
ACLKR/X ext out
2 23.2 ns
14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int -1.3 6 ns
ACLKR/X ext in
ACLKR/X ext out
2 23.7 ns

Table 7-51 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8(1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
9 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns
10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.5P - 2.5 (2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5P - 2.5 (3) ns
13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int -0.5 6 ns
ACLKR/X ext in
ACLKR/X ext out
1.9 24.5 ns
14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int -1.4 7.1 ns
ACLKR/X ext in
ACLKR/X ext out
1.1 24.2 ns
AM5718-HIREL SPRS906_TIMING_McASP_02.gif
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
Figure 7-42 McASP Output TimingAB

Table 7-52 through Table 7-59 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see Figure 7-43 through Figure 7-50).

Table 7-52 Virtual Mode Case Details for McASP1

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL2_ASYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL2_ASYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL2_ASYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL2_ASYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP1_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 7-53 Virtual Mode Case Details for McASP2

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode)(1) See Figure 7-43
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)(1)
AXR(Inputs)/CLKR/FSR MCASP2_VIRTUAL4_ASYNC_RX_80M (2)
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP2_VIRTUAL2_ASYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL2_ASYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL2_ASYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX(1) See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL3_SYNC_RX(1)
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL1_SYNC_RX_80M(2)
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
  1. Used up to 50MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are bidirectional).
  2. Used in 80MHz input only mode when AXR, CLKX and FSX are all inputs.

Table 7-54 Virtual Mode Case Details for McASP3

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 7-55 Virtual Mode Case Details for McASP4

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 7-56 Virtual Mode Case Details for McASP5

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 7-57 Virtual Mode Case Details for McASP6

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 7-58 Virtual Mode Case Details for McASP7

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 7-59 Virtual Mode Case Details for McASP8

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-43
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-44
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 7-45
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 7-46
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-47
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 7-48
AXR(Inputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 7-49
AXR(Inputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 7-50
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
AM5718-HIREL SPRS906_MCASP_uc_01.gif Figure 7-43 McASP1-8 COIFOI - ASYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_02.gif Figure 7-44 McASP1-8 COIFIO - ASYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_03.gif Figure 7-45 McASP1-8 CIOFIO - ASYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_04.gif Figure 7-46 McASP1-8 CIOFOI - ASYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_05.gif Figure 7-47 McASP1-8 CO-FO- - SYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_06.gif Figure 7-48 McASP1-8 CI-FO- - SYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_07.gif Figure 7-49 McASP1-8 CI-FI- - SYNC Mode
AM5718-HIREL SPRS906_MCASP_uc_08.gif Figure 7-50 McASP1-8 CO-FI- - SYNC Mode

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

CAUTION

The I/O Timings provided in this section are valid only for some McASP usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP1. See Table 7-2, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-60, Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.

Table 7-60 presents the values for DELAYMODE bitfield.

Table 7-60 Virtual Functions Mapping for McASP1

BALL BALL NAME Delay Mode Value MUXMODE
MCASP1_VIRTUAL1_SYNC_RX MCASP1_VIRTUAL2_ASYNC_RX 0 1 2 3
C14 mcasp1_aclkx 15 14 mcasp1_aclkx
E21 gpio6_14 14 13 mcasp1_axr8
A13 mcasp1_axr13 15 14 mcasp1_axr13
E12 mcasp1_axr4 14 13 mcasp1_axr4
B26 xref_clk2 14 13 mcasp1_axr6
A11 mcasp1_axr9 15 14 mcasp1_axr9
D12 mcasp1_axr7 14 13 mcasp1_axr7
E14 mcasp1_axr12 15 14 mcasp1_axr12
F21 gpio6_16 14 13 mcasp1_axr10
F20 gpio6_15 14 13 mcasp1_axr9
C23 xref_clk3 14 13 mcasp1_axr7
C12 mcasp1_axr6 14 13 mcasp1_axr6
B13 mcasp1_axr10 15 14 mcasp1_axr10
J14 mcasp1_fsr N/A 14 mcasp1_fsr
B12 mcasp1_axr8 15 14 mcasp1_axr8
A12 mcasp1_axr11 15 14 mcasp1_axr11
G13 mcasp1_axr2 14 13 mcasp1_axr2
D14 mcasp1_fsx 15 14 mcasp1_fsx
G14 mcasp1_axr14 15 14 mcasp1_axr14
F14 mcasp1_axr15 15 14 mcasp1_axr15
F12 mcasp1_axr1 15 14 mcasp1_axr1
B14 mcasp1_aclkr N/A 14 mcasp1_aclkr
F13 mcasp1_axr5 14 13 mcasp1_axr5
E17 xref_clk1 15 14 mcasp1_axr5
G12 mcasp1_axr0 15 14 mcasp1_axr0
J11 mcasp1_axr3 14 13 mcasp1_axr3
D18 xref_clk0 15 14 mcasp1_axr4 mcasp1_ahclkx

Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP2. See Table 7-2, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-61, Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.

Table 7-61 presents the values for DELAYMODE bitfield.

Table 7-61 Virtual Functions Mapping for McASP2

BALL BALL NAME Delay Mode Value MUXMODE
MCASP2_VIRTUAL1
_SYNC_RX_80M
MCASP2_VIRTUAL2
_ASYNC_RX
MCASP2_VIRTUAL3
_SYNC_RX
MCASP2_VIRTUAL4
_ASYNC_RX_80M
0 1 2 3
B19 mcasp3_axr0 15 14 10 9 mcasp2_axr14
B17 mcasp2_axr6 14 13 12 11 mcasp2_axr6
B16 mcasp2_axr5 14 13 12 11 mcasp2_axr5
A18 mcasp2_fsx 15 14 10 9 mcasp2_fsx
B26 xref_clk2 12 11 10 9 mcasp2_axr10
A16 mcasp2_axr3 15 14 10 9 mcasp2_axr3
E15 mcasp2_aclkr N/A 14 N/A 13 mcasp2_aclkr
B18 mcasp3_aclkx 15 14 10 9 mcasp2_axr12
A19 mcasp2_aclkx 15 14 10 9 mcasp2_aclkx
A17 mcasp2_axr7 14 13 12 11 mcasp2_axr7
C23 xref_clk3 12 11 10 9 mcasp2_axr11
C17 mcasp3_axr1 15 14 10 8 mcasp2_axr15
F15 mcasp3_fsx 15 14 10 9 mcasp2_axr13
C15 mcasp2_axr2 15 14 10 9 mcasp2_axr2
D15 mcasp2_axr4 14 13 12 11 mcasp2_axr4
A20 mcasp2_fsr N/A 14 N/A 13 mcasp2_fsr
E17 xref_clk1 10 9 8 6 mcasp2_axr9 mcasp2_ahclkx
A15 mcasp2_axr1 14 13 12 11 mcasp2_axr1
B15 mcasp2_axr0 14 13 12 11 mcasp2_axr0
D18 xref_clk0 10 9 8 6 mcasp2_axr8

Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP3/4/5/6/7/8. See Table 7-2, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-62, Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the Virtual modes.

Table 7-62 presents the values for DELAYMODE bitfield.

Table 7-62 Virtual Functions Mapping for McASP3/4/5/6/7/8

BALL BALL NAME Delay Mode Value MUXMODE
0 1 2
MCASP3_VIRTUAL2_SYNC_RX
A16 mcasp2_axr3 8 mcasp3_axr3
B18 mcasp3_aclkx 8 mcasp3_aclkx mcasp3_aclkr
B19 mcasp3_axr0 8 mcasp3_axr0
C17 mcasp3_axr1 6 mcasp3_axr1
F15 mcasp3_fsx 8 mcasp3_fsx mcasp3_fsr
C15 mcasp2_axr2 8 mcasp3_axr2
MCASP4_VIRTUAL1_SYNC_RX
A21 mcasp4_fsx 14 mcasp4_fsx mcasp4_fsr
C18 mcasp4_aclkx 14 mcasp4_aclkx mcasp4_aclkr
G16 mcasp4_axr0 14 mcasp4_axr0
D17 mcasp4_axr1 14 mcasp4_axr1
F13 mcasp1_axr5 12 mcasp4_axr3
E12 mcasp1_axr4 12 mcasp4_axr2
MCASP5_VIRTUAL1_SYNC_RX
AA3 mcasp5_aclkx 14 mcasp5_aclkx mcasp5_aclkr
AB9 mcasp5_fsx 14 mcasp5_fsx mcasp5_fsr
AA4 mcasp5_axr1 14 mcasp5_axr1
C12 mcasp1_axr6 12 mcasp5_axr2
AB3 mcasp5_axr0 14 mcasp5_axr0
D12 mcasp1_axr7 12 mcasp5_axr3
MCASP6_VIRTUAL1_SYNC_RX
G13 mcasp1_axr2 12 mcasp6_axr2
J11 mcasp1_axr3 12 mcasp6_axr3
B13 mcasp1_axr10 10 mcasp6_aclkx mcasp6_aclkr
A11 mcasp1_axr9 10 mcasp6_axr1
B12 mcasp1_axr8 10 mcasp6_axr0
A12 mcasp1_axr11 10 mcasp6_fsx mcasp6_fsr
MCASP7_VIRTUAL2_SYNC_RX
E14 mcasp1_axr12 10 mcasp7_axr0
F14 mcasp1_axr15 10 mcasp7_fsx mcasp7_fsr
G14 mcasp1_axr14 10 mcasp7_aclkx mcasp7_aclkr
A13 mcasp1_axr13 10 mcasp7_axr1
B14 mcasp1_aclkr 13 mcasp7_axr2
J14 mcasp1_fsr 13 mcasp7_axr3
MCASP8_VIRTUAL1_SYNC_RX
D15 mcasp2_axr4 10 mcasp8_axr0
A17 mcasp2_axr7 10 mcasp8_fsx mcasp8_fsr
B17 mcasp2_axr6 10 mcasp8_aclkx mcasp8_aclkr
A20 mcasp2_fsr 12 mcasp8_axr3
B16 mcasp2_axr5 10 mcasp8_axr1
E15 mcasp2_aclkr 12 mcasp8_axr2

Universal Serial Bus (USB)

SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:

  • USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0) PHY and HS/FS (USB2.0) PHY.
  • USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.

NOTE

For more information, see the SuperSpeed USB DRD section of the Device TRM.

USB1 DRD PHY

The USB1 DRD interface supports the following applications:

  • USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum data rate of 480 Mbps.
  • USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate of 5Gbps.

USB2 PHY

The USB2 interface supports the following applications:

  • USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum data rate of 480 Mbps.

Serial Advanced Technology Attachment (SATA)

The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate:

  • Gen2i, Gen2m, Gen2x: 3Gbps.
  • Gen1i, Gen1m, Gen1x: 1.5Gbps.

NOTE

For more information, see the SATA Controller section of the Device TRM.

Peripheral Component Interconnect Express (PCIe)

The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane) (Single Lane and Flexible dual lane configuration).

The device PCIe supports the following features:

  • 16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
  • Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
  • Single virtual channel (VC0), single traffic class (TC0)
  • Single function in end-point mode
  • Automatic width and speed negotiation
  • Max payload: 128 byte outbound, 256 byte inbound
  • Automatic credit management
  • ECRC generation and checking
  • Configurable BAR filtering
  • Legacy interrupt reception (RC) and generation (EP)
  • MSI generation and reception
  • PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
  • All PCI Device Power Management D-states with the exception of D3cold / L2 state

The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and the PCI Local Bus Specification, revision 3.0.

NOTE

For more information, see the PCIe Controller section of the Device TRM.

Controller Area Network Interface (DCAN)

The device provides two DCAN interfaces for supporting distributed realtime control with a high level of security. The DCAN interfaces implement the following features:

  • Supports CAN protocol version 2.0 part A, B
  • Bit rates up to 1 MBit/s
  • 64 message objects
  • Individual identifier mask for each message object
  • Programmable FIFO mode for message objects
  • Programmable loop-back modes for self-test operation
  • Suspend mode for debug support
  • Software module reset
  • Automatic bus on after Bus-Off state by a programmable 32-bit timer
  • Direct access to Message RAM during test mode
  • CAN Rx/Tx pins are configurable as general-purpose IO pins
  • Two interrupt lines (plus additional parity-error interrupts line)
  • RAM initialization
  • DMA support

NOTE

For more information, see the DCAN section of the Device TRM.

NOTE

The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.

Table 7-63, Table 7-64 and Figure 7-51 present timing and switching characteristics for DCANx Interface.

Table 7-63 Timing Requirements for DCANx Receive(1)

NO. PARAMETER DESCRIPTION MIN NOM MAX UNIT
f(baud) Maximum programmable baud rate 1 Mbps
1 tw(DCANRX) Pulse duration, receive data bit (DCANx_RX) H - 15 H + 15 ns
  1. H = period of baud rate, 1/programmed baud rate.

Table 7-64 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit (1)

NO. PARAMETER DESCRIPTION MIN MAX UNIT
f(baud) Maximum programmable baud rate 1 Mbps
2 tw(DCANTX) Pulse duration, transmit data bit (DCANx_TX) H - 15 H + 15 ns
  1. H = period of baud rate, 1/programmed baud rate.
AM5718-HIREL SPRS906_TIMING_DCAN_01.gif Figure 7-51 DCANx Timings

Ethernet Interface (GMAC_SW)

The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII) in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY) management.

NOTE

For more information, see the Ethernet Subsystem section of the Device TRM.

NOTE

The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as MIIn, RMIIn and RGMIIn.

CAUTION

The I/O timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 7-69, Table 7-72, Table 7-77 and Table 7-84.

CAUTION

The I/O Timings provided in this section are valid only for some GMAC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-65 and Figure 7-52 present timing requirements for MIIn in receive operation.

GMAC MII Timings

Table 7-65 Timing Requirements for miin_rxclk - MII Operation

NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
1 tc(RX_CLK) Cycle time, miin_rxclk 10 Mbps 400 ns
100 Mbps 40 ns
2 tw(RX_CLKH) Pulse duration, miin_rxclk high 10 Mbps 140 260 ns
100 Mbps 14 26 ns
3 tw(RX_CLKL) Pulse duration, miin_rxclk low 10 Mbps 140 260 ns
100 Mbps 14 26 ns
4 tt(RX_CLK) Transition time, miin_rxclk 10 Mbps 3 ns
100 Mbps 3 ns
AM5718-HIREL SPRS906_TIMING_GMAC_MIIRXCLK_01.gif Figure 7-52 Clock Timing (GMAC Receive) - MIIn operation

Table 7-66 and Figure 7-53 present timing requirements for MIIn in transmit operation.

Table 7-66 Timing Requirements for miin_txclk - MII Operation

NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
1 tc(TX_CLK) Cycle time, miin_txclk 10 Mbps 400 ns
100 Mbps 40 ns
2 tw(TX_CLKH) Pulse duration, miin_txclk high 10 Mbps 140 260 ns
100 Mbps 14 26 ns
3 tw(TX_CLKL) Pulse duration, miin_txclk low 10 Mbps 140 260 ns
100 Mbps 14 26 ns
4 tt(TX_CLK) Transition time, miin_txclk 10 Mbps 3 ns
100 Mbps 3 ns
AM5718-HIREL SPRS906_TIMING_GMAC_MIITXCLK_02.gif Figure 7-53 Clock Timing (GMAC Transmit) - MIIn operation

Table 7-67 and Figure 7-54 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.

Table 7-67 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s

NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 tsu(RXD-RX_CLK) Setup time, receive selected signals valid before miin_rxclk 8 ns
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
2 th(RX_CLK-RXD) Hold time, receive selected signals valid after miin_rxclk 8 ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
AM5718-HIREL SPRS906_TIMING_GMAC_MIIRCV_03.gif Figure 7-54 GMAC Receive Interface Timing MIIn operation

Table 7-68 and Figure 7-55 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.

Table 7-68 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s

NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 td(TX_CLK-TXD) Delay time, miin_txclk to transmit selected signals valid 0 25 ns
td(TX_CLK-TX_EN)
AM5718-HIREL SPRS906_TIMING_GMAC_MIITX_04.gif Figure 7-55 GMAC Transmit Interface Timing MIIn operation

In Table 7-69 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.

Table 7-69 GMAC MII IOSETs

SIGNALS IOSET5 IOSET6
BALL MUX BALL MUX
GMAC MII1
mii1_txd3 C5 8
mii1_txd2 D6 8
mii1_txd1 B2 8
mii1_txd0 C4 8
mii1_rxd3 F5 8
mii1_rxd2 E4 8
mii1_rxd1 C1 8
mii1_rxd0 E6 8
mii1_col B4 8
mii1_rxer B3 8
mii1_txer A3 8
mii1_txen A4 8
mii1_crs B5 8
mii1_rxclk D5 8
mii1_txclk C3 8
mii1_rxdv C2 8
GMAC MII0
mii0_txd3 V5 3
mii0_txd2 V4 3
mii0_txd1 Y2 3
mii0_txd0 W2 3
mii0_rxd3 W9 3
mii0_rxd2 V9 3
mii0_rxd1 V6 3
mii0_rxd0 U6 3
mii0_txclk U5 3
mii0_txer U4 3
mii0_rxer U7 3
mii0_rxdv V2 3
mii0_crs V7 3
mii0_col V1 3
mii0_rxclk Y1 3
mii0_txen V3 3

GMAC MDIO Interface Timings

CAUTION

The I/O Timings provided in this section are valid only for some GMAC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-70, Table 7-70 and Figure 7-56 present timing requirements for MDIO.

Table 7-70 Timing Requirements for MDIO Input

NO. PARAMETER DESCRIPTION MIN MAX UNIT
MDIO1 tc(MDC) Cycle time, MDC 400 ns
MDIO2 tw(MDCH) Pulse Duration, MDC High 160 ns
MDIO3 tw(MDCL) Pulse Duration, MDC Low 160 ns
MDIO4 tsu(MDIO-MDC) Setup time, MDIO valid before MDC High 90 ns
MDIO5 th(MDIO_MDC) Hold time, MDIO valid from MDC High 0 ns

Table 7-71 Switching Characteristics Over Recommended Operating Conditions for MDIO Output

NO. PARAMETER DESCRIPTION MIN MAX UNIT
MDIO6 tt(MDC) Transition time, MDC 5 ns
MDIO7 td(MDC-MDIO) Delay time, MDC High to MDIO valid 10 390 ns
AM5718-HIREL SPRS906_TIMING_GMAC_MDIO_05.gif Figure 7-56 GMAC MDIO diagrams

In Table 7-72 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.

Table 7-72 GMAC MDIO IOSETs

SIGNALS IOSET7 IOSET8 IOSET9 IOSET10
BALL MUX BALL MUX BALL MUX BALL MUX
mdio_d F6 3 U4 0 AB4 1 B20 5
mdio_mclk D3 3 V1 0 AC5 1 B21 5

GMAC RMII Timings

The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the PRCM chapter of the device TRM for full details about RMII reference clock.

CAUTION

The I/O Timings provided in this section are valid only for some GMAC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-73, Table 7-74 and Figure 7-57 present timing requirements for GMAC RMIIn Receive.

Table 7-73 Timing Requirements for GMAC REF_CLK - RMII Operation

NO. PARAMETER DESCRIPTION MIN MAX UNIT
RMII1 tc(REF_CLK) Cycle time, REF_CLK 20 ns
RMII2 tw(REF_CLKH) Pulse duration, REF_CLK high 7 13 ns
RMII3 tw(REF_CLKL) Pulse duration, REF_CLK low 7 13 ns
RMII4 ttt(REF_CLK) Transistion time, REF_CLK 3 ns

Table 7-74 Timing Requirements for GMAC RMIIn Receive

NO. PARAMETER DESCRIPTION MIN MAX UNIT
RMII5 tsu(RXD-REF_CLK) Setup time, receive selected signals valid before REF_CLK 4 ns
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
RMII6 th(REF_CLK-RXD) Hold time, receive selected signals valid after REF_CLK 2 ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
AM5718-HIREL SPRS906_TIMING_GMAC_RMIIRX_06.gif Figure 7-57 GMAC Receive Interface Timing RMIIn operation

Table 7-75, Table 7-75 and Figure 7-58 present switching characteristics for GMAC RMIIn Transmit 10/100Mbit/s.

Table 7-75 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation

NO. PARAMETER DESCRIPTION MIN MAX UNIT
RMII7 tc(REF_CLK) Cycle time, REF_CLK 20 ns
RMII8 tw(REF_CLKH) Pulse duration, REF_CLK high 7 13 ns
RMII9 tw(REF_CLKL) Pulse duration, REF_CLK low 7 13 ns
RMII10 tt(REF_CLK) Transistion time, REF_CLK 3 ns

Table 7-76 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s

NO. PARAMETER DESCRIPTION RMIIn MIN MAX UNIT
RMII11 td(REF_CLK-TXD) Delay time, REF_CLK high to selected transmit signals valid RMII0 2 13.5 ns
tdd(REF_CLK-TXEN)
td(REF_CLK-TXD) RMII1 2 13.8 ns
tdd(REF_CLK-TXEN)
AM5718-HIREL SPRS906_TIMING_GMAC_RMIITX_07.gif Figure 7-58 GMAC Transmit Interface Timing RMIIn Operation

In Table 7-77 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.

Table 7-77 GMAC RMII IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
GMAC RMII1
RMII_MHZ_50_CLK U3 0
rmii1_txd1 V5 2
rmii1_txd0 V4 2
rmii1_rxd1 W9 2
rmii1_rxd0 V9 2
rmii1_rxer Y1 2
rmii1_txen U5 2
rmii1_crs V2 2
GMAC RMII0
RMII_MHZ_50_CLK U3 0
rmii0_txd1 Y2 1
rmii0_txd0 W2 1
rmii0_rxd1 V6 1
rmii0_rxd0 U6 1
rmii0_txen V3 1
rmii0_rxer U7 1
rmii0_crs V7 1

Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-78 Manual Functions Mapping for GMAC RMII0 for a definition of the Manual modes.

Table 7-78 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-78 Manual Functions Mapping for GMAC RMII0

BALL BALL NAME GMAC_RMII0_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 0 1
U3 RMII_MHZ_50_CLK 0 0 CFG_RMII_MHZ_50_CLK_IN RMII_MHZ_50_CLK
U6 rgmii0_txd0 2444 804 CFG_RGMII0_TXD0_IN rmii0_rxd0
V6 rgmii0_txd1 2453 981 CFG_RGMII0_TXD1_IN rmii0_rxd1
U7 rgmii0_txd2 2356 847 CFG_RGMII0_TXD2_IN rmii0_rxer
V7 rgmii0_txd3 2415 993 CFG_RGMII0_TXD3_IN rmii0_crs

Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-79 Manual Functions Mapping for GMAC RMII1 for a definition of the Manual modes.

Table 7-79 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-79 Manual Functions Mapping for GMAC RMII1

BALL BALL NAME GMAC_RMII1_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 0 2
U3 RMII_MHZ_50_CLK 0 0 CFG_RMII_MHZ_50_CLK_IN RMII_MHZ_50_CLK
V9 rgmii0_txctl 2450 909 CFG_RGMII0_TXCTL_IN rmii1_rxd0
W9 rgmii0_txc 2327 926 CFG_RGMII0_TXC_IN rmii1_rxd1
Y1 uart3_txd 2553 443 CFG_UART3_TXD_IN rmii1_rxer
V2 uart3_rxd 1943 1110 CFG_UART3_RXD_IN rmii1_crs

GMAC RGMII Timings

CAUTION

The I/O Timings provided in this section are valid only for some GMAC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 7-80, Table 7-81 and Figure 7-59 present timing requirements for receive RGMIIn operation.

Table 7-80 Timing Requirements for rgmiin_rxc - RGMIIn Operation

NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
1 tc(RXC) Cycle time, rgmiin_rxc 10 Mbps 360 440 ns
100 Mbps 36 44 ns
1000 Mbps 7.2 8.8 ns
2 tw(RXCH) Pulse duration, rgmiin_rxc high 10 Mbps 160 240 ns
100 Mbps 16 24 ns
1000 Mbps 3.6 4.4 ns
3 tw(RXCL) Pulse duration, rgmiin_rxc low 10 Mbps 160 240 ns
100 Mbps 16 24 ns
1000 Mbps 3.6 4.4 ns
4 tt(RXC) Transition time, rgmiin_rxc 10 Mbps 0.75 ns
100 Mbps 0.75 ns
1000 Mbps 0.75 ns

Table 7-81 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps (1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
5 tsu(RXD-RXCH) Setup time, receive selected signals valid before rgmiin_rxc high/low RGMII0/1 1 ns
6 th(RXCH-RXD) Hold time, receive selected signals valid after rgmiin_rxc high/low RGMII0/1 1 ns
  1. For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
AM5718-HIREL SPRS906_TIMING_GMAC_RGMIIRX_08.gif
rgmiin_rxc must be externally delayed relative to the data and control pins.
Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
Figure 7-59 GMAC Receive Interface Timing, RGMIIn operation

Table 7-82, Table 7-83 and Figure 7-60 present switching characteristics for transmit - RGMIIn for 10/100/1000Mbit/s.

Table 7-82 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s

NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
1 tc(TXC) Cycle time, rgmiin_txc 10 Mbps 360 440 ns
100 Mbps 36 44 ns
1000 Mbps 7.2 8.8 ns
2 tw(TXCH) Pulse duration, rgmiin_txc high 10 Mbps 160 240 ns
100 Mbps 16 24 ns
1000 Mbps 3.6 4.4 ns
3 tw(TXCL) Pulse duration, rgmiin_txc low 10 Mbps 160 240 ns
100 Mbps 16 24 ns
1000 Mbps 3.6 4.4 ns
4 tt(TXC) Transition time, rgmiin_txc 10 Mbps 0.75 ns
100 Mbps 0.75 ns
1000 Mbps 0.75 ns

Table 7-83 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
5 tosu(TXD-TXC) Output Setup time, transmit selected signals valid to rgmiin_txc high/low RGMII0, Internal Delay Enabled, 1000 Mbps 1.05 (2) ns
RGMII0, Internal Delay Enabled, 10/100 Mbps 1.2 ns
RGMII1, Internal Delay Enabled, 1000 Mbps 1.05 (3) ns
RGMII1, Internal Delay Enabled, 10/100 Mbps 1.2 ns
6 toh(TXC-TXD) Output Hold time, transmit selected signals valid after rgmiin_txc high/low RGMII0, Internal Delay Enabled, 1000 Mbps 1.05 (2) ns
RGMII0, Internal Delay Enabled, 10/100 Mbps 1.2 ns
RGMII1, Internal Delay Enabled, 1000 Mbps 1.05 (3) ns
RGMII1, Internal Delay Enabled, 10/100 Mbps 1.2 ns
  1. For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
  2. RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of rgmii0_txc.
  3. RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of rgmii1_txc.
AM5718-HIREL SPRS906_TIMING_GMAC_RGMIITX_09.gif
TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 7-60 GMAC Transmit Interface Timing RGMIIn operation

In Table 7-84 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.

Table 7-84 GMAC RGMII IOSETs

SIGNALS IOSET3 IOSET4
BALL MUX BALL MUX
GMAC RGMII1
rgmii1_txd3 C3 3
rgmii1_txd2 C4 3
rgmii1_txd1 B2 3
rgmii1_txd0 D6 3
rgmii1_rxd3 B3 3
rgmii1_rxd2 B4 3
rgmii1_rxd1 B5 3
rgmii1_rxd0 A4 3
rgmii1_rxctl A3 3
rgmii1_txc D5 3
rgmii1_txctl C2 3
rgmii1_rxc C5 3
GMAC RGMII0
rgmii0_txd3 V7 0
rgmii0_txd2 U7 0
rgmii0_txd1 V6 0
rgmii0_txd0 U6 0
rgmii0_rxd3 V4 0
rgmii0_rxd2 V3 0
rgmii0_rxd1 Y2 0
rgmii0_rxd0 W2 0
rgmii0_txc W9 0
rgmii0_rxctl V5 0
rgmii0_rxc U5 0
rgmii0_txctl V9 0

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-85 Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.

Table 7-85 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-85 Manual Functions Mapping for GMAC RGMII0

BALL BALL NAME GMAC_RGMII0_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 0
U5 rgmii0_rxc 413 0 CFG_RGMII0_RXC_IN rgmii0_rxc
V5 rgmii0_rxctl 27 2296 CFG_RGMII0_RXCTL_IN rgmii0_rxctl
W2 rgmii0_rxd0 3 1721 CFG_RGMII0_RXD0_IN rgmii0_rxd0
Y2 rgmii0_rxd1 134 1786 CFG_RGMII0_RXD1_IN rgmii0_rxd1
V3 rgmii0_rxd2 40 1966 CFG_RGMII0_RXD2_IN rgmii0_rxd2
V4 rgmii0_rxd3 0 2057 CFG_RGMII0_RXD3_IN rgmii0_rxd3
W9 rgmii0_txc 0 60 CFG_RGMII0_TXC_OUT rgmii0_txc
V9 rgmii0_txctl 0 60 CFG_RGMII0_TXCTL_OUT rgmii0_txctl
U6 rgmii0_txd0 0 60 CFG_RGMII0_TXD0_OUT rgmii0_txd0
V6 rgmii0_txd1 0 0 CFG_RGMII0_TXD1_OUT rgmii0_txd1
U7 rgmii0_txd2 0 60 CFG_RGMII0_TXD2_OUT rgmii0_txd2
V7 rgmii0_txd3 0 120 CFG_RGMII0_TXD3_OUT rgmii0_txd3

Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-86 Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.

Table 7-86 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-86 Manual Functions Mapping for GMAC RGMII1

BALL BALL NAME GMAC_RGMII1_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 3
C5 vin2a_d18 530 0 CFG_VIN2A_D18_IN rgmii1_rxc
A3 vin2a_d19 71 1099 CFG_VIN2A_D19_IN rgmii1_rxctl
B3 vin2a_d20 142 1337 CFG_VIN2A_D20_IN rgmii1_rxd3
B4 vin2a_d21 114 1517 CFG_VIN2A_D21_IN rgmii1_rxd2
B5 vin2a_d22 171 1331 CFG_VIN2A_D22_IN rgmii1_rxd1
A4 vin2a_d23 0 1328 CFG_VIN2A_D23_IN rgmii1_rxd0
D5 vin2a_d12 0 0 CFG_VIN2A_D12_OUT rgmii1_txc
C2 vin2a_d13 170 0 CFG_VIN2A_D13_OUT rgmii1_txctl
C3 vin2a_d14 150 0 CFG_VIN2A_D14_OUT rgmii1_txd3
C4 vin2a_d15 0 0 CFG_VIN2A_D15_OUT rgmii1_txd2
B2 vin2a_d16 60 0 CFG_VIN2A_D16_OUT rgmii1_txd1
D6 vin2a_d17 60 0 CFG_VIN2A_D17_OUT rgmii1_txd0

eMMC/SD/SDIO

The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)

NOTE

The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.

MMC1-SD Card Interface

MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card applications:

  • Default speed, 4-bit data, SDR, half-cycle
  • High speed, 4-bit data, SDR, half-cycle
  • SDR12, 4-bit data, half-cycle
  • SDR25, 4-bit data, half-cycle
  • UHS-I SDR50, 4-bit data, half-cycle
  • UHS-I SDR104, 4-bit data, half-cycle
  • UHS-I DDR50, 4-bit data

NOTE

For more information, see the eMMC/SD/SDIO chapter of the Device TRM.

Default speed, 4-bit data, SDR, half-cycle

Table 7-87 and Table 7-88 present Timing requirements and Switching characteristics for MMC1 - Default Speed in receiver and transmitter mode (see Figure 7-61 and Figure 7-62).

Table 7-87 Timing Requirements for MMC1 - SD Card Default Speed Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
DSSD5 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.11 ns
DSSD6 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 20.46 ns
DSSD7 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.11 ns
DSSD8 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 20.46 ns

Table 7-88 Switching Characteristics for MMC1 - SD Card Default Speed Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
DSSD0 fop(clk) Operating frequency, mmc1_clk 24 MHz
DSSD1 tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
DSSD2 tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185 (1) ns
DSSD3 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -14.93 14.93 ns
DSSD4 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -14.93 14.93 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_01.gif Figure 7-61 MMC/SD/SDIO in - Default Speed - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC1_02.gif Figure 7-62 MMC/SD/SDIO in - Default Speed - Transmitter Mode

High speed, 4-bit data, SDR, half-cycle

Table 7-89 and Table 7-90 present Timing requirements and Switching characteristics for MMC1 - High Speed in receiver and transmitter mode (see Figure 7-63 and Figure 7-64).

Table 7-89 Timing Requirements for MMC1 - SD Card High Speed

NO. PARAMETER DESCRIPTION MIN MAX UNIT
HSSD3 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.3 ns
HSSD4 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.6 ns
HSSD7 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.3 ns
HSSD8 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 2.6 ns

Table 7-90 Switching Characteristics for MMC1 - SD Card High Speed

NO. PARAMETER DESCRIPTION MIN MAX UNIT
HSSD1 fop(clk) Operating frequency, mmc1_clk 48 MHz
HSSD2H tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
HSSD2L tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185 (1) ns
HSSD5 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -7.6 3.6 ns
HSSD6 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -7.6 3.6 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_03.gif Figure 7-63 MMC/SD/SDIO in - High Speed - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC1_04.gif Figure 7-64 MMC/SD/SDIO in - High Speed - Transmitter Mode

SDR12, 4-bit data, half-cycle

Table 7-91 and Table 7-92 present Timing requirements and Switching characteristics for MMC1 - SDR12 in receiver and transmitter mode (see Figure 7-65 and Figure 7-66).

Table 7-91 Timing Requirements for MMC1 - SD Card SDR12 Mode

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SDR125 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 25.99 ns
SDR126 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Pad Loopback Clock 1.6 ns
Internal Loopback Clock 1.6 ns
SDR127 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 25.99 ns
SDR128 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge Pad Loopback Clock 1.6 ns
Internal Loopback Clock 1.6 ns

Table 7-92 Switching Characteristics for MMC1 - SD Card SDR12 Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR120 fop(clk) Operating frequency, mmc1_clk 24 MHz
SDR121 tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
SDR122 tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185(1) ns
SDR123 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -19.13 16.93 ns
SDR124 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -19.13 16.93 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_05.gif Figure 7-65 MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC1_06.gif Figure 7-66 MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode

SDR25, 4-bit data, half-cycle

Table 7-93 and Table 7-94 present Timing requirements and Switching characteristics for MMC1 - SDR25 in receiver and transmitter mode (see Figure 7-67 and Figure 7-68).

Table 7-93 Timing Requirements for MMC1 - SD Card SDR25 Mode

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SDR253 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.3 ns
SDR254 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1.6 ns
SDR257 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.3 ns
SDR258 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge Pad Loopback Clock 1.6 ns
Internal Loopback Clock 1.6 ns

Table 7-94 Switching Characteristics for MMC1 - SD Card SDR25 Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR251 fop(clk) Operating frequency, mmc1_clk 48 MHz
SDR252H tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
SDR252L tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185 (1) ns
SDR255 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -8.8 6.6 ns
SDR256 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -8.8 6.6 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_07.gif Figure 7-67 MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC1_08.gif Figure 7-68 MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode

UHS-I SDR50, 4-bit data, half-cycle

Table 7-95 and Table 7-96 present Timing requirements and Switching characteristics for MMC1 - SDR50 in receiver and transmitter mode (see Figure 7-69 and Figure 7-70).

Table 7-95 Timing Requirements for MMC1 - SD Card SDR50 Mode

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SDR503 tsu(cmdV-clkH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 1.48 ns
SDR504 th(clkH-cmdV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1.7 ns
SDR507 tsu(dV-clkH) Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 1.48 ns
SDR508 th(clkH-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge Pad Loopback Clock 1.7 ns
Internal Loopback Clock 1.6 ns

Table 7-96 Switching Characteristics for MMC1 - SD Card SDR50 Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR501 fop(clk) Operating frequency, mmc1_clk 96 MHz
SDR502H tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
SDR502L tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185 (1) ns
SDR505 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -8.8 6.6 ns
SDR506 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -3.66 1.46 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_09.gif Figure 7-69 MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC1_10.gif Figure 7-70 MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode

UHS-I SDR104, 4-bit data, half-cycle

Table 7-97 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and transmitter mode (see Figure 7-71 and Figure 7-72).

Table 7-97 Switching Characteristics for MMC1 - SD Card SDR104 Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR1041 fop(clk) Operating frequency, mmc1_clk 192 MHz
SDR1042H tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
SDR1042L tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185 (1) ns
SDR1045 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -1.09 0.49 ns
SDR1046 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -1.09 0.49 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_11.gif Figure 7-71 MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC1_12.gif Figure 7-72 MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode

UHS-I DDR50, 4-bit data

Table 7-98 and Table 7-99 present Timing requirements and Switching characteristics for MMC1 - DDR50 in receiver and transmitter mode (see Figure 7-73 and Figure 7-74).

Table 7-98 Timing Requirements for MMC1 - SD Card DDR50 Mode

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
DDR505 tsu(cmdV-clk) Setup time, mmc1_cmd valid before mmc1_clk transition 1.79 ns
DDR506 th(clk-cmdV) Hold time, mmc1_cmd valid after mmc1_clk transition 2 ns
DDR507 tsu(dV-clk) Setup time, mmc1_dat[3:0] valid before mmc1_clk transition Pad Loopback 1.79 ns
Internal Loopback 1.79 ns
DDR508 th(clk-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk transition Pad Loopback 2 ns
Internal Loopback 1.6 ns

Table 7-99 Switching Characteristics for MMC1 - SD Card DDR50 Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
DDR500 fop(clk) Operating frequency, mmc1_clk 48 MHz
DDR501 tw(clkH) Pulse duration, mmc1_clk high 0.5*P-0.185 (1) ns
DDR502 tw(clkL) Pulse duration, mmc1_clk low 0.5*P-0.185 (1) ns
DDR503 td(clk-cmdV) Delay time, mmc1_clk transition to mmc1_cmd transition 1.225 6.6 ns
DDR504 td(clk-dV) Delay time, mmc1_clk transition to mmc1_dat[3:0] transition 1.225 6.6 ns
  1. P = output mmc1_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC1_13.gif Figure 7-73 SDMMC - High Speed SD - DDR - Data/Command Receive
AM5718-HIREL SPRS906_TIMING_MMC1_14.gif Figure 7-74 SDMMC - High Speed SD - DDR - Data/Command Transmit

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-100 Virtual Functions Mapping for MMC1 for a definition of the Virtual modes.

Table 7-100 presents the values for DELAYMODE bitfield.

Table 7-100 Virtual Functions Mapping for MMC1

BALL BALL NAME Delay Mode Value MUXMODE
MMC1_
VIRTUAL1
MMC1_
VIRTUAL4
MMC1_
VIRTUAL5
MMC1_
VIRTUAL6
0
W6 mmc1_clk 15 12 11 10 mmc1_clk
Y6 mmc1_cmd 15 12 11 10 mmc1_cmd
AA6 mmc1_dat0 15 12 11 10 mmc1_dat0
Y4 mmc1_dat1 15 12 11 10 mmc1_dat1
AA5 mmc1_dat2 15 12 11 10 mmc1_dat2
Y3 mmc1_dat3 15 12 11 10 mmc1_dat3

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module chapter in the Device TRM.

Manual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-101 Manual Functions Mapping for MMC1 for a definition of the Manual modes.

Table 7-101 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-101 Manual Functions Mapping for MMC1

BALL BALL NAME MMC1_MANUAL1 MMC1_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0
W6 mmc1_clk 588 0 - - CFG_MMC1_CLK_IN mmc1_clk
Y6 mmc1_cmd 1000 0 - - CFG_MMC1_CMD_IN mmc1_cmd
AA6 mmc1_dat0 1375 0 - - CFG_MMC1_DAT0_IN mmc1_dat0
Y4 mmc1_dat1 1000 0 - - CFG_MMC1_DAT1_IN mmc1_dat1
AA5 mmc1_dat2 1000 0 - - CFG_MMC1_DAT2_IN mmc1_dat2
Y3 mmc1_dat3 1000 0 - - CFG_MMC1_DAT3_IN mmc1_dat3
W6 mmc1_clk 1230 0 520 320 CFG_MMC1_CLK_OUT mmc1_clk
Y6 mmc1_cmd 0 0 0 0 CFG_MMC1_CMD_OUT mmc1_cmd
AA6 mmc1_dat0 56 0 40 0 CFG_MMC1_DAT0_OUT mmc1_dat0
Y4 mmc1_dat1 76 0 83 0 CFG_MMC1_DAT1_OUT mmc1_dat1
AA5 mmc1_dat2 91 0 98 0 CFG_MMC1_DAT2_OUT mmc1_dat2
Y3 mmc1_dat3 99 0 106 0 CFG_MMC1_DAT3_OUT mmc1_dat3
Y6 mmc1_cmd 0 0 51 0 CFG_MMC1_CMD_OEN mmc1_cmd
AA6 mmc1_dat0 0 0 0 0 CFG_MMC1_DAT0_OEN mmc1_dat0
Y4 mmc1_dat1 0 0 363 0 CFG_MMC1_DAT1_OEN mmc1_dat1
AA5 mmc1_dat2 0 0 199 0 CFG_MMC1_DAT2_OEN mmc1_dat2
Y3 mmc1_dat3 0 0 273 0 CFG_MMC1_DAT3_OEN mmc1_dat3

MMC2 - eMMC

MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:

  • Standard JC64 SDR, 8-bit data, half cycle
  • High-speed JC64 SDR, 8-bit data, half cycle
  • High-speed HS200 JEDS84, 8-bit data, half cycle
  • High-speed JC64 DDR, 8-bit data

NOTE

For more information, see the eMMC/SD/SDIO chapter of the Device TRM.

Standard JC64 SDR, 8-bit data, half cycle

Table 7-102 and Table 7-103 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter mode (see Figure 7-75 and Figure 7-76).

Table 7-102 Timing Requirements for MMC2 - JC64 Standard SDR Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
SSDR5 tsu(cmdV-clkH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 13.19 ns
SSDR6 th(clkH-cmdV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 8.4 ns
SSDR7 tsu(dV-clkH) Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 13.19 ns
SSDR8 th(clkH-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 8.4 ns

Table 7-103 Switching Characteristics for MMC2 - JC64 Standard SDR Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
SSDR1 fop(clk) Operating frequency, mmc2_clk 24 MHz
SSDR2H tw(clkH) Pulse duration, mmc2_clk high 0.5*P-0.172 (1) ns
SSDR2L tw(clkL) Pulse duration, mmc2_clk low 0.5*P-0.172 (1) ns
SSDR3 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -16.96 16.96 ns
SSDR4 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -16.96 16.96 ns
  1. P = output mmc2_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC2_01.gif Figure 7-75 MMC/SD/SDIO in - Standard JC64 - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC2_02.gif Figure 7-76 MMC/SD/SDIO in - Standard JC64 - Transmitter Mode

High-speed JC64 SDR, 8-bit data, half cycle

Table 7-104 and Table 7-105 present Timing requirements and Switching characteristics for MMC2 - High speed SDR in receiver and transmitter mode (see Figure 7-77 and Figure 7-78).

Table 7-104 Timing Requirements for MMC2 - JC64 High Speed SDR Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
JC643 tsu(cmdV-clkH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 ns
JC644 th(clkH-cmdV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.6 ns
JC647 tsu(dV-clkH) Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 5.6 ns
JC648 th(clkH-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 2.6 ns

Table 7-105 Switching Characteristics for MMC2 - JC64 High Speed SDR Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
JC641 fop(clk) Operating frequency, mmc2_clk 48 MHz
JC642H tw(clkH) Pulse duration, mmc2_clk high 0.5*P-0.172 (1) ns
JC642L tw(clkL) Pulse duration, mmc2_clk low 0.5*P-0.172 (1) ns
JC645 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -6.64 6.64 ns
JC646 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -6.64 6.64 ns
  1. P = output mmc2_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC2_03.gif Figure 7-77 MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
AM5718-HIREL SPRS906_TIMING_MMC2_04.gif Figure 7-78 MMC/SD/SDIO in - High Speed JC64 - Transmitter Mode

High-speed HS200 JEDS84, 8-bit data, half cycle

Table 7-106 presents Switching characteristics for MMC2 - HS200 in transmitter mode (see Figure 7-79).

Table 7-106 Switching Characteristics for MMC2 - JEDS84 HS200 Mode

NO. PARAMETER DESCRIPTION MIN MAX UNIT
HS2001 fop(clk) Operating frequency, mmc2_clk 192 MHz
HS2002H tw(clkH) Pulse duration, mmc2_clk high 0.5*P-0.172 (1) ns
HS2002L tw(clkL) Pulse duration, mmc2_clk low 0.5*P-0.172 (1) ns
HS2005 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -1.136 0.536 ns
HS2006 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -1.136 0.536 ns
  1. P = output mmc2_clk period in ns
AM5718-HIREL SPRS906_TIMING_MMC2_05.gif Figure 7-79 eMMC in - HS200 SDR - Transmitter Mode

High-speed JC64 DDR, 8-bit data

Table 7-107 and Table 7-108 present Timing requirements and Switching characteristics for MMC2 - High speed DDR in receiver and transmitter mode (see Figure 7-80 and Figure 7-81).

Table 7-107 Timing Requirements for MMC2 - JC64 High Speed DDR Mode

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
DDR3 tsu(cmdV-clk) Setup time, mmc2_cmd valid before mmc2_clk transition 1.8 ns
DDR4 th(clk-cmdV) Hold time, mmc2_cmd valid after mmc2_clk transition 1.6 ns
DDR7 tsu(dV-clk) Setup time, mmc2_dat[7:0] valid before mmc2_clk transition 1.8 ns
DDR8 th(clk-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk transition Pad Loopback (1.8V and 3.3V), Boot 1.6 ns
Internal Loopback (1.8V with MMC2_VIRTUAL2) 1.86 ns
Internal Loopback (3.3V with MMC2_VIRTUAL2) 1.95 ns
Internal Loopback (1.8V with MMC2_MANUAL2) ns
Internal Loopback (3.3V with MMC2_MANUAL2) 1.6 ns

    Table 7-108 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    DDR1 fop(clk) Operating frequency, mmc2_clk 48 MHz
    DDR2H tw(clkH) Pulse duration, mmc2_clk high 0.5*P-0.172 (1) ns
    DDR2L tw(clkL) Pulse duration, mmc2_clk low 0.5*P-0.172 (1) ns
    DDR5 td(clk-cmdV) Delay time, mmc2_clk transition to mmc2_cmd transition 2.9 7.14 ns
    DDR6 td(clk-dV) Delay time, mmc2_clk transition to mmc2_dat[7:0] transition 2.9 7.14 ns
    1. P = output mmc2_clk period in ns
    AM5718-HIREL SPRS906_TIMING_MMC2_07.gif Figure 7-80 MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
    AM5718-HIREL SPRS906_TIMING_MMC2_08.gif Figure 7-81 MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode

    NOTE

    To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

    The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

    Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-109 Virtual Functions Mapping for MMC2 for a definition of the Virtual modes.

    Table 7-109 presents the values for DELAYMODE bitfield.

    Table 7-109 Virtual Functions Mapping for MMC2

    BALL BALL NAME Delay Mode Value MUXMODE
    MMC2_VIRTUAL2 1
    H6 gpmc_cs1 13 mmc2_cmd
    K7 gpmc_a19 13 mmc2_dat4
    M7 gpmc_a20 13 mmc2_dat5
    J5 gpmc_a21 13 mmc2_dat6
    K6 gpmc_a22 13 mmc2_dat7
    J7 gpmc_a23 13 mmc2_clk
    J4 gpmc_a24 13 mmc2_dat0
    J6 gpmc_a25 13 mmc2_dat1
    H4 gpmc_a26 13 mmc2_dat2
    H5 gpmc_a27 13 mmc2_dat3

    NOTE

    To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.

    The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module chapter in the Device TRM.

    Manual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-110 Manual Functions Mapping for MMC2 for a definition of the Manual modes.

    Table 7-110 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-110 Manual Functions Mapping for MMC2

    BALL BALL NAME MMC2_MANUAL1 MMC2_MANUAL2 MMC2_MANUAL3 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 1
    K7 gpmc_a19 0 0 0 14 - - CFG_GPMC_A19_IN mmc2_dat4
    M7 gpmc_a20 119 0 127 0 - - CFG_GPMC_A20_IN mmc2_dat5
    J5 gpmc_a21 0 0 22 0 - - CFG_GPMC_A21_IN mmc2_dat6
    K6 gpmc_a22 18 0 72 0 - - CFG_GPMC_A22_IN mmc2_dat7
    J7 gpmc_a23 894 0 410 4000 - - CFG_GPMC_A23_IN mmc2_clk
    J4 gpmc_a24 30 0 82 0 - - CFG_GPMC_A24_IN mmc2_dat0
    J6 gpmc_a25 0 0 0 0 - - CFG_GPMC_A25_IN mmc2_dat1
    H4 gpmc_a26 23 0 77 0 - - CFG_GPMC_A26_IN mmc2_dat2
    H5 gpmc_a27 0 0 0 0 - - CFG_GPMC_A27_IN mmc2_dat3
    H6 gpmc_cs1 0 0 0 0 - - CFG_GPMC_CS1_IN mmc2_cmd
    K7 gpmc_a19 152 0 152 0 285 0 CFG_GPMC_A19_OUT mmc2_dat4
    M7 gpmc_a20 206 0 206 0 189 0 CFG_GPMC_A20_OUT mmc2_dat5
    J5 gpmc_a21 78 0 78 0 0 120 CFG_GPMC_A21_OUT mmc2_dat6
    K6 gpmc_a22 2 0 2 0 0 70 CFG_GPMC_A22_OUT mmc2_dat7
    J7 gpmc_a23 266 0 266 0 730 360 CFG_GPMC_A23_OUT mmc2_clk
    J4 gpmc_a24 0 0 0 0 0 0 CFG_GPMC_A24_OUT mmc2_dat0
    J6 gpmc_a25 0 0 0 0 0 0 CFG_GPMC_A25_OUT mmc2_dat1
    H4 gpmc_a26 43 0 43 0 70 0 CFG_GPMC_A26_OUT mmc2_dat2
    H5 gpmc_a27 0 0 0 0 0 0 CFG_GPMC_A27_OUT mmc2_dat3
    H6 gpmc_cs1 0 0 0 0 0 120 CFG_GPMC_CS1_OUT mmc2_cmd
    K7 gpmc_a19 0 0 0 0 0 0 CFG_GPMC_A19_OEN mmc2_dat4
    M7 gpmc_a20 0 0 0 0 231 0 CFG_GPMC_A20_OEN mmc2_dat5
    J5 gpmc_a21 0 0 0 0 39 0 CFG_GPMC_A21_OEN mmc2_dat6
    K6 gpmc_a22 0 0 0 0 91 0 CFG_GPMC_A22_OEN mmc2_dat7
    J4 gpmc_a24 0 0 0 0 176 0 CFG_GPMC_A24_OEN mmc2_dat0
    J6 gpmc_a25 0 0 0 0 0 0 CFG_GPMC_A25_OEN mmc2_dat1
    H4 gpmc_a26 0 0 0 0 101 0 CFG_GPMC_A26_OEN mmc2_dat2
    H5 gpmc_a27 0 0 0 0 0 0 CFG_GPMC_A27_OEN mmc2_dat3
    H6 gpmc_cs1 0 0 0 0 360 0 CFG_GPMC_CS1_OEN mmc2_cmd

    MMC3 and MMC4-SDIO/SD

    MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it supports the following applications:

    • MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
    • MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
    • MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half cycle
    • MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
    • MMC3 8-bit data, UHS-I SDR50

    NOTE

    The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.

    NOTE

    For more information, see the MMC/SDIO chapter of the Device TRM.

    MMC3 and MMC4, SD Default Speed

    Figure 7-82, Figure 7-83, and Table 7-111 through Table 7-114 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.

    Table 7-111 Timing Requirements for MMC3 - Default Speed Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    DS5 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.11 ns
    DS6 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 20.46 ns
    DS7 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.11 ns
    DS8 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 20.46 ns
    1. i in [i:0] = 7

    Table 7-112 Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    DS0 fop(clk) Operating frequency, mmc3_clk 24 MHz
    DS1 tw(clkH) Pulse duration, mmc3_clk high 0.5*P-0.270 (1) ns
    DS2 tw(clkL) Pulse duration, mmc3_clk low 0.5*P-0.270 (1) ns
    DS3 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -14.93 14.93 ns
    DS4 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -14.93 14.93 ns
    1. P = output mmc3_clk period in ns
    2. i in [i:0] = 7

    Table 7-113 Timing Requirements for MMC4 - Default Speed Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    DS5 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.11 ns
    DS6 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 20.46 ns
    DS7 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.11 ns
    DS8 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 20.46 ns
    1. i in [i:0] = 3

    Table 7-114 Switching Characteristics for MMC4 - Default Speed Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    DS0 fop(clk) Operating frequency, mmc4_clk 24 MHz
    DS1 tw(clkH) Pulse duration, mmc4_clk high 0.5*P-0.270 (1) ns
    DS2 tw(clkL) Pulse duration, mmc4_clk low 0.5*P-0.270 (1) ns
    DS3 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -14.93 14.93 ns
    DS4 td(clkL-dV) Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -14.93 14.93 ns
    1. P = output mmc4_clk period in ns
    2. i in [i:0] = 3
    AM5718-HIREL SPRS906_TIMING_MMC3_07.gif Figure 7-82 MMC/SD/SDIOj in - Default Speed - Receiver Mode
    AM5718-HIREL SPRS906_TIMING_MMC3_08.gif Figure 7-83 MMC/SD/SDIOj in - Default Speed - Transmitter Mode

    MMC3 and MMC4, SD High Speed

    Figure 7-84, Figure 7-85, and Table 7-115 through Table 7-118 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter mode.

    Table 7-115 Timing Requirements for MMC3 - SD/SDIO High Speed Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    HS3 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.3 ns
    HS4 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 2.6 ns
    HS7 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.3 ns
    HS8 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 2.6 ns
    1. i in [i:0] = 7

    Table 7-116 Switching Characteristics for MMC3 - SD/SDIO High Speed Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    HS1 fop(clk) Operating frequency, mmc3_clk 48 MHz
    HS2H tw(clkH) Pulse duration, mmc3_clk high 0.5*P-0.270 (1) ns
    HS2L tw(clkL) Pulse duration, mmc3_clk low 0.5*P-0.270 (1) ns
    HS5 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -7.6 3.6 ns
    HS6 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -7.6 3.6 ns
    1. P = output mmc3_clk period in ns
    2. i in [i:0] = 7

    Table 7-117 Timing Requirements for MMC4 - High Speed Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    HS3 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.3 ns
    HS4 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns
    HS7 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.3 ns
    HS8 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns
    1. i in [i:0] = 3

    Table 7-118 Switching Characteristics for MMC4 - High Speed Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    HS1 fop(clk) Operating frequency, mmc4_clk 48 MHz
    HS2H tw(clkH) Pulse duration, mmc4_clk high 0.5*P-0.270 (1) ns
    HS2L tw(clkL) Pulse duration, mmc4_clk low 0.5*P-0.270 (1) ns
    HS5 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns
    HS6 td(clkL-dV) Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns
    1. P = output mmc4_clk period in ns
    2. i in [i:0] = 3
    AM5718-HIREL SPRS906_TIMING_MMC3_09.gif Figure 7-84 MMC/SD/SDIOj in - High Speed Signaling - Receiver Mode
    AM5718-HIREL SPRS906_TIMING_MMC3_10.gif Figure 7-85 MMC/SD/SDIOj in - High Speed Signaling - Transmitter Mode

    MMC3 and MMC4, SD and SDIO SDR12 Mode

    Figure 7-86, Figure 7-87, and Table 7-119, through Table 7-122 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.

    Table 7-119 Timing Requirements for MMC3 - SDR12 Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR125 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 25.99 ns
    SDR126 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns
    SDR127 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 25.99 ns
    SDR128 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns
    1. i in [i:0] = 7

    Table 7-120 Switching Characteristics for MMC3 - SDR12 Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR120 fop(clk) Operating frequency, mmc3_clk 24 MHz
    SDR121 tw(clkH) Pulse duration, mmc3_clk high 0.5*P-0.270 (1) ns
    SDR122 tw(clkL) Pulse duration, mmc3_clk low 0.5*P-0.270 (1) ns
    SDR123 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -19.13 16.93 ns
    SDR124 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -19.13 16.93 ns
    1. P = output mmc3_clk period in ns
    2. i in [i:0] = 7

    Table 7-121 Timing Requirements for MMC4 - SDR12 Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR125 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 25.99 ns
    SDR126 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns
    SDR127 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 25.99 ns
    SDR128 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns
    1. j in [i:0] = 3

    Table 7-122 Switching Characteristics for MMC4 - SDR12 Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR120 fop(clk) Operating frequency, mmc4_clk 24 MHz
    SDR121 tw(clkH) Pulse duration, mmc4_clk high 0.5*P-0.270 (1) ns
    SDR122 tw(clkL) Pulse duration, mmc4_clk low 0.5*P-0.270 (1) ns
    SDR125 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -19.13 16.93 ns
    SDR126 td(clkL-dV) Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -19.13 16.93 ns
    1. P = output mmc4_clk period in ns
    2. j in [i:0] = 3
    AM5718-HIREL SPRS906_TIMING_MMC3_11.gif Figure 7-86 MMC/SD/SDIOj in - SDR12 - Receiver Mode
    AM5718-HIREL SPRS906_TIMING_MMC3_12.gif Figure 7-87 MMC/SD/SDIOj in - SDR12 - Transmitter Mode

    MMC3 and MMC4, SD SDR25 Mode

    Figure 7-88, Figure 7-89, and Table 7-123, through Table 7-126 present Timing requirements and Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.

    Table 7-123 Timing Requirements for MMC3 - SDR25 Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR253 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.3 ns
    SDR254 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns
    SDR257 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.3 ns
    SDR258 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns
    1. i in [i:0] = 7

    Table 7-124 Switching Characteristics for MMC3 - SDR25 Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR251 fop(clk) Operating frequency, mmc3_clk 48 MHz
    SDR252H tw(clkH) Pulse duration, mmc3_clk high 0.5*P-0.270 (1) ns
    SDR252L tw(clkL) Pulse duration, mmc3_clk low 0.5*P-0.270 (1) ns
    SDR255 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -8.8 6.6 ns
    SDR256 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -8.8 6.6 ns
    1. P = output mmc3_clk period in ns
    2. i in [i:0] = 7

    Table 7-125 Timing Requirements for MMC4 - SDR25 Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR255 tsu(cmdV-clkH) Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.3 ns
    SDR256 th(clkH-cmdV) Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns
    SDR257 tsu(dV-clkH) Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.3 ns
    SDR258 th(clkH-dV) Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns
    1. i in [i:0] = 3

    Table 7-126 Switching Characteristics for MMC4 - SDR25 Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR251 fop(clk) Operating frequency, mmc4_clk 48 MHz
    SDR252H tw(clkH) Pulse duration, mmc4_clk high 0.5*P-0.270 (1) ns
    SDR252L tw(clkL) Pulse duration, mmc4_clk low 0.5*P-0.270 (1) ns
    SDR255 td(clkL-cmdV) Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns
    SDR256 td(clkL-dV) Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns
    1. P = output mmc4_clk period in ns
    2. i in [i:0] = 3
    AM5718-HIREL SPRS906_TIMING_MMC3_13.gif Figure 7-88 MMC/SD/SDIOj in - SDR25 - Receiver Mode
    AM5718-HIREL SPRS906_TIMING_MMC3_14.gif Figure 7-89 MMC/SD/SDIOj in - SDR25 - Transmitter Mode

    MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle

    Figure 7-90, Figure 7-91, Table 7-127, and Table 7-128 present Timing requirements and Switching characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.

    Table 7-127 Timing Requirements for MMC3 - SDR50 Mode (1)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR503 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 1.48 ns
    SDR504 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns
    SDR507 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 1.48 ns
    SDR508 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns
    1. i in [i:0] = 7

    Table 7-128 Switching Characteristics for MMC3 - SDR50 Mode (2)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    SDR501 fop(clk) Operating frequency, mmc3_clk 64 MHz
    SDR502H tw(clkH) Pulse duration, mmc3_clk high 0.5*P-0.270 (1) ns
    SDR502L tw(clkL) Pulse duration, mmc3_clk low 0.5*P-0.270 (1) ns
    SDR505 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -3.66 1.46 ns
    SDR506 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -3.66 1.46 ns
    1. P = output mmc3_clk period in ns
    2. i in [i:0] = 7
    AM5718-HIREL SPRS906_TIMING_MMC3_05.gif Figure 7-90 MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode
    AM5718-HIREL SPRS906_TIMING_MMC3_06.gif Figure 7-91 MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode

    NOTE

    To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.

    The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module chapter in the Device TRM.

    Manual IO Timings Modes must be used to guaranteed some IO timings for MMC3. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-129 Manual Functions Mapping for MMC3 for a definition of the Manual modes.

    Table 7-129 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-129 Manual Functions Mapping for MMC3

    BALL BALL NAME MMC3_MANUAL1 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 0
    AD4 mmc3_clk 1085 21 CFG_MMC3_CLK_IN mmc3_clk
    AD4 mmc3_clk 1269 0 CFG_MMC3_CLK_OUT mmc3_clk
    AC4 mmc3_cmd 0 0 CFG_MMC3_CMD_IN mmc3_cmd
    AC4 mmc3_cmd 128 0 CFG_MMC3_CMD_OEN mmc3_cmd
    AC4 mmc3_cmd 98 0 CFG_MMC3_CMD_OUT mmc3_cmd
    AC7 mmc3_dat0 0 0 CFG_MMC3_DAT0_IN mmc3_dat0
    AC7 mmc3_dat0 362 0 CFG_MMC3_DAT0_OEN mmc3_dat0
    AC7 mmc3_dat0 0 0 CFG_MMC3_DAT0_OUT mmc3_dat0
    AC6 mmc3_dat1 7 0 CFG_MMC3_DAT1_IN mmc3_dat1
    AC6 mmc3_dat1 333 0 CFG_MMC3_DAT1_OEN mmc3_dat1
    AC6 mmc3_dat1 0 0 CFG_MMC3_DAT1_OUT mmc3_dat1
    AC9 mmc3_dat2 0 0 CFG_MMC3_DAT2_IN mmc3_dat2
    AC9 mmc3_dat2 402 0 CFG_MMC3_DAT2_OEN mmc3_dat2
    AC9 mmc3_dat2 0 0 CFG_MMC3_DAT2_OUT mmc3_dat2
    AC3 mmc3_dat3 203 0 CFG_MMC3_DAT3_IN mmc3_dat3
    AC3 mmc3_dat3 549 0 CFG_MMC3_DAT3_OEN mmc3_dat3
    AC3 mmc3_dat3 1 0 CFG_MMC3_DAT3_OUT mmc3_dat3
    AC8 mmc3_dat4 121 0 CFG_MMC3_DAT4_IN mmc3_dat4
    AC8 mmc3_dat4 440 0 CFG_MMC3_DAT4_OEN mmc3_dat4
    AC8 mmc3_dat4 206 0 CFG_MMC3_DAT4_OUT mmc3_dat4
    AD6 mmc3_dat5 336 0 CFG_MMC3_DAT5_IN mmc3_dat5
    AD6 mmc3_dat5 283 0 CFG_MMC3_DAT5_OEN mmc3_dat5
    AD6 mmc3_dat5 174 0 CFG_MMC3_DAT5_OUT mmc3_dat5
    AB8 mmc3_dat6 320 0 CFG_MMC3_DAT6_IN mmc3_dat6
    AB8 mmc3_dat6 443 0 CFG_MMC3_DAT6_OEN mmc3_dat6
    AB8 mmc3_dat6 0 0 CFG_MMC3_DAT6_OUT mmc3_dat6
    AB5 mmc3_dat7 2 0 CFG_MMC3_DAT7_IN mmc3_dat7
    AB5 mmc3_dat7 344 0 CFG_MMC3_DAT7_OEN mmc3_dat7
    AB5 mmc3_dat7 0 0 CFG_MMC3_DAT7_OUT mmc3_dat7

    NOTE

    To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

    The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

    General-Purpose Interface (GPIO)

    The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 215 pins.

    These pins can be configured for the following applications:

    • Data input (capture)/output (drive)
    • Keyboard interface with a debounce cell
    • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations
    • Wake-up request generation in idle mode upon the detection of external events

    NOTE

    For more information, see the General-Purpose Interface chapter of the Device TRM.

    NOTE

    The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.

    PRU-ICSS Interfaces

    The device Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) consists of dual 32-bit Load / Store RISC CPU cores - Programmable Real-Time Units (PRU0 and PRU1), shared, data, and instruction memories, internal peripheral modules, and an interrupt controller (PRU-ICSS_INTC). The programmable nature of the PRUs, along with their access to pins, events and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, customer peripheral interfaces, and in off-loading tasks from the other processor cores of the system-on-chip (SoC).

    The each PRU-ICSS includes the following main features:

    • 21x Enhanced GPIs (EGPIs) and 21x Enhanced GPOs (EGPOs) with asynchronous capture and serial support per each PRU CPU core
    • One Ethernet MII_RT module (PRU-ICSS_MII_RT) with two MII ports and configurable connections to PRUs
    • 1 MDIO Port (PRU-ICSS_MII_MDIO)
    • One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions
    • 1 x 16550-compatible UART with a dedicated 192 MHz clock to support 12Mbps Profibus
    • 1 Industrial Ethernet timer with 7/9 capture and 8 compare events
    • 1 Enhanced Capture Module (ECAP)
    • 1 Interrupt Controller (PRU-ICSS_INTC)
    • A flexible power management support
    • Integrated switched central resource with programmable priority
    • Parity control supported by all memories

    CAUTION

    The I/O timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 7-152 and Table 7-153.

    NOTE

    For more information about PRU-ICSS subsystems interfaces, please see the device TRM.

    NOTE

    To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

    The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter.

    Programmable Real-Time Unit (PRU-ICSS PRU)

    PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing

    Table 7-130 PRU-ICSS PRU Timing Requirements - Direct Input Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(GPI) Pulse width, GPI 2*P (1) ns
    2 tsk(GPI) Skew between GPI[20:0] signals 4.5 ns
    1. ICSS_CLK clock period
    AM5718-HIREL SPRS91x_TIMING_PRU_01.gif Figure 7-92 PRU-ICSS PRU Direct Input Timing
    1. m in GPI[m:0] = 20

    Table 7-131 PRU-ICSS PRU Switching Requirements - Direct Output Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(GPO) Pulse width, GPO 2*P (1) ns
    2 tsk(GPO) Skew between GPO[20:0] signals 4.5 ns
    1. ICSS_CLK clock period
    AM5718-HIREL SPRS91x_TIMING_PRU_02.gif Figure 7-93 PRU-ICSS PRU Direct Output Timing
    1. n in GPO[n:0] = 20

    PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing

    Table 7-132 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(CLOCKIN) Cyle time, CLOCKIN 20 ns
    2 tw(CLOCKIN_L) Pulse duration, CLOCKIN low 9 11 ns
    3 tw(CLOCKIN_H) Pulse duration, CLOCKIN high 9 11 ns
    4 tsu(DATAIN-CLOCKIN) Setup time, DATAIN valid before CLOCKIN 4.5 ns
    5 th(CLOCKIN-DATAIN) Hold time, DATAIN valid after CLOCKIN 0 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_03.gif Figure 7-94 PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode
    AM5718-HIREL SPRS91x_TIMING_PRU_04.gif Figure 7-95 PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode

    PRU-ICSS PRU Shift Mode Electrical Data and Timing

    Table 7-133 PRU-ICSS PRU Timing Requirements - Shift In Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tc(DATAIN) Cycle time, DATAIN 10.00 ns
    2 tw(DATAIN) Pulse width, DATAIN 0.45*P (1) ns
    1. P = 10.00ns
    AM5718-HIREL SPRS91x_TIMING_PRU_05.gif Figure 7-96 PRU-ICSS PRU Shift In Timing

    Table 7-134 PRU-ICSS PRU Switching Requirements - Shift Out Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tc(CLOCKOUT) Cycle time, CLOCKOUT 10.00 ns
    2 tw(CLOCKOUT) Pulse width, CLOCKOUT 0.45*P (1) ns
    3 td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT Valid -3.00 3.60 ns
    1. P = 10.00ns
    AM5718-HIREL SPRS91x_TIMING_PRU_06.gif Figure 7-97 PRU-ICSS PRU Shift Out Timing

    PRU-ICSS PRU Sigma Delta and EnDAT Modes

    Table 7-135 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(SDx_CLK) Pulse width, SDx_CLK 20 ns
    2 tsu(SDx_D-SDx_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10 ns
    3 th(SDx_CLK-SDx_D) Hold time, SDx_D valid before SDx_CLK active edge 5 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_07.gif Figure 7-98 PRU-ICSS PRU SD_CLK Falling Active Edge
    AM5718-HIREL SPRS91x_TIMING_PRU_08.gif Figure 7-99 PRU-ICSS PRU SD_CLK Rising Active Edge

    Table 7-136 PRU-ICSS PRU Timing Requirements - EnDAT Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(ENDATx_IN) Pulse width, ENDATx_IN 40 ns

    Table 7-137 PRU-ICSS PRU Switching Requirements - EnDAT Mode

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    2 tw(ENDATx_CLK) Pulse width, ENDATx_CLK 20 ns
    3 td(ENDATx_OUT-ENDATx_CLK) Delay time, ENDATx_CLK fall to ENDATx_OUT -10 10 ns
    4 td(ENDATx_OUT_EN-ENDATx_CLK) Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN -10 10 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_09.gif Figure 7-100 PRU-ICSS PRU EnDAT Timing

    PRU-ICSS EtherCAT (PRU-ICSS ECAT)

    PRU-ICSS ECAT Electrical Data and Timing

    Table 7-138 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(EDIO_LATCH_IN) Pulse width, EDIO_LATCH_IN 100.00 ns
    2 tsu(EDIO_DATA_IN-EDIO_LATCH_IN) Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN active edge 20.00 ns
    3 th(EDIO_LATCH_IN-EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active edge 20.00 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_ECAT_01.gif Figure 7-101 PRU-ICSS ECAT Input Validated with LATCH_IN Timing

    Table 7-139 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(EDC_SYNCx_OUT) Pulse width, EDC_SYNCx_OUT 100.00 ns
    2 tsu(EDIO_DATA_IN-EDC_SYNCx_OUT) Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active edge 20.00 ns
    3 th(EDC_SYNCx_OUT-EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge 20.00 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_ECAT_02.gif Figure 7-102 PRU-ICSS ECAT Input Validated With SYNCx Timing

    Table 7-140 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(EDIO_SOF) Pulse duration, EDIO_SOF 4*P (1) 5*P (1) ns
    2 tsu(EDIO_DATA_IN-EDIO_SOF) Setup time, EDIO_DATA_IN valid before EDIO_SOF active edge 20.00 ns
    3 th(EDIO_SOF-EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDIO_SOF active edge 20.00 ns
    1. ICSS_IEP_CLK clock period
    AM5718-HIREL SPRS91x_TIMING_PRU_ECAT_03.gif Figure 7-103 PRU-ICSS ECAT Input Validated With SOF

    Table 7-141 PRU-ICSS ECAT Timing Requirements - LATCHx_IN

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(EDC_LATCHx_IN) Pulse duration, EDC_LATCHx_IN 3*P (1) ns
    1. ICSS_IEP_CLK clock period
    AM5718-HIREL SPRS91x_TIMING_PRU_ECAT_04.gif Figure 7-104 PRU-ICSS ECAT LATCHx_IN Timing

    Table 7-142 PRU-ICSS ECAT Switching Requirements - Digital IOs

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tw(EDIO_OUTVALID) Pulse duration, EDIO_OUTVALID 14*P (1) 32*P (1) ns
    2 td(EDIO_OUTVALID-EDIO_DATA_OUT) Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0.00 18 × P (1) ns
    1 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 8 ns
    1. ICSS_IEP_CLK clock period

    PRU-ICSS MII_RT and Switch

    PRU-ICSS MDIO Electrical Data and Timing

    Table 7-143 PRU-ICSS MDIO Timing Requirements - MDIO_DATA

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tsu(MDIO-MDC) Setup time, MDIO valid before MDC high 90 ns
    2 th(MDIO-MDC) Hold time, MDIO valid from MDC high 0 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_01.gif Figure 7-105 PRU-ICSS MDIO_DATA Timing - Input Mode

    Table 7-144 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 tc(MDC) Cycle time, MDC 400 ns
    2 tw(MDCH) Pulse duration, MDC high 160 ns
    3 tw(MDCL) Pulse duration, MDC low 160 ns
    4 tt(MDC) Transition time, MDC 5 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_02.gif Figure 7-106 PRU-ICSS MDIO_CLK Timing

    Table 7-145 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 td(MDC-MDIO) Delay time, MDC high to MDIO valid 0 390 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_03.gif Figure 7-107 PRU-ICSS MDIO_DATA Timing - Output Mode

    PRU-ICSS MII_RT Electrical Data and Timing

    NOTE

    In order to guarantee the MII_RT IO timing values published in the device data manual, the ICSS_CLK clock must be configured for 200MHz (default value) and the TX_CLK_DELAY bitfield in the PRUSS_MII_RT_TXCFG0/1 register must be set to 6h (non-default value).

    Table 7-146 PRU-ICSS MII_RT Timing Requirements - MII[x]_RXCLK

    NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
    1 tc(RX_CLK) Cycle time, RX_CLK 10 Mbps 399.96 400.04 ns
    100 Mbps 39.996 40.004 ns
    2 tw(RX_CLKH) Pulse duration, RX_CLK high 10 Mbps 140 260 ns
    100 Mbps 14 26 ns
    3 tw(RX_CLKL) Pulse duration, RX_CLK low 10 Mbps 140 260 ns
    100 Mbps 14 26 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_04.gif Figure 7-108 PRU-ICSS MII[x]_RXCLK Timing

    Table 7-147 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK

    NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
    1 tc(TX_CLK) Cycle time, TX_CLK 10 Mbps 399.96 400.04 ns
    100 Mbps 39.996 40.004 ns
    2 tw(TX_CLKH) Pulse duration, TX_CLK high 10 Mbps 140 260 ns
    100 Mbps 14 26 ns
    3 tw(TX_CLKL) Pulse duration, TX_CLK low 10 Mbps 140 260 ns
    100 Mbps 14 26 ns
    4 tt(TX_CLK) Transition time, TX_CLK 10 Mbps 3 ns
    100 Mbps 3 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_05.gif Figure 7-109 PRU-ICSS MII[x]_TXCLK Timing

    Table 7-148 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER

    NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
    1 tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 10 Mbps 8 ns
    tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK
    tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK
    tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 100 Mbps 8 ns
    tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK
    tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK
    2 th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK 10 Mbps 8 ns
    th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK
    th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK
    th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK 100 Mbps 8 ns
    th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK
    th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_06.gif Figure 7-110 PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing

    Table 7-149 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN

    NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
    1 td(TX_CLK-TXD) Delay time, TX_CLK high to TXD[3:0] valid 10 Mbps 5 25 ns
    td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid
    td(TX_CLK-TXD) Delay time, TX_CLK high to TXD[3:0] valid 100 Mbps 5 25 ns
    td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid
    AM5718-HIREL SPRS91x_TIMING_PRU_MII_RT_07.gif Figure 7-111 PRU-ICSS MII_TXD[3:0], MII_TXEN Timing

    PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)

    Table 7-150 Timing Requirements for PRU-ICSS UART Receive

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    3 tw(RX) Pulse duration, receive start, stop, data bit 0.96U (1) 1.05U ns
    1. U = UART baud time = 1/programmed baud rate.

    Table 7-151 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit

    NO. PARAMETER DESCRIPTION MIN MAX UNIT
    1 ƒbaud(baud) Maximum programmable baud rate 0 12 MHz
    2 tw(TX) Pulse duration, transmit start, stop, data bit U - 2 (1) U + 2 ns
    AM5718-HIREL SPRS91x_TIMING_PRU_UART_01.gif Figure 7-112 PRU-ICSS UART Timing

    In Table 7-152 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS1.

    Table 7-152 PRU-ICSS1 IOSETs

    SIGNALS IOSET1 IOSET2 IOSET3(1) IOSET4(1)
    BALL MUX BALL MUX BALL MUX BALL MUX
    PRU-ICSS 1
    pr1_pru1_gpi20 A4 12
    pr1_pru1_gpi19 B5 12
    pr1_pru1_gpi18 B4 12
    pr1_pru1_gpi17 B3 12
    pr1_pru1_gpi16 A3 12
    pr1_pru1_gpi15 C5 12
    pr1_pru1_gpi14 D6 12
    pr1_pru1_gpi13 B2 12
    pr1_pru1_gpi12 C4 12
    pr1_pru1_gpi11 C3 12
    pr1_pru1_gpi10 C2 12
    pr1_pru1_gpo20 A4 13
    pr1_pru1_gpo19 B5 13
    pr1_pru1_gpo18 B4 13
    pr1_pru1_gpo17 B3 13
    pr1_pru1_gpo16 A3 13
    pr1_pru1_gpo15 C5 13
    pr1_pru1_gpo14 D6 13
    pr1_pru1_gpo13 B2 13
    pr1_pru1_gpo12 C4 13
    pr1_pru1_gpo11 C3 13
    pr1_pru1_gpo10 C2 13
    pr1_pru1_gpi9 D5 12
    pr1_pru1_gpi8 F6 12
    pr1_pru1_gpi7 D3 12
    pr1_pru1_gpi6 E6 12
    pr1_pru1_gpi5 F5 12
    pr1_pru1_gpi4 E4 12
    pr1_pru1_gpi3 C1 12
    pr1_pru1_gpi2 F4 12
    pr1_pru1_gpi1 D2 12
    pr1_pru1_gpi0 E2 12
    pr1_pru1_gpo9 D5 13
    pr1_pru1_gpo8 F6 13
    pr1_pru1_gpo7 D3 13
    pr1_pru1_gpo6 E6 13
    pr1_pru1_gpo5 F5 13
    pr1_pru1_gpo4 E4 13
    pr1_pru1_gpo3 C1 13
    pr1_pru1_gpo2 F4 13
    pr1_pru1_gpo1 D2 13
    pr1_pru1_gpo0 E2 13
    pr1_edio_data_out7 D1 13
    pr1_edio_data_out6 F3 13
    pr1_edio_data_out5 F2 13
    pr1_edio_data_out4 G6 13
    pr1_edio_data_out3 G1 13
    pr1_edio_data_out2 H7 13
    pr1_edio_data_out1 G2 13
    pr1_edio_data_out0 E1 13
    pr1_edio_data_in7 D1 12
    pr1_edio_data_in6 F3 12
    pr1_edio_data_in5 F2 12
    pr1_edio_data_in4 G6 12
    pr1_edio_data_in3 G1 12
    pr1_edio_data_in2 H7 12
    pr1_edio_data_in1 G2 12
    pr1_edio_data_in0 E1 12
    pr1_edio_sof F4 11
    pr1_edc_latch0_in E2 11
    pr1_edc_sync0_out D2 11
    pr1_uart0_cts_n G1 11 F11 10
    pr1_uart0_rts_n G6 11 G10 10
    pr1_uart0_txd F3 11 G11 10
    pr1_uart0_rxd F2 11 F10 10
    pr1_ecap0_ecap_capin_apwm_o D1 11 E9 10
    PRU-ICSS 1 MII
    pr1_mii1_crs A4 11 G10 12
    pr1_mii1_rxlink B4 11 F11 12
    pr1_mii1_col B5 11 E2 12
    pr1_mii0_col V1 11 B9 12
    pr1_mii0_rxlink U4 11 A9 12
    pr1_mii0_crs V7 11 A10 12
    pr1_mii1_txd3 F5 11 F5 11
    pr1_mii1_txd2 E6 11 E6 11
    pr1_mii1_txd1 D5 11 D2 13
    pr1_mii1_txd0 C2 11 F4 13
    pr1_mii1_rxd3 B2 11 E9 12
    pr1_mii1_rxd2 D6 11 F9 12
    pr1_mii1_rxd1 C5 11 F8 12
    pr1_mii1_rxd0 A3 11 E7 12
    pr1_mii1_rxdv C4 11 G11 12
    pr1_mii1_txen E4 11 E4 11
    pr1_mii1_rxer B3 11 E11 12
    pr1_mii_mr1_clk C3 11 F10 12
    pr1_mii_mt1_clk C1 11 C1 11
    pr1_mii0_txd3 V5 11 D9 13
    pr1_mii0_txd2 V4 11 D7 13
    pr1_mii0_txd1 Y2 11 A5 13
    pr1_mii0_txd0 W2 11 C6 13
    pr1_mii0_rxd3 W9 11 B7 12
    pr1_mii0_rxd2 V9 11 B8 12
    pr1_mii0_rxd1 V6 11 A7 12
    pr1_mii0_rxd0 U6 11 A8 12
    pr1_mii0_rxdv V2 11 C7 12
    pr1_mii0_txen V3 11 D8 13
    pr1_mii0_rxer U7 11 C9 12
    pr1_mii_mt0_clk U5 11 E8 12
    pr1_mii_mr0_clk Y1 11 C8 12
    pr1_mdio_mdclk D3 11
    pr1_mdio_data F6 11
    1. These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the PRU-ICSS internal wrapper multiplexing.

    In Table 7-153, Table 7-154 and Table 7-155 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS2.

    Table 7-153 PRU-ICSS2 IOSETs

    SIGNALS IOSET1 IOSET2
    BALL MUX BALL MUX
    PRU-ICSS 2
    pr2_pru1_gpi20 F10 12 F10 12
    pr2_pru1_gpi19 G10 12 G10 12
    pr2_pru1_gpi18 F11 12 F11 12
    pr2_pru1_gpi17 E11 12 E11 12
    pr2_pru1_gpi16 W2 12 G14 12
    pr2_pru1_gpi15 Y2 12 A13 12
    pr2_pru1_gpi14 V3 12 E14 12
    pr2_pru1_gpi13 V4 12 A12 12
    pr2_pru1_gpi12 V5 12 B13 12
    pr2_pru1_gpi11 U5 12 A11 12
    pr2_pru1_gpi10 U6 12 B12 12
    pr2_pru1_gpi9 V6 12 F12 12
    pr2_pru1_gpi8 U7 12 G12 12
    pr2_pru1_gpi7 V7 12 C14 12
    pr2_pru1_gpi6 V9 12 E17 12
    pr2_pru1_gpi5 W9 12 D18 12
    pr2_pru1_gpi4 Y1 12 AA4 12
    pr2_pru1_gpi3 V2 12 AB3 12
    pr2_pru1_gpi2 U3 12 AB9 12
    pr2_pru1_gpi1 U4 12 AA3 12
    pr2_pru1_gpi0 V1 12 D17 12
    pr2_pru1_gpo20 F10 13 F10 13
    pr2_pru1_gpo19 G10 13 G10 13
    pr2_pru1_gpo18 F11 13 F11 13
    pr2_pru1_gpo17 E11 13 E11 13
    pr2_pru1_gpo16 W2 13 G14 13
    pr2_pru1_gpo15 Y2 13 A13 13
    pr2_pru1_gpo14 V3 13 E14 13
    pr2_pru1_gpo13 V4 13 A12 13
    pr2_pru1_gpo12 V5 13 B13 13
    pr2_pru1_gpo11 U5 13 A11 13
    pr2_pru1_gpo10 U6 13 B12 13
    pr2_pru1_gpo9 V6 13 F12 13
    pr2_pru1_gpo8 U7 13 G12 13
    pr2_pru1_gpo7 V7 13 C14 13
    pr2_pru1_gpo6 V9 13 E17 13
    pr2_pru1_gpo5 W9 13 D18 13
    pr2_pru1_gpo4 Y1 13 AA4 13
    pr2_pru1_gpo3 V2 13 AB3 13
    pr2_pru1_gpo2 U3 13 AB9 13
    pr2_pru1_gpo1 U4 13 AA3 13
    pr2_pru1_gpo0 V1 13 D17 13
    pr2_pru0_gpi20 A10 12 F14 12
    pr2_pru0_gpi19 B9 12 A18 12
    pr2_pru0_gpi18 A9 12 A19 12
    pr2_pru0_gpi17 C9 12 A16 12
    pr2_pru0_gpi16 A8 12 C15 12
    pr2_pru0_gpi15 A7 12 C17 12
    pr2_pru0_gpi14 B8 12 B19 12
    pr2_pru0_gpi13 B7 12 F15 12
    pr2_pru0_gpi12 C7 12 B18 12
    pr2_pru0_gpi11 C8 12 AB5 12
    pr2_pru0_gpi10 C6 12 AB8 12
    pr2_pru0_gpi9 A5 12 AD6 12
    pr2_pru0_gpi8 D8 12 AC8 12
    pr2_pru0_gpi7 D7 12 AC3 12
    pr2_pru0_gpi6 D9 12 AC9 12
    pr2_pru0_gpi5 E8 12 AC6 12
    pr2_pru0_gpi4 E7 12 AC7 12
    pr2_pru0_gpi3 F8 12 AC4 12
    pr2_pru0_gpi2 F9 12 AD4 12
    pr2_pru0_gpi1 E9 12 AB4 12
    pr2_pru0_gpi0 G11 12 AC5 12
    pr2_pru0_gpo20 A10 13 F14 13
    pr2_pru0_gpo19 B9 13 A18 13
    pr2_pru0_gpo18 A9 13 A19 13
    pr2_pru0_gpo17 C9 13 A16 13
    pr2_pru0_gpo16 A8 13 C15 13
    pr2_pru0_gpo15 A7 13 C17 13
    pr2_pru0_gpo14 B8 13 B19 13
    pr2_pru0_gpo13 B7 13 F15 13
    pr2_pru0_gpo12 C7 13 B18 13
    pr2_pru0_gpo11 C8 13 AB5 13
    pr2_pru0_gpo10 C6 13 AB8 13
    pr2_pru0_gpo9 A5 13 AD6 13
    pr2_pru0_gpo8 D8 13 AC8 13
    pr2_pru0_gpo7 D7 13 AC3 13
    pr2_pru0_gpo6 D9 13 AC9 13
    pr2_pru0_gpo5 E8 13 AC6 13
    pr2_pru0_gpo4 E7 13 AC7 13
    pr2_pru0_gpo3 F8 13 AC4 13
    pr2_pru0_gpo2 F9 13 AD4 13
    pr2_pru0_gpo1 E9 13 AB4 13
    pr2_pru0_gpo0 G11 13 AC5 13
    pr2_mii1_crs E17 11
    pr2_mii1_rxlink C17 11
    pr2_mii0_crs B18 11
    pr2_mii0_rxlink A16 11
    pr2_mii0_col F15 11
    pr2_mii1_col D18 11
    pr2_edio_data_out7 A10 11
    pr2_edio_data_out6 B9 11
    pr2_edio_data_out5 A9 11
    pr2_edio_data_out4 C9 11
    pr2_edio_data_out3 A8 11
    pr2_edio_data_out2 A7 11
    pr2_edio_data_out1 B8 11
    pr2_edio_data_out0 B7 11
    pr2_edio_data_in7 A10 10
    pr2_edio_data_in6 B9 10
    pr2_edio_data_in5 A9 10
    pr2_edio_data_in4 C9 10
    pr2_edio_data_in3 A8 10
    pr2_edio_data_in2 A7 10
    pr2_edio_data_in1 B8 10
    pr2_edio_data_in0 B7 10
    pr2_edio_latch_in D9 10
    pr2_edio_sof D7 10
    pr2_edc_sync0_out E7 10
    pr2_edc_sync1_out E8 10
    pr2_edc_latch0_in F9 10
    pr2_edc_latch1_in F8 10
    pr2_uart0_rxd C6 10
    pr2_uart0_txd C8 10
    pr2_uart0_cts_n D8 10
    pr2_uart0_rts_n A5 10
    pr2_ecap0_ecap_capin_apwm_o C7 10
    PRU-ICSS 2 MII
    pr2_mii1_txd3 AD4 11
    pr2_mii1_txd2 AC4 11
    pr2_mii1_txd1 AC7 11
    pr2_mii1_txd0 AC6 11
    pr2_mii1_rxd3 AC8 11
    pr2_mii1_rxd2 AD6 11
    pr2_mii1_rxd1 AB8 11
    pr2_mii1_rxd0 AB5 11
    pr2_mii_mr1_clk AC9 11
    pr2_mii1_rxer B19 11
    pr2_mii_mt1_clk AC5 11
    pr2_mii1_rxdv AC3 11
    pr2_mii1_txen AB4 11
    pr2_mii0_txd3 A11 11
    pr2_mii0_txd2 B13 11
    pr2_mii0_txd1 A12 11
    pr2_mii0_txd0 E14 11
    pr2_mii0_rxd3 F14 11
    pr2_mii0_rxd2 A19 11
    pr2_mii0_rxd1 A18 11
    pr2_mii0_rxd0 C15 11
    pr2_mii_mr0_clk A13 11
    pr2_mii0_rxer G12 11
    pr2_mii_mt0_clk F12 11
    pr2_mii0_rxdv G14 11
    pr2_mii0_txen B12 11
    pr2_mdio_mdclk C14 11 AB3 11
    pr2_mdio_data D14 11 AA4 11

    Table 7-154 PRU-ICSS2 IOSETs (EnDAT)(1)

    SIGNALS IOSET3 IOSET4
    BALL MUX BALL MUX
    PRU-ICSS 2 EnDAT
    pr2_pru1_endat0_clk V1 13 D17 13
    pr2_pru1_endat0_out U4 13 AA3 13
    pr2_pru1_endat0_out_en U3 13 AB9 13
    pr2_pru1_endat1_clk V2 13 AB3 13
    pr2_pru1_endat1_out Y1 13 AA4 13
    pr2_pru1_endat1_out_en W9 13 D18 13
    pr2_pru1_endat2_clk V9 13 E17 13
    pr2_pru1_endat2_out V7 13 C14 13
    pr2_pru1_endat2_out_en U7 13 G12 13
    pr2_pru1_endat0_in V6 12 F12 12
    pr2_pru1_endat1_in U6 12 B12 12
    pr2_pru1_endat2_in U5 12 A11 12
    1. These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the PRU-ICSS internal wrapper multiplexing.

    Table 7-155 PRU-ICSS2 IOSETs (Sigma Delta)(1)

    SIGNALS IOSET3 IOSET4
    BALL MUX BALL MUX
    PRU-ICSS 2 SD
    pr2_pru0_sd0_clk G11 12 AC5 12
    pr2_pru0_sd0_d E9 12 AB4 12
    pr2_pru0_sd1_clk F9 12 AD4 12
    pr2_pru0_sd1_d F8 12 AC4 12
    pr2_pru0_sd2_clk E7 12 AC7 12
    pr2_pru0_sd2_d E8 12 AC6 12
    pr2_pru0_sd3_clk D9 12 AC9 12
    pr2_pru0_sd3_d D7 12 AC3 12
    pr2_pru0_sd4_clk D8 12 AC8 12
    pr2_pru0_sd4_d A5 12 AD6 12
    pr2_pru0_sd5_clk C6 12 AB8 12
    pr2_pru0_sd5_d C8 12 AB5 12
    pr2_pru0_sd6_clk C7 12 B18 12
    pr2_pru0_sd6_d B7 12 F15 12
    pr2_pru0_sd7_clk B8 12 B19 12
    pr2_pru0_sd7_d A7 12 C17 12
    pr2_pru0_sd8_clk A8 12 C15 12
    pr2_pru0_sd8_d C9 12 A16 12
    1. These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the PRU-ICSS internal wrapper multiplexing.

    PRU-ICSS Manual Functional Mapping

    NOTE

    To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

    The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module Chapter in the Device TRM.

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-156 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the Manual modes.

    Table 7-156 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-156 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode

    BALL BALL NAME PR1_PRU1_DIR_IN_MANUAL CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 12
    D3 vin2a_d10 0 800 CFG_VIN2A_D10_IN pr1_pru1_gpi7
    F6 vin2a_d11 0 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
    D5 vin2a_d12 0 200 CFG_VIN2A_D12_IN pr1_pru1_gpi9
    C2 vin2a_d13 0 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
    C3 vin2a_d14 0 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
    C4 vin2a_d15 0 400 CFG_VIN2A_D15_IN pr1_pru1_gpi12
    B2 vin2a_d16 0 300 CFG_VIN2A_D16_IN pr1_pru1_gpi13
    D6 vin2a_d17 0 400 CFG_VIN2A_D17_IN pr1_pru1_gpi14
    C5 vin2a_d18 0 900 CFG_VIN2A_D18_IN pr1_pru1_gpi15
    A3 vin2a_d19 0 1500 CFG_VIN2A_D19_IN pr1_pru1_gpi16
    B3 vin2a_d20 0 100 CFG_VIN2A_D20_IN pr1_pru1_gpi17
    B4 vin2a_d21 0 500 CFG_VIN2A_D21_IN pr1_pru1_gpi18
    B5 vin2a_d22 0 500 CFG_VIN2A_D22_IN pr1_pru1_gpi19
    A4 vin2a_d23 0 600 CFG_VIN2A_D23_IN pr1_pru1_gpi20
    E2 vin2a_d3 0 900 CFG_VIN2A_D3_IN pr1_pru1_gpi0
    D2 vin2a_d4 0 100 CFG_VIN2A_D4_IN pr1_pru1_gpi1
    F4 vin2a_d5 0 600 CFG_VIN2A_D5_IN pr1_pru1_gpi2
    C1 vin2a_d6 0 200 CFG_VIN2A_D6_IN pr1_pru1_gpi3
    E4 vin2a_d7 0 400 CFG_VIN2A_D7_IN pr1_pru1_gpi4
    F5 vin2a_d8 0 500 CFG_VIN2A_D8_IN pr1_pru1_gpi5
    E6 vin2a_d9 0 600 CFG_VIN2A_D9_IN pr1_pru1_gpi6

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-157 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the Manual modes.

    Table 7-157 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-157 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode

    BALL BALL NAME PR1_PRU1_DIR_OUT_MANUAL CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 13
    D3 vin2a_d10 0 1000 CFG_VIN2A_D10_OUT pr1_pru1_gpo7
    F6 vin2a_d11 0 1300 CFG_VIN2A_D11_OUT pr1_pru1_gpo8
    D5 vin2a_d12 0 2300 CFG_VIN2A_D12_OUT pr1_pru1_gpo9
    C2 vin2a_d13 0 2200 CFG_VIN2A_D13_OUT pr1_pru1_gpo10
    C3 vin2a_d14 0 1800 CFG_VIN2A_D14_OUT pr1_pru1_gpo11
    C4 vin2a_d15 0 1800 CFG_VIN2A_D15_OUT pr1_pru1_gpo12
    B2 vin2a_d16 0 1600 CFG_VIN2A_D16_OUT pr1_pru1_gpo13
    D6 vin2a_d17 0 2000 CFG_VIN2A_D17_OUT pr1_pru1_gpo14
    C5 vin2a_d18 0 700 CFG_VIN2A_D18_OUT pr1_pru1_gpo15
    A3 vin2a_d19 0 700 CFG_VIN2A_D19_OUT pr1_pru1_gpo16
    B3 vin2a_d20 0 500 CFG_VIN2A_D20_OUT pr1_pru1_gpo17
    B4 vin2a_d21 0 400 CFG_VIN2A_D21_OUT pr1_pru1_gpo18
    B5 vin2a_d22 0 0 CFG_VIN2A_D22_OUT pr1_pru1_gpo19
    A4 vin2a_d23 0 400 CFG_VIN2A_D23_OUT pr1_pru1_gpo20
    E2 vin2a_d3 0 2200 CFG_VIN2A_D3_OUT pr1_pru1_gpo0
    D2 vin2a_d4 540 2800 CFG_VIN2A_D4_OUT pr1_pru1_gpo1
    F4 vin2a_d5 0 400 CFG_VIN2A_D5_OUT pr1_pru1_gpo2
    C1 vin2a_d6 0 1500 CFG_VIN2A_D6_OUT pr1_pru1_gpo3
    E4 vin2a_d7 0 2200 CFG_VIN2A_D7_OUT pr1_pru1_gpo4
    F5 vin2a_d8 0 2600 CFG_VIN2A_D8_OUT pr1_pru1_gpo5
    E6 vin2a_d9 0 2300 CFG_VIN2A_D9_OUT pr1_pru1_gpo6

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Parallel Capture Mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-158 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode for a definition of the Manual modes.

    Table 7-158 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-158 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode

    BALL BALL NAME PR1_PRU1_PAR_CAP_MANUAL CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 12
    D3 vin2a_d10 1535 0 CFG_VIN2A_D10_IN pr1_pru1_gpi7
    F6 vin2a_d11 1151 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
    D5 vin2a_d12 1173 0 CFG_VIN2A_D12_IN pr1_pru1_gpi9
    C2 vin2a_d13 970 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
    C3 vin2a_d14 1196 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
    C4 vin2a_d15 1286 0 CFG_VIN2A_D15_IN pr1_pru1_gpi12
    B2 vin2a_d16 1354 0 CFG_VIN2A_D16_IN pr1_pru1_gpi13
    D6 vin2a_d17 1331 0 CFG_VIN2A_D17_IN pr1_pru1_gpi14
    C5 vin2a_d18 2097 0 CFG_VIN2A_D18_IN pr1_pru1_gpi15
    A3 vin2a_d19 0 453 CFG_VIN2A_D19_IN pr1_pru1_gpi16
    E2 vin2a_d3 1566 0 CFG_VIN2A_D3_IN pr1_pru1_gpi0
    D2 vin2a_d4 1012 0 CFG_VIN2A_D4_IN pr1_pru1_gpi1
    F4 vin2a_d5 1337 0 CFG_VIN2A_D5_IN pr1_pru1_gpi2
    C1 vin2a_d6 1130 0 CFG_VIN2A_D6_IN pr1_pru1_gpi3
    E4 vin2a_d7 1202 0 CFG_VIN2A_D7_IN pr1_pru1_gpi4
    F5 vin2a_d8 1395 0 CFG_VIN2A_D8_IN pr1_pru1_gpi5
    E6 vin2a_d9 1338 0 CFG_VIN2A_D9_IN pr1_pru1_gpi6

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-159 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode for a definition of the Manual modes.

    Table 7-159 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-159 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode

    BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 12
    D7 vout1_d10 0 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7
    D8 vout1_d11 0 0 CFG_VOUT1_D11_IN pr2_pru0_gpi8
    A5 vout1_d12 0 0 CFG_VOUT1_D12_IN pr2_pru0_gpi9
    C6 vout1_d13 0 0 CFG_VOUT1_D13_IN pr2_pru0_gpi10
    C8 vout1_d14 0 0 CFG_VOUT1_D14_IN pr2_pru0_gpi11
    C7 vout1_d15 0 0 CFG_VOUT1_D15_IN pr2_pru0_gpi12
    B7 vout1_d16 0 0 CFG_VOUT1_D16_IN pr2_pru0_gpi13
    B8 vout1_d17 0 0 CFG_VOUT1_D17_IN pr2_pru0_gpi14
    A7 vout1_d18 0 0 CFG_VOUT1_D18_IN pr2_pru0_gpi15
    A8 vout1_d19 0 0 CFG_VOUT1_D19_IN pr2_pru0_gpi16
    C9 vout1_d20 0 0 CFG_VOUT1_D20_IN pr2_pru0_gpi17
    A9 vout1_d21 0 0 CFG_VOUT1_D21_IN pr2_pru0_gpi18
    B9 vout1_d22 0 0 CFG_VOUT1_D22_IN pr2_pru0_gpi19
    A10 vout1_d23 0 0 CFG_VOUT1_D23_IN pr2_pru0_gpi20
    G11 vout1_d3 0 0 CFG_VOUT1_D3_IN pr2_pru0_gpi0
    E9 vout1_d4 0 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1
    F9 vout1_d5 0 0 CFG_VOUT1_D5_IN pr2_pru0_gpi2
    F8 vout1_d6 0 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3
    E7 vout1_d7 0 0 CFG_VOUT1_D7_IN pr2_pru0_gpi4
    E8 vout1_d8 0 0 CFG_VOUT1_D8_IN pr2_pru0_gpi5
    D9 vout1_d9 0 0 CFG_VOUT1_D9_IN pr2_pru0_gpi6

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-160 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a definition of the Manual modes.

    Table 7-160 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-160 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode

    BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 12
    AC5 gpio6_10 1000 3300 CFG_GPIO6_10_IN pr2_pru0_gpi0
    AB4 gpio6_11 1000 3400 CFG_GPIO6_11_IN pr2_pru0_gpi1
    F14 mcasp1_axr15 0 1300 CFG_MCASP1_AXR15_IN pr2_pru0_gpi20
    A19 mcasp2_aclkx 0 800 CFG_MCASP2_ACLKX_IN pr2_pru0_gpi18
    C15 mcasp2_axr2 0 1900 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
    A16 mcasp2_axr3 0 1400 CFG_MCASP2_AXR3_IN pr2_pru0_gpi17
    A18 mcasp2_fsx 0 1400 CFG_MCASP2_FSX_IN pr2_pru0_gpi19
    B19 mcasp3_axr0 0 1400 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
    C17 mcasp3_axr1 0 1000 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
    F15 mcasp3_fsx 0 1300 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
    AD4 mmc3_clk 1000 3700 CFG_MMC3_CLK_IN pr2_pru0_gpi2
    AC4 mmc3_cmd 1000 3500 CFG_MMC3_CMD_IN pr2_pru0_gpi3
    AC7 mmc3_dat0 1000 3500 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
    AC6 mmc3_dat1 1000 4000 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
    AC9 mmc3_dat2 1000 3300 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
    AC3 mmc3_dat3 1000 3900 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
    AC8 mmc3_dat4 1000 3500 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
    AD6 mmc3_dat5 1000 3600 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
    AB8 mmc3_dat6 1000 3500 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
    AB5 mmc3_dat7 1000 3100 CFG_MMC3_DAT7_IN pr2_pru0_gpi11
    B18 mcasp3_aclkx 0 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-161 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode for a definition of the Manual modes.

    Table 7-161 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-161 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode

    BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 13
    D7 vout1_d10 0 600 CFG_VOUT1_D10_OUT pr2_pru0_gpo7
    D8 vout1_d11 0 700 CFG_VOUT1_D11_OUT pr2_pru0_gpo8
    A5 vout1_d12 1200 200 CFG_VOUT1_D12_OUT pr2_pru0_gpo9
    C6 vout1_d13 0 600 CFG_VOUT1_D13_OUT pr2_pru0_gpo10
    C8 vout1_d14 200 300 CFG_VOUT1_D14_OUT pr2_pru0_gpo11
    C7 vout1_d15 400 0 CFG_VOUT1_D15_OUT pr2_pru0_gpo12
    B7 vout1_d16 0 0 CFG_VOUT1_D16_OUT pr2_pru0_gpo13
    B8 vout1_d17 0 300 CFG_VOUT1_D17_OUT pr2_pru0_gpo14
    A7 vout1_d18 120 300 CFG_VOUT1_D18_OUT pr2_pru0_gpo15
    A8 vout1_d19 0 0 CFG_VOUT1_D19_OUT pr2_pru0_gpo16
    C9 vout1_d20 250 200 CFG_VOUT1_D20_OUT pr2_pru0_gpo17
    A9 vout1_d21 300 200 CFG_VOUT1_D21_OUT pr2_pru0_gpo18
    B9 vout1_d22 0 0 CFG_VOUT1_D22_OUT pr2_pru0_gpo19
    A10 vout1_d23 0 0 CFG_VOUT1_D23_OUT pr2_pru0_gpo20
    G11 vout1_d3 920 0 CFG_VOUT1_D3_OUT pr2_pru0_gpo0
    E9 vout1_d4 1500 300 CFG_VOUT1_D4_OUT pr2_pru0_gpo1
    F9 vout1_d5 460 100 CFG_VOUT1_D5_OUT pr2_pru0_gpo2
    F8 vout1_d6 300 300 CFG_VOUT1_D6_OUT pr2_pru0_gpo3
    E7 vout1_d7 160 0 CFG_VOUT1_D7_OUT pr2_pru0_gpo4
    E8 vout1_d8 0 0 CFG_VOUT1_D8_OUT pr2_pru0_gpo5
    D9 vout1_d9 0 1200 CFG_VOUT1_D9_OUT pr2_pru0_gpo6

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-162 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode for a definition of the Manual modes.

    Table 7-162 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-162 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode

    BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 13
    AC5 gpio6_10 1800 1900 CFG_GPIO6_10_OUT pr2_pru0_gpo0
    AB4 gpio6_11 2500 2100 CFG_GPIO6_11_OUT pr2_pru0_gpo1
    F14 mcasp1_axr15 0 400 CFG_MCASP1_AXR15_OUT pr2_pru0_gpo20
    A19 mcasp2_aclkx 0 400 CFG_MCASP2_ACLKX_OUT pr2_pru0_gpo18
    C15 mcasp2_axr2 0 500 CFG_MCASP2_AXR2_OUT pr2_pru0_gpo16
    A16 mcasp2_axr3 0 500 CFG_MCASP2_AXR3_OUT pr2_pru0_gpo17
    A18 mcasp2_fsx 0 0 CFG_MCASP2_FSX_OUT pr2_pru0_gpo19
    B18 mcasp3_aclkx 0 500 CFG_MCASP3_ACLKX_OUT pr2_pru0_gpo12
    B19 mcasp3_axr0 0 0 CFG_MCASP3_AXR0_OUT pr2_pru0_gpo14
    C17 mcasp3_axr1 0 200 CFG_MCASP3_AXR1_OUT pr2_pru0_gpo15
    F15 mcasp3_fsx 0 300 CFG_MCASP3_FSX_OUT pr2_pru0_gpo13
    AD4 mmc3_clk 2100 2200 CFG_MMC3_CLK_OUT pr2_pru0_gpo2
    AC4 mmc3_cmd 2300 2300 CFG_MMC3_CMD_OUT pr2_pru0_gpo3
    AC7 mmc3_dat0 2000 1600 CFG_MMC3_DAT0_OUT pr2_pru0_gpo4
    AC6 mmc3_dat1 2000 1700 CFG_MMC3_DAT1_OUT pr2_pru0_gpo5
    AC9 mmc3_dat2 2050 2200 CFG_MMC3_DAT2_OUT pr2_pru0_gpo6
    AC3 mmc3_dat3 2000 2000 CFG_MMC3_DAT3_OUT pr2_pru0_gpo7
    AC8 mmc3_dat4 2150 2600 CFG_MMC3_DAT4_OUT pr2_pru0_gpo8
    AD6 mmc3_dat5 2400 2600 CFG_MMC3_DAT5_OUT pr2_pru0_gpo9
    AB8 mmc3_dat6 2200 2300 CFG_MMC3_DAT6_OUT pr2_pru0_gpo10
    AB5 mmc3_dat7 1800 2400 CFG_MMC3_DAT7_OUT pr2_pru0_gpo11

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-163 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode for a definition of the Manual modes.

    Table 7-163 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-163 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode

    BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 12
    U3 RMII_MHZ_50_CLK 1400 1200 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
    U4 mdio_d 1300 1600 CFG_MDIO_D_IN pr2_pru1_gpi1
    V1 mdio_mclk 1400 800 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
    U5 rgmii0_rxc 1400 500 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
    V5 rgmii0_rxctl 1400 1800 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
    W2 rgmii0_rxd0 1400 1300 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
    Y2 rgmii0_rxd1 1400 1650 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
    V3 rgmii0_rxd2 1400 1400 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
    V4 rgmii0_rxd3 1400 1650 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
    W9 rgmii0_txc 1400 900 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
    V9 rgmii0_txctl 1400 1300 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
    U6 rgmii0_txd0 1400 900 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
    V6 rgmii0_txd1 1300 1400 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
    U7 rgmii0_txd2 1300 1100 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
    V7 rgmii0_txd3 1300 1300 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
    V2 uart3_rxd 1300 1000 CFG_UART3_RXD_IN pr2_pru1_gpi3
    Y1 uart3_txd 1300 800 CFG_UART3_TXD_IN pr2_pru1_gpi4
    E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_IN pr2_pru1_gpi17
    F11 vout1_d0 0 0 CFG_VOUT1_D0_IN pr2_pru1_gpi18
    G10 vout1_d1 0 0 CFG_VOUT1_D1_IN pr2_pru1_gpi19
    F10 vout1_d2 0 0 CFG_VOUT1_D2_IN pr2_pru1_gpi20

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-164 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode for a definition of the Manual modes.

    Table 7-164 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-164 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode

    BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 12
    C14 mcasp1_aclkx 400 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
    G12 mcasp1_axr0 700 200 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
    F12 mcasp1_axr1 600 300 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
    B13 mcasp1_axr10 600 500 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
    A12 mcasp1_axr11 700 500 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
    E14 mcasp1_axr12 500 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
    A13 mcasp1_axr13 600 200 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
    G14 mcasp1_axr14 600 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
    E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_IN pr2_pru1_gpi17
    F11 vout1_d0 0 0 CFG_VOUT1_D0_IN pr2_pru1_gpi18
    G10 vout1_d1 0 0 CFG_VOUT1_D1_IN pr2_pru1_gpi19
    F10 vout1_d2 0 0 CFG_VOUT1_D2_IN pr2_pru1_gpi20
    B12 mcasp1_axr8 800 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
    A11 mcasp1_axr9 600 300 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
    D17 mcasp4_axr1 500 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
    AA3 mcasp5_aclkx 2100 1959 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
    AB3 mcasp5_axr0 2300 2000 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
    AA4 mcasp5_axr1 2300 1800 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
    AB9 mcasp5_fsx 2100 1780 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
    D18 xref_clk0 0 0 CFG_XREF_CLK0_IN pr2_pru1_gpi5
    E17 xref_clk1 0 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-165 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode for a definition of the Manual modes.

    Table 7-165 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-165 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode

    BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 13
    U3 RMII_MHZ_50_CLK 2306 100 CFG_RMII_MHZ_50_CLK_OUT pr2_pru1_gpo2
    U4 mdio_d 1900 2000 CFG_MDIO_D_OUT pr2_pru1_gpo1
    V1 mdio_mclk 2000 1100 CFG_MDIO_MCLK_OUT pr2_pru1_gpo0
    U5 rgmii0_rxc 2000 1200 CFG_RGMII0_RXC_OUT pr2_pru1_gpo11
    V5 rgmii0_rxctl 2000 1700 CFG_RGMII0_RXCTL_OUT pr2_pru1_gpo12
    W2 rgmii0_rxd0 2000 1000 CFG_RGMII0_RXD0_OUT pr2_pru1_gpo16
    Y2 rgmii0_rxd1 2200 1000 CFG_RGMII0_RXD1_OUT pr2_pru1_gpo15
    V3 rgmii0_rxd2 2200 1300 CFG_RGMII0_RXD2_OUT pr2_pru1_gpo14
    V4 rgmii0_rxd3 2250 1100 CFG_RGMII0_RXD3_OUT pr2_pru1_gpo13
    W9 rgmii0_txc 2350 1000 CFG_RGMII0_TXC_OUT pr2_pru1_gpo5
    V9 rgmii0_txctl 2000 1200 CFG_RGMII0_TXCTL_OUT pr2_pru1_gpo6
    U6 rgmii0_txd0 2000 1500 CFG_RGMII0_TXD0_OUT pr2_pru1_gpo10
    V6 rgmii0_txd1 1850 1000 CFG_RGMII0_TXD1_OUT pr2_pru1_gpo9
    U7 rgmii0_txd2 2100 1100 CFG_RGMII0_TXD2_OUT pr2_pru1_gpo8
    V7 rgmii0_txd3 2200 1000 CFG_RGMII0_TXD3_OUT pr2_pru1_gpo7
    V2 uart3_rxd 2000 1600 CFG_UART3_RXD_OUT pr2_pru1_gpo3
    Y1 uart3_txd 2000 1000 CFG_UART3_TXD_OUT pr2_pru1_gpo4
    F11 vout1_d0 400 0 CFG_VOUT1_D0_OUT pr2_pru1_gpo18
    G10 vout1_d1 0 0 CFG_VOUT1_D1_OUT pr2_pru1_gpo19
    F10 vout1_d2 200 0 CFG_VOUT1_D2_OUT pr2_pru1_gpo20
    E11 vout1_vsync 500 0 CFG_VOUT1_VSYNC_OUT pr2_pru1_gpo17

    Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-166 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode for a definition of the Manual modes.

    Table 7-166 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

    Table 7-166 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode

    BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
    A_DELAY (ps) G_DELAY (ps) 13
    C14 mcasp1_aclkx 200 800 CFG_MCASP1_ACLKX_OUT pr2_pru1_gpo7
    G12 mcasp1_axr0 200 1000 CFG_MCASP1_AXR0_OUT pr2_pru1_gpo8
    F12 mcasp1_axr1 0 1110 CFG_MCASP1_AXR1_OUT pr2_pru1_gpo9
    B13 mcasp1_axr10 0 2500 CFG_MCASP1_AXR10_OUT pr2_pru1_gpo12
    A12 mcasp1_axr11 0 1900 CFG_MCASP1_AXR11_OUT pr2_pru1_gpo13
    E14 mcasp1_axr12 0 2300 CFG_MCASP1_AXR12_OUT pr2_pru1_gpo14
    A13 mcasp1_axr13 200 1200 CFG_MCASP1_AXR13_OUT pr2_pru1_gpo15
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