SPRS999 August   2017 AM5718-HIREL

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3  Device Comparison
    1. 3.1 Device Comparison Table
  4. 4  Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem - Video Output Ports
      3. 4.4.3  Display Subsystem - High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power On Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY-1.5 V and 1.8 V
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
      4. 7.23.4 GMAC RGMII Timings
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Single-Ended Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 QSPI Board Design and Layout Guidelines
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical Packaging and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZBO|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Terminal Assignment

Figure 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and are used in conjunction with Table 4-2 through Table 4-35 to locate signal names and ball grid numbers.

AM5718-HIREL SPRS906_BALL_01.gif Figure 4-1 ZBO S-PBGA-N760 Package (Bottom View)

NOTE

The following bottom balls are not pinned out: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 / AE25 / AB26 / W3 / W26 / T3 / T26 / N3 / N26 / K3 / K26 / G3 / D4 / D25 / C10 / C13 / C16 / C19 / C22.

These balls do not exist on the package.

NOTE

The following bottom balls are not connected: AH11 / AH12 / AG2 / AG8 / AG11 / AG12 / AF4 / AF6 / AF8 / AF9 / AE3 / AE5 / AE6 / AE8 / AE9 / AD3 / AD8 / AD9 / Y15 / Y16 / V18 / V19 / U18 / U19 / U22 / U23 / U24 / U25 / U26 / U27 / U28 / T22 / T23 / T27 / T28 / R20 / R22 / R23 / R24 / R25 / R26 / R27 / R28 / P19 / P22 / P23 / P24 / P25 / P26 / P27 / N20 / N22 / N23 / N27 / N28 / M20 / M21 / M22 / M23 / M24 / M25 / M26 / M27 / M28 / L20 / L21 / L22 / L23 / L24 / L25 / L26 / L27 / L28 / K20 / K21 / K22 / K23 / K27 / K28 / J20 / J21 / J22 / J23 / J24 / J25 / J26 / J27 / H20 / H21 / H22 / H23 / H24 / H25 / H26 / H27 / H28 / G22 / G23 / G24 / G25 / G26 / G27 / G28 / F24 / F25 / F26 / F27 / F28 / E24 / E26 / E27 / E28.

These balls can be connected as desired, including to vss.

4.1.1 Unused Balls Connection Requirements

This section describes the Unused/Reserved balls connection requirements.

NOTE

The following balls are reserved: A27 / K14 / Y5 / Y10 / B28

These balls must be left unconnected.

NOTE

All unused power supply balls must be supplied with the voltages specified in the Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are included in Section 4.4, Signal Descriptions.

Table 4-1 Unused Balls Specific Connection Requirements

BALLS CONNECTION REQUIREMENTS
AE15 / AC15 / AE14 / D20 / AD17 / AC16 / V27 These balls must be connected to GND through an external pull resistor if unused
E20 / D21 / E23 / C20 / C21 / V28 / F18 These balls must be connect to the corresponding power supply through an external pull resistor if unused
AF14 (rtc_iso) This ball should be connected to the corresponding power supply through an external pull resistor if unused; or can be connected to F22 (porz) when RTC unused (level translation may be needed)
AB17 (rtc_porz) This ball should be connected to VSS when RTC is unused; or can be connected to F22 (porz) when RTC unused (level translation may be needed)

NOTE

All other unused signal balls with a Pad Configuration Register can be left unconnected with their internal pullup or pulldown resistor enabled.

NOTE

All other unused signal balls without Pad Configuration Register can be left unconnected.

4.2 Ball Characteristics

Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list describes the table column headers:

  1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

    4. NOTE

    Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal Descriptions.

    NOTE

    In the Driver off mode, the buffer is configured in high-impedance.

    NOTE

    In some cases Table 4-2 may present more than one signal name per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

    All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

  4. PN: This column shows if the functionality is applicable for AM5716 device. Note that the Ball Characteristics table presents a functionality of AM5718. If the cell is empty it means that the signal is available in all devices.
    - Yes - Functionality is presented in AM5716
    - No - Functionality is not presented in AM5716
    An empty box means Yes.
  5. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

      2. NOTE

      The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.
    2. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • D = Open drain
    • DS = Differential Signaling
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor
  7. BALL RESET STATE: The state of the terminal at power-on reset:
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
  8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor

    9. NOTE

    For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power, Reset, and Clock Management / PRCM Reset Management Functional Description section of the Device TRM.
  9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
  10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
  11. POWER: The voltage supply that powers the terminal IO buffers.

    12. NOTE

    VOUT1, VOUT2 and VOUT3 are only supported at 1.8V and not at 3.3V. This must be considered in the pin mux programming and VDDSHVx supply connections.
  12. HYS: Indicates if the input buffer is with hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis
      An empty box means "Yes".

    13. NOTE

    For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
  13. BUFFER TYPE: Drive strength of the associated output buffer.

    14. NOTE

    For programmable buffer strength:

    • The default value is given in Table 4-2.
    • A note describes all possible values according to the selected muxmode.
  14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
    • 0: Logic 0 driven on the peripheral's input signal port.
    • 1: Logic 1 driven on the peripheral's input signal port.
    • blank: Pin state driven on the peripheral's input signal port.

    16. NOTE

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

    NOTE

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

    NOTE

    Some of the EMIF1 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

    drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0].

    OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0].

    NOTE

    Dual rank support is not available on this device, but signal names are retained for consistency with the AM57xx family of devices.

Table 4-2 Ball Characteristics(1)

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14]
K9 cap_vbbldo_dsp cap_vbbldo_dsp CAP
Y14 cap_vbbldo_gpu cap_vbbldo_gpu CAP
J10 cap_vbbldo_iva cap_vbbldo_iva CAP
J16 cap_vbbldo_mpu cap_vbbldo_mpu CAP
T20 cap_vddram_core1 cap_vddram_core1 CAP
L9 cap_vddram_core3 cap_vddram_core3 CAP
J19 cap_vddram_core4 cap_vddram_core4 CAP
J9 cap_vddram_dsp cap_vddram_dsp CAP
Y13 cap_vddram_gpu cap_vddram_gpu CAP
K16 cap_vddram_iva cap_vddram_iva CAP
K19 cap_vddram_mpu cap_vddram_mpu CAP
AE1 csi2_0_dx0 csi2_0_dx0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AF1 csi2_0_dx1 csi2_0_dx1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AF2 csi2_0_dx2 csi2_0_dx2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH4 csi2_0_dx3 csi2_0_dx3 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH3 csi2_0_dx4 csi2_0_dx4 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AD2 csi2_0_dy0 csi2_0_dy0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AE2 csi2_0_dy1 csi2_0_dy1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AF3 csi2_0_dy2 csi2_0_dy2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG4 csi2_0_dy3 csi2_0_dy3 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG3 csi2_0_dy4 csi2_0_dy4 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG5 csi2_1_dx0 csi2_1_dx0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG6 csi2_1_dx1 csi2_1_dx1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH7 csi2_1_dx2 csi2_1_dx2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH5 csi2_1_dy0 csi2_1_dy0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH6 csi2_1_dy1 csi2_1_dy1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG7 csi2_1_dy2 csi2_1_dy2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
G19 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart8_txd 2 O
mmc2_sdwp 3 I
sata1_led 4 O
hdmi1_cec No 6 IO
gpio1_15 14 IO
Driver off 15 I
G20 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart8_rxd 2 I
mmc2_sdcd 3 I
hdmi1_hpd No 6 IO
gpio1_14 14 IO
Driver off 15 I
AD20 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC19 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC20 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB19 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF21 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH22 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG23 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE21 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF22 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE22 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD21 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD22 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC21 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF18 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE17 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD18 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF17 ddr1_ba0 ddr1_ba0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE18 ddr1_ba1 ddr1_ba1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB18 ddr1_ba2 ddr1_ba2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC18 ddr1_casn ddr1_casn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG24 ddr1_ck ddr1_ck 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG22 ddr1_cke ddr1_cke 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH23 ddr1_csn0 ddr1_csn0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB16 ddr1_csn1 ddr1_csn1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF25 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF26 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG26 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH26 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF24 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE24 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE23 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC23 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG27 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF28 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE26 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC24 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD25 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V20 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W20 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB28 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC28 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC27 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y19 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB27 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y20 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA23 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y22 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y23 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA24 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y24 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA26 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA25 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA28 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD23 ddr1_dqm0 ddr1_dqm0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB23 ddr1_dqm1 ddr1_dqm1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC26 ddr1_dqm2 ddr1_dqm2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA27 ddr1_dqm3 ddr1_dqm3 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V26 ddr1_dqm_ecc ddr1_dqm_ecc 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
V28 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
V27 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS DDR PUx/PDy
W22 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V23 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W19 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W23 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y25 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V24 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V25 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y26 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH24 ddr1_nck ddr1_nck 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE20 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC17 ddr1_odt1 ddr1_odt1 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF20 ddr1_rasn ddr1_rasn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG21 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y18 ddr1_vref0 ddr1_vref0 0 PWR OFF drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR NA
AH21 ddr1_wen ddr1_wen 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
G21 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_30 14 IO
D24 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_31 14 IO
AC5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_mclk 1 O
i2c3_sda 2 IO
vin2b_hsync1 4 I
vin1a_clk0 9 I
ehrpwm2A 10 O
pr2_mii_mt1_clk 11 I
pr2_pru0_gpi0 12 I
pr2_pru0_gpo0 13 O
gpio6_10 14 IO
Driver off 15 I
AB4 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_d 1 IO
i2c3_scl 2 IO
vin2b_vsync1 4 I
vin1a_de0 9 I
ehrpwm2B 10 O
pr2_mii1_txen 11 O
pr2_pru0_gpi1 12 I
pr2_pru0_gpo1 13 O
gpio6_11 14 IO
Driver off 15 I
E21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr8 1 IO
dcan2_tx 2 IO
uart10_rxd 3 I
vout2_hsync No 6 O
vin2a_hsync0
vin1a_hsync0		 8 I
i2c3_sda 9 IO
timer1 10 IO
gpio6_14 14 IO
Driver off 15 I
F20 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr9 1 IO
dcan2_rx 2 IO
uart10_txd 3 O
vout2_vsync No 6 O
vin2a_vsync0
vin1a_vsync0		 8 I
i2c3_scl 9 IO
timer2 10 IO
gpio6_15 14 IO
Driver off 15 I
F21 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr10 1 IO
vout2_fld No 6 O
vin2a_fld0
vin1a_fld0		 8 I
clkout1 9 O
timer3 10 IO
gpio6_16 14 IO
Driver off 15 I
R6 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d16 2 I
vout3_d16 No 3 O
vin2a_d0
vin1a_d0		 4 I
vin1b_d0 6 I
i2c4_scl 7 IO
uart5_rxd 8 I
gpio7_3
gpmc_a26
gpmc_a16		 14 IO
Driver off 15 I
T9 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d17 2 I
vout3_d17 No 3 O
vin2a_d1
vin1a_d1		 4 I
vin1b_d1 6 I
i2c4_sda 7 IO
uart5_txd 8 O
gpio7_4 14 IO
Driver off 15 I
T6 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d18 2 I
vout3_d18 No 3 O
vin2a_d2
vin1a_d2		 4 I
vin1b_d2 6 I
uart7_rxd 7 I
uart5_ctsn 8 I
gpio7_5 14 IO
Driver off 15 I
T7 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs2 1 O
vin1a_d19 2 I
vout3_d19 No 3 O
vin2a_d3
vin1a_d3		 4 I
vin1b_d3 6 I
uart7_txd 7 O
uart5_rtsn 8 O
gpio7_6 14 IO
Driver off 15 I
P6 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs3 1 O
vin1a_d20 2 I
vout3_d20 No 3 O
vin2a_d4
vin1a_d4		 4 I
vin1b_d4 6 I
i2c5_scl 7 IO
uart6_rxd 8 I
gpio1_26 14 IO
Driver off 15 I
R9 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d21 2 I
vout3_d21 No 3 O
vin2a_d5
vin1a_d5		 4 I
vin1b_d5 6 I
i2c5_sda 7 IO
uart6_txd 8 O
gpio1_27 14 IO
Driver off 15 I
R5 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d22 2 I
vout3_d22 No 3 O
vin2a_d6
vin1a_d6		 4 I
vin1b_d6 6 I
uart8_rxd 7 I
uart6_ctsn 8 I
gpio1_28 14 IO
Driver off 15 I
P5 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d23 2 I
vout3_d23 No 3 O
vin2a_d7
vin1a_d7		 4 I
vin1b_d7 6 I
uart8_txd 7 O
uart6_rtsn 8 O
gpio1_29 14 IO
Driver off 15 I
N7 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_hsync0 2 I
vout3_hsync No 3 O
vin1b_hsync1 6 I
timer12 7 IO
spi4_sclk 8 IO
gpio1_30 14 IO
Driver off 15 I
R4 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_vsync0 2 I
vout3_vsync No 3 O
vin1b_vsync1 6 I
timer11 7 IO
spi4_d1 8 IO
gpio1_31 14 IO
Driver off 15 I
N9 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_de0 2 I
vout3_de No 3 O
vin1b_clk1 6 I
timer10 7 IO
spi4_d0 8 IO
gpio2_0 14 IO
Driver off 15 I
P9 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_fld0 2 I
vout3_fld No 3 O
vin2a_fld0
vin1a_fld0		 4 I
vin1b_de1 6 I
timer9 7 IO
spi4_cs0 8 IO
gpio2_1 14 IO
Driver off 15 I
P4 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin2a_clk0
vin1a_clk0		 4 I
gpmc_a0 5 O
vin1b_fld1 6 I
timer8 7 IO
spi4_cs1 8 IO
dma_evt1 9 I
gpio2_2 14 IO
Driver off 15 I
R3 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_rtclk 1 I
vin2a_hsync0
vin1a_hsync0		 4 I
timer7 7 IO
spi4_cs2 8 IO
dma_evt2 9 I
gpio2_3 14 IO
Driver off 15 I
T2 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d3 1 IO
vin2a_vsync0
vin1a_vsync0		 4 I
timer6 7 IO
spi4_cs3 8 IO
gpio2_4 14 IO
Driver off 15 I
U2 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d2 1 IO
vin2a_d8
vin1a_d8		 4 I
timer5 7 IO
gpio2_5 14 IO
Driver off 15 I
U1 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d0 1 IO
vin2a_d9
vin1a_d9		 4 I
gpio2_6 14 IO
Driver off 15 I
P3 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d1 1 IO
vin2a_d10
vin1a_d10		 4 I
gpio2_7 14 IO
Driver off 15 I
R2 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_sclk 1 IO
vin2a_d11
vin1a_d11		 4 I
gpio2_8 14 IO
Driver off 15 I
K7 gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat4 1 IO
gpmc_a13 2 O
vin2a_d12
vin1a_d12		 4 I
vin2b_d0
vin1b_d0		 6 I
gpio2_9 14 IO
Driver off 15 I
M7 gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat5 1 IO
gpmc_a14 2 O
vin2a_d13
vin1a_d13		 4 I
vin2b_d1
vin1b_d1		 6 I
gpio2_10 14 IO
Driver off 15 I
J5 gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat6 1 IO
gpmc_a15 2 O
vin2a_d14
vin1a_d14		 4 I
vin2b_d2
vin1b_d2		 6 I
gpio2_11 14 IO
Driver off 15 I
K6 gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat7 1 IO
gpmc_a16 2 O
vin2a_d15
vin1a_d15		 4 I
vin2b_d3
vin1b_d3		 6 I
gpio2_12 14 IO
Driver off 15 I
J7 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_clk 1 IO
gpmc_a17 2 O
vin2a_fld0
vin1a_fld0		 4 I
vin2b_d4
vin1b_d4		 6 I
gpio2_13 14 IO
Driver off 15 I
J4 gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat0 1 IO
gpmc_a18 2 O
vin1a_d8 4 I
vin2b_d5
vin1b_d5		 6 I
gpio2_14 14 IO
Driver off 15 I
J6 gpmc_a25 gpmc_a25 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat1 1 IO
gpmc_a19 2 O
vin1a_d9 4 I
vin2b_d6
vin1b_d6		 6 I
gpio2_15 14 IO
Driver off 15 I
H4 gpmc_a26 gpmc_a26 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat2 1 IO
gpmc_a20 2 O
vin1a_d10 4 I
vin2b_d7
vin1b_d7		 6 I
gpio2_16 14 IO
Driver off 15 I
H5 gpmc_a27 gpmc_a27 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat3 1 IO
gpmc_a21 2 O
vin1a_d11 4 I
vin2b_hsync1
vin1b_hsync1		 6 I
gpio2_17 14 IO
Driver off 15 I
M6 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d0 2 I
vout3_d0 No 3 O
gpio1_6 14 IO
sysboot0 15 I
M2 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d1 2 I
vout3_d1 No 3 O
gpio1_7 14 IO
sysboot1 15 I
L5 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d2 2 I
vout3_d2 No 3 O
gpio1_8 14 IO
sysboot2 15 I
M1 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d3 2 I
vout3_d3 No 3 O
gpio1_9 14 IO
sysboot3 15 I
L6 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d4 2 I
vout3_d4 No 3 O
gpio1_10 14 IO
sysboot4 15 I
L4 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d5 2 I
vout3_d5 No 3 O
gpio1_11 14 IO
sysboot5 15 I
L3 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d6 2 I
vout3_d6 No 3 O
gpio1_12 14 IO
sysboot6 15 I
L2 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d7 2 I
vout3_d7 No 3 O
gpio1_13 14 IO
sysboot7 15 I
L1 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d8 2 I
vout3_d8 No 3 O
gpio7_18 14 IO
sysboot8 15 I
K2 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d9 2 I
vout3_d9 No 3 O
gpio7_19 14 IO
sysboot9 15 I
J1 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d10 2 I
vout3_d10 No 3 O
gpio7_28 14 IO
sysboot10 15 I
J2 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d11 2 I
vout3_d11 No 3 O
gpio7_29 14 IO
sysboot11 15 I
H1 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d12 2 I
vout3_d12 No 3 O
gpio1_18 14 IO
sysboot12 15 I
J3 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d13 2 I
vout3_d13 No 3 O
gpio1_19 14 IO
sysboot13 15 I
H2 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d14 2 I
vout3_d14 No 3 O
gpio1_20 14 IO
sysboot14 15 I
H3 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d15 2 I
vout3_d15 No 3 O
gpio1_21 14 IO
sysboot15 15 I
N1 gpmc_advn_ale gpmc_advn_ale 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs6 1 O
clkout2 2 O
gpmc_wait1 3 I
vin2a_vsync0
vin1a_vsync0		 4 I
gpmc_a2 5 O
gpmc_a23 6 O
timer3 7 IO
i2c3_sda 8 IO
dma_evt2 9 I
gpio2_23
gpmc_a19		 14 IO
Driver off 15 I
N6 gpmc_ben0 gpmc_ben0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs4 1 O
vin2b_de1
vin1b_de1		 6 I
timer2 7 IO
dma_evt3 9 I
gpio2_26
gpmc_a21		 14 IO
Driver off 15 I
M4 gpmc_ben1 gpmc_ben1 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs5 1 O
vin2b_clk1
vin1b_clk1		 4 I
gpmc_a3 5 O
vin2b_fld1
vin1b_fld1		 6 I
timer1 7 IO
dma_evt4 9 I
gpio2_27
gpmc_a22		 14 IO
Driver off 15 I
P7 gpmc_clk gpmc_clk 0 IO PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs7 1 O
clkout1 2 O
gpmc_wait1 3 I
vin2a_hsync0
vin1a_hsync0		 4 I
vin2a_de0
vin1a_de0		 5 I
vin2b_clk1
vin1b_clk1		 6 I
timer4 7 IO
i2c3_scl 8 IO
dma_evt1 9 I
gpio2_22
gpmc_a20		 14 IO
Driver off 15 I
T1 gpmc_cs0 gpmc_cs0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_19 14 IO
Driver off 15 I
H6 gpmc_cs1 gpmc_cs1 0 O PU PU 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_cmd 1 IO
gpmc_a22 2 O
vin2a_de0
vin1a_de0		 4 I
vin2b_vsync1
vin1b_vsync1		 6 I
gpio2_18 14 IO
Driver off 15 I
P2 gpmc_cs2 gpmc_cs2 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs0 1 IO
gpio2_20
gpmc_a23
gpmc_a13		 14 IO
Driver off 15 I
P1 gpmc_cs3 gpmc_cs3 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs1 1 O
vin1a_clk0 2 I
vout3_clk No 3 O
gpmc_a1 5 O
gpio2_21
gpmc_a24
gpmc_a14		 14 IO
Driver off 15 I
M5 gpmc_oen_ren gpmc_oen_ren 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_24 14 IO
Driver off 15 I
N2 gpmc_wait0 gpmc_wait0 0 I PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_28
gpmc_a25
gpmc_a15		 14 IO
Driver off 15 I
M3 gpmc_wen gpmc_wen 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_25 14 IO
Driver off 15 I
AG16 hdmi1_clockx hdmi1_clockx No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AH16 hdmi1_clocky hdmi1_clocky No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AG17 hdmi1_data0x hdmi1_data0x No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AH17 hdmi1_data0y hdmi1_data0y No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AG18 hdmi1_data1x hdmi1_data1x No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AH18 hdmi1_data1y hdmi1_data1y No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AG19 hdmi1_data2x hdmi1_data2x No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
AH19 hdmi1_data2y hdmi1_data2y No 0 O 1.8 vdda_hdmi NA HDMIPHY Pdy
C20 i2c1_scl i2c1_scl 0 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
Driver off 15 I
C21 i2c1_sda i2c1_sda 0 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
Driver off 15 I
F17 i2c2_scl i2c2_scl 0 IO 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
hdmi1_ddc_sda No 1 IO
Driver off 15 I
C25 i2c2_sda i2c2_sda 0 IO 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
hdmi1_ddc_scl No 1 IO
Driver off 15 I
AH15 ljcb_clkn ljcb_clkn 0 IO 1.8 vdda_pcie NA LJCB NA
AG15 ljcb_clkp ljcb_clkp 0 IO 1.8 vdda_pcie NA LJCB NA
B14 mcasp1_aclkr mcasp1_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr2 1 IO
vout2_d0 No 6 O
vin2a_d0
vin1a_d0		 8 I
i2c4_sda 10 IO
gpio5_0 14 IO
Driver off 15 I
C14 mcasp1_aclkx mcasp1_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_fld0 7 I
i2c3_sda 10 IO
pr2_mdio_mdclk 11 O
pr2_pru1_gpi7 12 I
pr2_pru1_gpo7 13 O
gpio7_31 14 IO
Driver off 15 I
G12 mcasp1_axr0 mcasp1_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 3 I
vin1a_vsync0 7 I
i2c5_sda 10 IO
pr2_mii0_rxer 11 I
pr2_pru1_gpi8 12 I
pr2_pru1_gpo8 13 O
gpio5_2 14 IO
Driver off 15 I
F12 mcasp1_axr1 mcasp1_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 3 O
vin1a_hsync0 7 I
i2c5_scl 10 IO
pr2_mii_mt0_clk 11 I
pr2_pru1_gpi9 12 I
pr2_pru1_gpo9 13 O
gpio5_3 14 IO
Driver off 15 I
G13 mcasp1_axr2 mcasp1_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr2 1 IO
uart6_ctsn 3 I
vout2_d2 No 6 O
vin2a_d2
vin1a_d2		 8 I
gpio5_4 14 IO
Driver off 15 I
J11 mcasp1_axr3 mcasp1_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr3 1 IO
uart6_rtsn 3 O
vout2_d3 No 6 O
vin2a_d3
vin1a_d3		 8 I
gpio5_5 14 IO
Driver off 15 I
E12 mcasp1_axr4 mcasp1_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_axr2 1 IO
vout2_d4 No 6 O
vin2a_d4
vin1a_d4		 8 I
gpio5_6 14 IO
Driver off 15 I
F13 mcasp1_axr5 mcasp1_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_axr3 1 IO
vout2_d5 No 6 O
vin2a_d5
vin1a_d5		 8 I
gpio5_7 14 IO
Driver off 15 I
C12 mcasp1_axr6 mcasp1_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp5_axr2 1 IO
vout2_d6 No 6 O
vin2a_d6
vin1a_d6		 8 I
gpio5_8 14 IO
Driver off 15 I
D12 mcasp1_axr7 mcasp1_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp5_axr3 1 IO
vout2_d7 No 6 O
vin2a_d7
vin1a_d7		 8 I
timer4 10 IO
gpio5_9 14 IO
Driver off 15 I
B12 mcasp1_axr8 mcasp1_axr8 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr0 1 IO
spi3_sclk 3 IO
vin1a_d15 7 I
timer5 10 IO
pr2_mii0_txen 11 O
pr2_pru1_gpi10 12 I
pr2_pru1_gpo10 13 O
gpio5_10 14 IO
Driver off 15 I
A11 mcasp1_axr9 mcasp1_axr9 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr1 1 IO
spi3_d1 3 IO
vin1a_d14 7 I
timer6 10 IO
pr2_mii0_txd3 11 O
pr2_pru1_gpi11 12 I
pr2_pru1_gpo11 13 O
gpio5_11 14 IO
Driver off 15 I
B13 mcasp1_axr10 mcasp1_axr10 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_aclkx 1 IO
mcasp6_aclkr 2 IO
spi3_d0 3 IO
vin1a_d13 7 I
timer7 10 IO
pr2_mii0_txd2 11 O
pr2_pru1_gpi12 12 I
pr2_pru1_gpo12 13 O
gpio5_12 14 IO
Driver off 15 I
A12 mcasp1_axr11 mcasp1_axr11 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_fsx 1 IO
mcasp6_fsr 2 IO
spi3_cs0 3 IO
vin1a_d12 7 I
timer8 10 IO
pr2_mii0_txd1 11 O
pr2_pru1_gpi13 12 I
pr2_pru1_gpo13 13 O
gpio4_17 14 IO
Driver off 15 I
E14 mcasp1_axr12 mcasp1_axr12 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr0 1 IO
spi3_cs1 3 IO
vin1a_d11 7 I
timer9 10 IO
pr2_mii0_txd0 11 O
pr2_pru1_gpi14 12 I
pr2_pru1_gpo14 13 O
gpio4_18 14 IO
Driver off 15 I
A13 mcasp1_axr13 mcasp1_axr13 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr1 1 IO
vin1a_d10 7 I
timer10 10 IO
pr2_mii_mr0_clk 11 I
pr2_pru1_gpi15 12 I
pr2_pru1_gpo15 13 O
gpio6_4 14 IO
Driver off 15 I
G14 mcasp1_axr14 mcasp1_axr14 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_aclkx 1 IO
mcasp7_aclkr 2 IO
vin1a_d9 7 I
timer11 10 IO
pr2_mii0_rxdv 11 I
pr2_pru1_gpi16 12 I
pr2_pru1_gpo16 13 O
gpio6_5 14 IO
Driver off 15 I
F14 mcasp1_axr15 mcasp1_axr15 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_fsx 1 IO
mcasp7_fsr 2 IO
vin1a_d8 7 I
timer12 10 IO
pr2_mii0_rxd3 11 I
pr2_pru0_gpi20 12 I
pr2_pru0_gpo20 13 O
gpio6_6 14 IO
Driver off 15 I
J14 mcasp1_fsr mcasp1_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr3 1 IO
vout2_d1 No 6 O
vin2a_d1
vin1a_d1		 8 I
i2c4_scl 10 IO
gpio5_1 14 IO
Driver off 15 I
D14 mcasp1_fsx mcasp1_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_de0 7 I
i2c3_scl 10 IO
pr2_mdio_data 11 IO
gpio7_30 14 IO
Driver off 15 I
E15 mcasp2_aclkr mcasp2_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr2 1 IO
vout2_d8 No 6 O
vin2a_d8
vin1a_d8		 8 I
Driver off 15 I
A19 mcasp2_aclkx mcasp2_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_d7 7 I
pr2_mii0_rxd2 11 I
pr2_pru0_gpi18 12 I
pr2_pru0_gpo18 13 O
Driver off 15 I
B15 mcasp2_axr0 mcasp2_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vout2_d10 No 6 O
vin2a_d10
vin1a_d10		 8 I
Driver off 15 I
A15 mcasp2_axr1 mcasp2_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vout2_d11 No 6 O
vin2a_d11
vin1a_d11		 8 I
Driver off 15 I
C15 mcasp2_axr2 mcasp2_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_axr2 1 IO
vin1a_d5 7 I
pr2_mii0_rxd0 11 I
pr2_pru0_gpi16 12 I
pr2_pru0_gpo16 13 O
gpio6_8 14 IO
Driver off 15 I
A16 mcasp2_axr3 mcasp2_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_axr3 1 IO
vin1a_d4 7 I
pr2_mii0_rxlink 11 I
pr2_pru0_gpi17 12 I
pr2_pru0_gpo17 13 O
gpio6_9 14 IO
Driver off 15 I
D15 mcasp2_axr4 mcasp2_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr0 1 IO
vout2_d12 No 6 O
vin2a_d12
vin1a_d12		 8 I
gpio1_4 14 IO
Driver off 15 I
B16 mcasp2_axr5 mcasp2_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr1 1 IO
vout2_d13 No 6 O
vin2a_d13
vin1a_d13		 8 I
gpio6_7 14 IO
Driver off 15 I
B17 mcasp2_axr6 mcasp2_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_aclkx 1 IO
mcasp8_aclkr 2 IO
vout2_d14 No 6 O
vin2a_d14
vin1a_d14		 8 I
gpio2_29 14 IO
Driver off 15 I
A17 mcasp2_axr7 mcasp2_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_fsx 1 IO
mcasp8_fsr 2 IO
vout2_d15 No 6 O
vin2a_d15
vin1a_d15		 8 I
gpio1_5 14 IO
Driver off 15 I
A20 mcasp2_fsr mcasp2_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr3 1 IO
vout2_d9 No 6 O
vin2a_d9
vin1a_d9		 8 I
Driver off 15 I
A18 mcasp2_fsx mcasp2_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_d6 7 I
pr2_mii0_rxd1 11 I
pr2_pru0_gpi19 12 I
pr2_pru0_gpo19 13 O
Driver off 15 I
B18 mcasp3_aclkx mcasp3_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_aclkr 1 IO
mcasp2_axr12 2 IO
uart7_rxd 3 I
vin1a_d3 7 I
pr2_mii0_crs 11 I
pr2_pru0_gpi12 12 I
pr2_pru0_gpo12 13 O
gpio5_13 14 IO
Driver off 15 I
B19 mcasp3_axr0 mcasp3_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr14 2 IO
uart7_ctsn 3 I
uart5_rxd 4 I
vin1a_d1 7 I
pr2_mii1_rxer 11 I
pr2_pru0_gpi14 12 I
pr2_pru0_gpo14 13 O
Driver off 15 I
C17 mcasp3_axr1 mcasp3_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr15 2 IO
uart7_rtsn 3 O
uart5_txd 4 O
vin1a_d0 7 I
vin1a_fld0 9 I
pr2_mii1_rxlink 11 I
pr2_pru0_gpi15 12 I
pr2_pru0_gpo15 13 O
Driver off 15 I
F15 mcasp3_fsx mcasp3_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_fsr 1 IO
mcasp2_axr13 2 IO
uart7_txd 3 O
vin1a_d2 7 I
pr2_mii0_col 11 I
pr2_pru0_gpi13 12 I
pr2_pru0_gpo13 13 O
gpio5_14 14 IO
Driver off 15 I
C18 mcasp4_aclkx mcasp4_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_aclkr 1 IO
spi3_sclk 2 IO
uart8_rxd 3 I
i2c4_sda 4 IO
vout2_d16 No 6 O
vin2a_d16
vin1a_d16		 8 I
vin1a_d15 9 I
Driver off 15 I
G16 mcasp4_axr0 mcasp4_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
spi3_d0 2 IO
uart8_ctsn 3 I
uart4_rxd 4 I
vout2_d18 No 6 O
vin2a_d18
vin1a_d18		 8 I
vin1a_d13 9 I
Driver off 15 I
D17 mcasp4_axr1 mcasp4_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
spi3_cs0 2 IO
uart8_rtsn 3 O
uart4_txd 4 O
vout2_d19 No 6 O
vin2a_d19
vin1a_d19		 8 I
vin1a_d12 9 I
pr2_pru1_gpi0 12 I
pr2_pru1_gpo0 13 O
Driver off 15 I
A21 mcasp4_fsx mcasp4_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_fsr 1 IO
spi3_d1 2 IO
uart8_txd 3 O
i2c4_scl 4 IO
vout2_d17 No 6 O
vin2a_d17
vin1a_d17		 8 I
vin1a_d14 9 I
Driver off 15 I
AA3 mcasp5_aclkx mcasp5_aclkx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mcasp5_aclkr 1 IO
spi4_sclk 2 IO
uart9_rxd 3 I
i2c5_sda 4 IO
vout2_d20 No 6 O
vin2a_d20
vin1a_d20		 8 I
vin1a_d11 9 I
pr2_pru1_gpi1 12 I
pr2_pru1_gpo1 13 O
Driver off 15 I
AB3 mcasp5_axr0 mcasp5_axr0 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_d0 2 IO
uart9_ctsn 3 I
uart3_rxd 4 I
vout2_d22 No 6 O
vin2a_d22
vin1a_d22		 8 I
vin1a_d9 9 I
pr2_mdio_mdclk 11 O
pr2_pru1_gpi3 12 I
pr2_pru1_gpo3 13 O
Driver off 15 I
AA4 mcasp5_axr1 mcasp5_axr1 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_cs0 2 IO
uart9_rtsn 3 O
uart3_txd 4 O
vout2_d23 No 6 O
vin2a_d23
vin1a_d23		 8 I
vin1a_d8 9 I
pr2_mdio_data 11 IO
pr2_pru1_gpi4 12 I
pr2_pru1_gpo4 13 O
Driver off 15 I
AB9 mcasp5_fsx mcasp5_fsx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mcasp5_fsr 1 IO
spi4_d1 2 IO
uart9_txd 3 O
i2c5_scl 4 IO
vout2_d21 No 6 O
vin2a_d21
vin1a_d21		 8 I
vin1a_d10 9 I
pr2_pru1_gpi2 12 I
pr2_pru1_gpo2 13 O
Driver off 15 I
U4 mdio_d mdio_d 0 IO PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
mii0_txer 3 O
vin2a_d0 4 I
vin1b_d0 5 I
pr1_mii0_rxlink 11 I
pr2_pru1_gpi1 12 I
pr2_pru1_gpo1 13 O
gpio5_16 14 IO
Driver off 15 I
V1 mdio_mclk mdio_mclk 0 O PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
mii0_col 3 I
vin2a_clk0 4 I
vin1b_clk1 5 I
pr1_mii0_col 11 I
pr2_pru1_gpi0 12 I
pr2_pru1_gpo0 13 O
gpio5_15 14 IO
Driver off 15 I
AB2 mlbp_clk_n mlbp_clk_n 0 I vdds_mlbp No BMLB18 NA
AB1 mlbp_clk_p mlbp_clk_p 0 I vdds_mlbp No BMLB18 NA
AA2 mlbp_dat_n mlbp_dat_n 0 IO OFF OFF vdds_mlbp No BMLB18 NA
AA1 mlbp_dat_p mlbp_dat_p 0 IO OFF OFF vdds_mlbp No BMLB18 NA
AC2 mlbp_sig_n mlbp_sig_n 0 IO OFF OFF vdds_mlbp No BMLB18 NA
AC1 mlbp_sig_p mlbp_sig_p 0 IO OFF OFF vdds_mlbp No BMLB18 NA
W6 mmc1_clk mmc1_clk 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_21 14 IO
Driver off 15 I
Y6 mmc1_cmd mmc1_cmd 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_22 14 IO
Driver off 15 I
AA6 mmc1_dat0 mmc1_dat0 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_23 14 IO
Driver off 15 I
Y4 mmc1_dat1 mmc1_dat1 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_24 14 IO
Driver off 15 I
AA5 mmc1_dat2 mmc1_dat2 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_25 14 IO
Driver off 15 I
Y3 mmc1_dat3 mmc1_dat3 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_26 14 IO
Driver off 15 I
W7 mmc1_sdcd mmc1_sdcd 0 I PU PU 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 3 I
i2c4_sda 4 IO
gpio6_27 14 IO
Driver off 15 I
Y9 mmc1_sdwp mmc1_sdwp 0 I PD PD 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 3 O
i2c4_scl 4 IO
gpio6_28 14 IO
Driver off 15 I
AD4 mmc3_clk mmc3_clk 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
vin2b_d7 4 I
vin1a_d7 9 I
ehrpwm2_tripzone_input 10 IO
pr2_mii1_txd3 11 O
pr2_pru0_gpi2 12 I
pr2_pru0_gpo2 13 O
gpio6_29 14 IO
Driver off 15 I
AC4 mmc3_cmd mmc3_cmd 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_sclk 1 IO
vin2b_d6 4 I
vin1a_d6 9 I
eCAP2_in_PWM2_out 10 IO
pr2_mii1_txd2 11 O
pr2_pru0_gpi3 12 I
pr2_pru0_gpo3 13 O
gpio6_30 14 IO
Driver off 15 I
AC7 mmc3_dat0 mmc3_dat0 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_d1 1 IO
uart5_rxd 2 I
vin2b_d5 4 I
vin1a_d5 9 I
eQEP3A_in 10 I
pr2_mii1_txd1 11 O
pr2_pru0_gpi4 12 I
pr2_pru0_gpo4 13 O
gpio6_31 14 IO
Driver off 15 I
AC6 mmc3_dat1 mmc3_dat1 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_d0 1 IO
uart5_txd 2 O
vin2b_d4 4 I
vin1a_d4 9 I
eQEP3B_in 10 I
pr2_mii1_txd0 11 O
pr2_pru0_gpi5 12 I
pr2_pru0_gpo5 13 O
gpio7_0 14 IO
Driver off 15 I
AC9 mmc3_dat2 mmc3_dat2 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_cs0 1 IO
uart5_ctsn 2 I
vin2b_d3 4 I
vin1a_d3 9 I
eQEP3_index 10 IO
pr2_mii_mr1_clk 11 I
pr2_pru0_gpi6 12 I
pr2_pru0_gpo6 13 O
gpio7_1 14 IO
Driver off 15 I
AC3 mmc3_dat3 mmc3_dat3 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_cs1 1 IO
uart5_rtsn 2 O
vin2b_d2 4 I
vin1a_d2 9 I
eQEP3_strobe 10 IO
pr2_mii1_rxdv 11 I
pr2_pru0_gpi7 12 I
pr2_pru0_gpo7 13 O
gpio7_2 14 IO
Driver off 15 I
AC8 mmc3_dat4 mmc3_dat4 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_sclk 1 IO
uart10_rxd 2 I
vin2b_d1 4 I
vin1a_d1 9 I
ehrpwm3A 10 O
pr2_mii1_rxd3 11 I
pr2_pru0_gpi8 12 I
pr2_pru0_gpo8 13 O
gpio1_22 14 IO
Driver off 15 I
AD6 mmc3_dat5 mmc3_dat5 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_d1 1 IO
uart10_txd 2 O
vin2b_d0 4 I
vin1a_d0 9 I
ehrpwm3B 10 O
pr2_mii1_rxd2 11 I
pr2_pru0_gpi9 12 I
pr2_pru0_gpo9 13 O
gpio1_23 14 IO
Driver off 15 I
AB8 mmc3_dat6 mmc3_dat6 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_d0 1 IO
uart10_ctsn 2 I
vin2b_de1 4 I
vin1a_hsync0 9 I
ehrpwm3_tripzone_input 10 IO
pr2_mii1_rxd1 11 I
pr2_pru0_gpi10 12 I
pr2_pru0_gpo10 13 O
gpio1_24 14 IO
Driver off 15 I
AB5 mmc3_dat7 mmc3_dat7 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_cs0 1 IO
uart10_rtsn 2 O
vin2b_clk1 4 I
vin1a_vsync0 9 I
eCAP3_in_PWM3_out 10 IO
pr2_mii1_rxd0 11 I
pr2_pru0_gpi11 12 I
pr2_pru0_gpo11 13 O
gpio1_25 14 IO
Driver off 15 I
D21 nmin_dsp nmin_dsp 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
Y11 on_off on_off 0 O PU drive 1 (OFF) 1.8/3.3 vddshv5 Yes BC1833IHHV PU/PD
AG13 pcie_rxn0 pcie_rxn0 0 I OFF OFF 1.8 vdda_pcie0 NA SERDES NA
AH13 pcie_rxp0 pcie_rxp0 0 I OFF OFF 1.8 vdda_pcie0 NA SERDES NA
AG14 pcie_txn0 pcie_txn0 0 O 1.8 vdda_pcie0 NA SERDES NA
AH14 pcie_txp0 pcie_txp0 0 O 1.8 vdda_pcie0 NA SERDES NA
F22 porz porz 0 I 1.8/3.3 vddshv3 Yes IHHV1833 PU/PD
E23 resetn resetn 0 I PU PU 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
U5 rgmii0_rxc rgmii0_rxc 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_txen 2 O
mii0_txclk 3 I
vin2a_d5 4 I
vin1b_d5 5 I
pr1_mii_mt0_clk 11 I
pr2_pru1_gpi11 12 I
pr2_pru1_gpo11 13 O
gpio5_26 14 IO
Driver off 15 I
V5 rgmii0_rxctl rgmii0_rxctl 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_txd1 2 O
mii0_txd3 3 O
vin2a_d6 4 I
vin1b_d6 5 I
pr1_mii0_txd3 11 O
pr2_pru1_gpi12 12 I
pr2_pru1_gpo12 13 O
gpio5_27 14 IO
Driver off 15 I
W2 rgmii0_rxd0 rgmii0_rxd0 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_txd0 1 O
mii0_txd0 3 O
vin2a_fld0 4 I
vin1b_fld1 5 I
pr1_mii0_txd0 11 O
pr2_pru1_gpi16 12 I
pr2_pru1_gpo16 13 O
gpio5_31 14 IO
Driver off 15 I
Y2 rgmii0_rxd1 rgmii0_rxd1 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_txd1 1 O
mii0_txd1 3 O
vin2a_d9 4 I
pr1_mii0_txd1 11 O
pr2_pru1_gpi15 12 I
pr2_pru1_gpo15 13 O
gpio5_30 14 IO
Driver off 15 I
V3 rgmii0_rxd2 rgmii0_rxd2 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_txen 1 O
mii0_txen 3 O
vin2a_d8 4 I
pr1_mii0_txen 11 O
pr2_pru1_gpi14 12 I
pr2_pru1_gpo14 13 O
gpio5_29 14 IO
Driver off 15 I
V4 rgmii0_rxd3 rgmii0_rxd3 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_txd0 2 O
mii0_txd2 3 O
vin2a_d7 4 I
vin1b_d7 5 I
pr1_mii0_txd2 11 O
pr2_pru1_gpi13 12 I
pr2_pru1_gpo13 13 O
gpio5_28 14 IO
Driver off 15 I
W9 rgmii0_txc rgmii0_txc 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
rmii1_rxd1 2 I
mii0_rxd3 3 I
vin2a_d3 4 I
vin1b_d3 5 I
spi3_d0 7 IO
spi4_cs2 8 IO
pr1_mii0_rxd3 11 I
pr2_pru1_gpi5 12 I
pr2_pru1_gpo5 13 O
gpio5_20 14 IO
Driver off 15 I
V9 rgmii0_txctl rgmii0_txctl 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
rmii1_rxd0 2 I
mii0_rxd2 3 I
vin2a_d4 4 I
vin1b_d4 5 I
spi3_cs0 7 IO
spi4_cs3 8 IO
pr1_mii0_rxd2 11 I
pr2_pru1_gpi6 12 I
pr2_pru1_gpo6 13 O
gpio5_21 14 IO
Driver off 15 I
U6 rgmii0_txd0 rgmii0_txd0 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd0 1 I
mii0_rxd0 3 I
vin2a_d10 4 I
spi4_cs0 7 IO
uart4_rtsn 8 O
pr1_mii0_rxd0 11 I
pr2_pru1_gpi10 12 I
pr2_pru1_gpo10 13 O
gpio5_25 14 IO
Driver off 15 I
V6 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd1 1 I
mii0_rxd1 3 I
vin2a_vsync0 4 I
vin1b_vsync1 5 I
spi4_d0 7 IO
uart4_ctsn 8 IO
pr1_mii0_rxd1 11 I
pr2_pru1_gpi9 12 I
pr2_pru1_gpo9 13 O
gpio5_24 14 IO
Driver off 15 I
U7 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxer 1 I
mii0_rxer 3 I
vin2a_hsync0 4 I
vin1b_hsync1 5 I
spi4_d1 7 IO
uart4_txd 8 O
pr1_mii0_rxer 11 I
pr2_pru1_gpi8 12 I
pr2_pru1_gpo8 13 O
gpio5_23 14 IO
Driver off 15 I
V7 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_crs 1 I
mii0_crs 3 I
vin2a_de0 4 I
vin1b_de1 5 I
spi4_sclk 7 IO
uart4_rxd 8 I
pr1_mii0_crs 11 I
pr2_pru1_gpi7 12 I
pr2_pru1_gpo7 13 O
gpio5_22 14 IO
Driver off 15 I
U3 RMII_MHZ_50_CLK RMII_MHZ_50_CLK 0 IO PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
vin2a_d11 4 I
pr2_pru1_gpi2 12 I
pr2_pru1_gpo2 13 O
gpio5_17 14 IO
Driver off 15 I
F23 rstoutn rstoutn 0 O PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
E18 rtck rtck 0 O PU OFF 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_29 14 IO
AF14 rtc_iso rtc_iso 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
AE14 rtc_osc_xi_clkin32 rtc_osc_xi_clkin32 0 I 1.8 vdda_rtc No LVCMOS OSC NA
AD14 rtc_osc_xo rtc_osc_xo 0 O 1.8 vdda_rtc No LVCMOS OSC NA
AB17 rtc_porz rtc_porz 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
AH9 sata1_rxn0 sata1_rxn0 0 I OFF OFF 1.8 vdda_sata NA SATAPHY NA
AG9 sata1_rxp0 sata1_rxp0 0 I OFF OFF 1.8 vdda_sata NA SATAPHY NA
AG10 sata1_txn0 sata1_txn0 0 O 1.8 vdda_sata NA SATAPHY NA
AH10 sata1_txp0 sata1_txp0 0 O 1.8 vdda_sata NA SATAPHY NA
A24 spi1_cs0 spi1_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_10 14 IO
Driver off 15 I
A22 spi1_cs1 spi1_cs1 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
sata1_led 2 O
spi2_cs1 3 IO
gpio7_11 14 IO
Driver off 15 I
B21 spi1_cs2 spi1_cs2 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart4_rxd 1 I
mmc3_sdcd 2 I
spi2_cs2 3 IO
dcan2_tx 4 IO
mdio_mclk 5 O
hdmi1_hpd No 6 IO
gpio7_12 14 IO
Driver off 15 I
B20 spi1_cs3 spi1_cs3 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart4_txd 1 O
mmc3_sdwp 2 I
spi2_cs3 3 IO
dcan2_rx 4 IO
mdio_d 5 IO
hdmi1_cec No 6 IO
gpio7_13 14 IO
Driver off 15 I
B25 spi1_d0 spi1_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_9 14 IO
Driver off 15 I
F16 spi1_d1 spi1_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_8 14 IO
Driver off 15 I
A25 spi1_sclk spi1_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_7 14 IO
Driver off 15 I
B24 spi2_cs0 spi2_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
uart5_txd 2 O
gpio7_17 14 IO
Driver off 15 I
G17 spi2_d0 spi2_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
uart5_rxd 2 I
gpio7_16 14 IO
Driver off 15 I
B22 spi2_d1 spi2_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 1 O
gpio7_15 14 IO
Driver off 15 I
A26 spi2_sclk spi2_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_rxd 1 I
gpio7_14 14 IO
Driver off 15 I
E20 tclk tclk 0 I PU PU 0 1.8/3.3 vddshv3 Yes IQ1833 PU/PD
D23 tdi tdi 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_27 14 I
F19 tdo tdo 0 O PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_28 14 IO
F18 tms tms 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
D20 trstn trstn 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
E25 uart1_ctsn uart1_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart9_rxd 2 I
mmc4_clk 3 IO
gpio7_24 14 IO
Driver off 15 I
C27 uart1_rtsn uart1_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart9_txd 2 O
mmc4_cmd 3 IO
gpio7_25 14 IO
Driver off 15 I
B27 uart1_rxd uart1_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc4_sdcd 3 I
gpio7_22 14 IO
Driver off 15 I
C26 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc4_sdwp 3 I
gpio7_23 14 IO
Driver off 15 I
D27 uart2_ctsn uart2_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_rxd 2 I
mmc4_dat2 3 IO
uart10_rxd 4 I
uart1_dtrn 5 O
gpio1_16 14 IO
Driver off 15 I
C28 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 1 O
uart3_irtx 2 O
mmc4_dat3 3 IO
uart10_txd 4 O
uart1_rin 5 I
gpio1_17 14 IO
Driver off 15 I
D28 uart2_rxd uart2_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
uart3_rctx 2 O
mmc4_dat0 3 IO
uart2_rxd 4 I
uart1_dcdn 5 I
gpio7_26 14 IO
Driver off 15 I
D26 uart2_txd uart2_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
uart3_sd 2 O
mmc4_dat1 3 IO
uart2_txd 4 O
uart1_dsrn 5 I
gpio7_27 14 IO
Driver off 15 I
V2 uart3_rxd uart3_rxd 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_crs 2 I
mii0_rxdv 3 I
vin2a_d1 4 I
vin1b_d1 5 I
spi3_sclk 7 IO
pr1_mii0_rxdv 11 I
pr2_pru1_gpi3 12 I
pr2_pru1_gpo3 13 O
gpio5_18 14 IO
Driver off 15 I
Y1 uart3_txd uart3_txd 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_rxer 2 I
mii0_rxclk 3 I
vin2a_d2 4 I
vin1b_d2 5 I
spi3_d1 7 IO
spi4_cs1 8 IO
pr1_mii_mr0_clk 11 I
pr2_pru1_gpi4 12 I
pr2_pru1_gpo4 13 O
gpio5_19 14 IO
Driver off 15 I
AC12 usb1_dm usb1_dm 0 IO OFF OFF 3.3 vdda33v_usb1 NA USBPHY NA
AD12 usb1_dp usb1_dp 0 IO OFF OFF 3.3 vdda33v_usb1 NA USBPHY NA
AB10 usb1_drvvbus usb1_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
timer16 7 IO
gpio6_12 14 IO
Driver off 15 I
AF11 usb2_dm usb2_dm 0 IO 3.3 vdda33v_usb2 No USBPHY NA
AE11 usb2_dp usb2_dp 0 IO 3.3 vdda33v_usb2 No USBPHY NA
AC10 usb2_drvvbus usb2_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
timer15 7 IO
gpio6_13 14 IO
Driver off 15 I
AF12 usb_rxn0 usb_rxn0 0 I OFF OFF 1.8 vdda_usb1 NA SERDES NA
pcie_rxn1 1 I
AE12 usb_rxp0 usb_rxp0 0 I OFF OFF 1.8 vdda_usb1 NA SERDES NA
pcie_rxp1 1 I
AC11 usb_txn0 usb_txn0 0 O 1.8 vdda_usb1 NA SERDES NA
pcie_txn1 1 O
AD11 usb_txp0 usb_txp0 0 O 1.8 vdda_usb1 NA SERDES NA
pcie_txp1 1 O
H13, H14, J17, J18, L7, L8, N10, N13, P11, P12, P13, R11, R16, R19, T13, T16, T19, U13, U16, U8, U9, V16, V8 vdd vdd PWR
AA12 vdda33v_usb1 vdda33v_usb1 PWR
Y12 vdda33v_usb2 vdda33v_usb2 PWR
P14 vdda_core_gmac vdda_core_gmac PWR
W12 vdda_csi vdda_csi PWR
R17 vdda_ddr vdda_ddr PWR
N11 vdda_debug vdda_debug PWR
N12 vdda_dsp_iva vdda_dsp_iva PWR
R14 vdda_gpu vdda_gpu PWR
Y17 vdda_hdmi vdda_hdmi PWR
N16 vdda_mpu_abe vdda_mpu_abe PWR
AD16, AE16 vdda_osc vdda_osc PWR
AA17 vdda_pcie vdda_pcie PWR
AA16 vdda_pcie0 vdda_pcie0 PWR
M14 vdda_per vdda_per PWR
P15 vdda_pll_spare vdda_pll_spare PWR
AB13 vdda_rtc vdda_rtc PWR
V13 vdda_sata vdda_sata PWR
AA13 vdda_usb1 vdda_usb1 PWR
AB12 vdda_usb2 vdda_usb2 PWR
W14 vdda_usb3 vdda_usb3 PWR
P16 vdda_video vdda_video PWR
G18, H17, M8, M9, N8, P8, R8, T8, V21, V22, W17, W18 vdds18v vdds18v PWR
AA18, AA19, N21, P20, P21, W21, Y21 vdds18v_ddr1 vdds18v_ddr1 PWR
E3, E5, G4, G5, H8, H9 vddshv1 vddshv1 PWR
B6, D10, E10, H10, H11 vddshv2 vddshv2 PWR
B23, D16, D22, E16, E22, G15, H15, H16, H18, H19 vddshv3 vddshv3 PWR
C24 vddshv4 vddshv4 PWR
V12 vddshv5 vddshv5 PWR
AD5, AD7, AE7, AF5 vddshv6 vddshv6 PWR
AB6, AB7 vddshv7 vddshv7 PWR
W8, Y8 vddshv8 vddshv8 PWR
U10, W4, W5 vddshv9 vddshv9 PWR
N4, N5, P10, R10, R7, T4, T5 vddshv10 vddshv10 PWR
J8, K8 vddshv11 vddshv11 PWR
AA21, AA22, AB21, AB22, AB24, AB25, AC22, AD26, AG20, AG28, AH27, T24, T25, W16, W27 vdds_ddr1 vdds_ddr1 PWR
AA7, Y7 vdds_mlbp vdds_mlbp PWR
K10, K11, L10, L11, M10, M11 vdd_dsp vdd_dsp PWR
U11, U12, V10, V11, V14, W10, W11, W13 vdd_gpu vdd_gpu PWR
J13, K12, K13, L12, M12, M13 vdd_iva vdd_iva PWR
K17, K18, L15, L16, L17, L18, L19, M15, M16, M17, M18, N17, N18, P17, P18, R18 vdd_mpu vdd_mpu PWR
AB15 vdd_rtc vdd_rtc PWR
E1 vin2a_clk0 vin2a_clk0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_fld No 4 O
emu5 5 O
kbd_row0 9 I
eQEP1A_in 10 I
pr1_edio_data_in0 12 I
pr1_edio_data_out0 13 O
gpio3_28
gpmc_a27
gpmc_a17		 14 IO
Driver off 15 I
F2 vin2a_d0 vin2a_d0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d23 No 4 O
emu10 5 O
uart9_ctsn 7 I
spi4_d0 8 IO
kbd_row4 9 I
ehrpwm1B 10 O
pr1_uart0_rxd 11 I
pr1_edio_data_in5 12 I
pr1_edio_data_out5 13 O
gpio4_1 14 IO
Driver off 15 I
F3 vin2a_d1 vin2a_d1 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d22 No 4 O
emu11 5 O
uart9_rtsn 7 O
spi4_cs0 8 IO
kbd_row5 9 I
ehrpwm1_tripzone_input 10 IO
pr1_uart0_txd 11 O
pr1_edio_data_in6 12 I
pr1_edio_data_out6 13 O
gpio4_2 14 IO
Driver off 15 I
D1 vin2a_d2 vin2a_d2 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d21 No 4 O
emu12 5 O
uart10_rxd 8 I
kbd_row6 9 I
eCAP1_in_PWM1_out 10 IO
pr1_ecap0_ecap_capin_apwm_o 11 IO
pr1_edio_data_in7 12 I
pr1_edio_data_out7 13 O
gpio4_3 14 IO
Driver off 15 I
E2 vin2a_d3 vin2a_d3 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d20 No 4 O
emu13 5 O
uart10_txd 8 O
kbd_col0 9 O
ehrpwm1_synci 10 I
pr1_edc_latch0_in 11 I
pr1_pru1_gpi0 12 I
pr1_pru1_gpo0 13 O
gpio4_4 14 IO
Driver off 15 I
D2 vin2a_d4 vin2a_d4 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d19 No 4 O
emu14 5 O
uart10_ctsn 8 I
kbd_col1 9 O
ehrpwm1_synco 10 O
pr1_edc_sync0_out 11 O
pr1_pru1_gpi1 12 I
pr1_pru1_gpo1 13 O
gpio4_5 14 IO
Driver off 15 I
F4 vin2a_d5 vin2a_d5 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d18 No 4 O
emu15 5 O
uart10_rtsn 8 O
kbd_col2 9 O
eQEP2A_in 10 I
pr1_edio_sof 11 O
pr1_pru1_gpi2 12 I
pr1_pru1_gpo2 13 O
gpio4_6 14 IO
Driver off 15 I
C1 vin2a_d6 vin2a_d6 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d17 No 4 O
emu16 5 O
mii1_rxd1 8 I
kbd_col3 9 O
eQEP2B_in 10 I
pr1_mii_mt1_clk 11 I
pr1_pru1_gpi3 12 I
pr1_pru1_gpo3 13 O
gpio4_7 14 IO
Driver off 15 I
E4 vin2a_d7 vin2a_d7 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d16 No 4 O
emu17 5 O
mii1_rxd2 8 I
kbd_col4 9 O
eQEP2_index 10 IO
pr1_mii1_txen 11 O
pr1_pru1_gpi4 12 I
pr1_pru1_gpo4 13 O
gpio4_8 14 IO
Driver off 15 I
F5 vin2a_d8 vin2a_d8 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d15 No 4 O
emu18 5 O
mii1_rxd3 8 I
kbd_col5 9 O
eQEP2_strobe 10 IO
pr1_mii1_txd3 11 O
pr1_pru1_gpi5 12 I
pr1_pru1_gpo5 13 O
gpio4_9
gpmc_a26		 14 IO
Driver off 15 I
E6 vin2a_d9 vin2a_d9 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d14 No 4 O
emu19 5 O
mii1_rxd0 8 I
kbd_col6 9 O
ehrpwm2A 10 O
pr1_mii1_txd2 11 O
pr1_pru1_gpi6 12 I
pr1_pru1_gpo6 13 O
gpio4_10
gpmc_a25		 14 IO
Driver off 15 I
D3 vin2a_d10 vin2a_d10 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
mdio_mclk 3 O
vout2_d13 No 4 O
kbd_col7 9 O
ehrpwm2B 10 O
pr1_mdio_mdclk 11 O
pr1_pru1_gpi7 12 I
pr1_pru1_gpo7 13 O
gpio4_11
gpmc_a24		 14 IO
Driver off 15 I
F6 vin2a_d11 vin2a_d11 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
mdio_d 3 IO
vout2_d12 No 4 O
kbd_row7 9 I
ehrpwm2_tripzone_input 10 IO
pr1_mdio_data 11 IO
pr1_pru1_gpi8 12 I
pr1_pru1_gpo8 13 O
gpio4_12
gpmc_a23		 14 IO
Driver off 15 I
D5 vin2a_d12 vin2a_d12 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txc 3 O
vout2_d11 No 4 O
mii1_rxclk 8 I
kbd_col8 9 O
eCAP2_in_PWM2_out 10 IO
pr1_mii1_txd1 11 O
pr1_pru1_gpi9 12 I
pr1_pru1_gpo9 13 O
gpio4_13 14 IO
Driver off 15 I
C2 vin2a_d13 vin2a_d13 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txctl 3 O
vout2_d10 No 4 O
mii1_rxdv 8 I
kbd_row8 9 I
eQEP3A_in 10 I
pr1_mii1_txd0 11 O
pr1_pru1_gpi10 12 I
pr1_pru1_gpo10 13 O
gpio4_14 14 IO
Driver off 15 I
C3 vin2a_d14 vin2a_d14 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd3 3 O
vout2_d9 No 4 O
mii1_txclk 8 I
eQEP3B_in 10 I
pr1_mii_mr1_clk 11 I
pr1_pru1_gpi11 12 I
pr1_pru1_gpo11 13 O
gpio4_15 14 IO
Driver off 15 I
C4 vin2a_d15 vin2a_d15 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd2 3 O
vout2_d8 No 4 O
mii1_txd0 8 O
eQEP3_index 10 IO
pr1_mii1_rxdv 11 I
pr1_pru1_gpi12 12 I
pr1_pru1_gpo12 13 O
gpio4_16 14 IO
Driver off 15 I
B2 vin2a_d16 vin2a_d16 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d7 2 I
rgmii1_txd1 3 O
vout2_d7 No 4 O
mii1_txd1 8 O
eQEP3_strobe 10 IO
pr1_mii1_rxd3 11 I
pr1_pru1_gpi13 12 I
pr1_pru1_gpo13 13 O
gpio4_24 14 IO
Driver off 15 I
D6 vin2a_d17 vin2a_d17 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d6 2 I
rgmii1_txd0 3 O
vout2_d6 No 4 O
mii1_txd2 8 O
ehrpwm3A 10 O
pr1_mii1_rxd2 11 I
pr1_pru1_gpi14 12 I
pr1_pru1_gpo14 13 O
gpio4_25 14 IO
Driver off 15 I
C5 vin2a_d18 vin2a_d18 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d5 2 I
rgmii1_rxc 3 I
vout2_d5 No 4 O
mii1_txd3 8 O
ehrpwm3B 10 O
pr1_mii1_rxd1 11 I
pr1_pru1_gpi15 12 I
pr1_pru1_gpo15 13 O
gpio4_26 14 IO
Driver off 15 I
A3 vin2a_d19 vin2a_d19 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d4 2 I
rgmii1_rxctl 3 I
vout2_d4 No 4 O
mii1_txer 8 O
ehrpwm3_tripzone_input 10 IO
pr1_mii1_rxd0 11 I
pr1_pru1_gpi16 12 I
pr1_pru1_gpo16 13 O
gpio4_27 14 IO
Driver off 15 I
B3 vin2a_d20 vin2a_d20 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d3 2 I
rgmii1_rxd3 3 I
vout2_d3 No 4 O
mii1_rxer 8 I
eCAP3_in_PWM3_out 10 IO
pr1_mii1_rxer 11 I
pr1_pru1_gpi17 12 I
pr1_pru1_gpo17 13 O
gpio4_28 14 IO
Driver off 15 I
B4 vin2a_d21 vin2a_d21 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d2 2 I
rgmii1_rxd2 3 I
vout2_d2 No 4 O
mii1_col 8 I
pr1_mii1_rxlink 11 I
pr1_pru1_gpi18 12 I
pr1_pru1_gpo18 13 O
gpio4_29 14 IO
Driver off 15 I
B5 vin2a_d22 vin2a_d22 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d1 2 I
rgmii1_rxd1 3 I
vout2_d1 No 4 O
mii1_crs 8 I
pr1_mii1_col 11 I
pr1_pru1_gpi19 12 I
pr1_pru1_gpo19 13 O
gpio4_30 14 IO
Driver off 15 I
A4 vin2a_d23 vin2a_d23 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d0 2 I
rgmii1_rxd0 3 I
vout2_d0 No 4 O
mii1_txen 8 O
pr1_mii1_crs 11 I
pr1_pru1_gpi20 12 I
pr1_pru1_gpo20 13 O
gpio4_31 14 IO
Driver off 15 I
G2 vin2a_de0 vin2a_de0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2a_fld0 1 I
vin2b_fld1 2 I
vin2b_de1 3 I
vout2_de No 4 O
emu6 5 O
kbd_row1 9 I
eQEP1B_in 10 I
pr1_edio_data_in1 12 I
pr1_edio_data_out1 13 O
gpio3_29 14 IO
Driver off 15 I
H7 vin2a_fld0 vin2a_fld0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_clk1 2 I
vout2_clk No 4 O
emu7 5 O
eQEP1_index 10 IO
pr1_edio_data_in2 12 I
pr1_edio_data_out2 13 O
gpio3_30
gpmc_a27
gpmc_a18		 14 IO
Driver off 15 I
G1 vin2a_hsync0 vin2a_hsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_hsync1 3 I
vout2_hsync No 4 O
emu8 5 O
uart9_rxd 7 I
spi4_sclk 8 IO
kbd_row2 9 I
eQEP1_strobe 10 IO
pr1_uart0_cts_n 11 I
pr1_edio_data_in3 12 I
pr1_edio_data_out3 13 O
gpio3_31
gpmc_a27		 14 IO
Driver off 15 I
G6 vin2a_vsync0 vin2a_vsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_vsync1 3 I
vout2_vsync No 4 O
emu9 5 O
uart9_txd 7 O
spi4_d1 8 IO
kbd_row3 9 I
ehrpwm1A 10 O
pr1_uart0_rts_n 11 O
pr1_edio_data_in4 12 I
pr1_edio_data_out4 13 O
gpio4_0 14 IO
Driver off 15 I
D11 vout1_clk vout1_clk No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_fld0
vin1a_fld0		 3 I
vin1a_fld0 4 I
spi3_cs0 8 IO
gpio4_19 14 IO
Driver off 15 I
F11 vout1_d0 vout1_d0 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart5_rxd 2 I
vin2a_d16
vin1a_d16		 3 I
vin1a_d16 4 I
spi3_cs2 8 IO
pr1_uart0_cts_n 10 I
pr2_pru1_gpi18 12 I
pr2_pru1_gpo18 13 O
gpio8_0 14 IO
Driver off 15 I
G10 vout1_d1 vout1_d1 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart5_txd 2 O
vin2a_d17
vin1a_d17		 3 I
vin1a_d17 4 I
pr1_uart0_rts_n 10 O
pr2_pru1_gpi19 12 I
pr2_pru1_gpo19 13 O
gpio8_1 14 IO
Driver off 15 I
F10 vout1_d2 vout1_d2 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu2 2 O
vin2a_d18
vin1a_d18		 3 I
vin1a_d18 4 I
obs0 5 O
obs16 6 O
obs_irq1 7 O
pr1_uart0_rxd 10 I
pr2_pru1_gpi20 12 I
pr2_pru1_gpo20 13 O
gpio8_2 14 IO
Driver off 15 I
G11 vout1_d3 vout1_d3 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu5 2 O
vin2a_d19
vin1a_d19		 3 I
vin1a_d19 4 I
obs1 5 O
obs17 6 O
obs_dmarq1 7 O
pr1_uart0_txd 10 O
pr2_pru0_gpi0 12 I
pr2_pru0_gpo0 13 O
gpio8_3 14 IO
Driver off 15 I
E9 vout1_d4 vout1_d4 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu6 2 O
vin2a_d20
vin1a_d20		 3 I
vin1a_d20 4 I
obs2 5 O
obs18 6 O
pr1_ecap0_ecap_capin_apwm_o 10 IO
pr2_pru0_gpi1 12 I
pr2_pru0_gpo1 13 O
gpio8_4 14 IO
Driver off 15 I
F9 vout1_d5 vout1_d5 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu7 2 O
vin2a_d21
vin1a_d21		 3 I
vin1a_d21 4 I
obs3 5 O
obs19 6 O
pr2_edc_latch0_in 10 I
pr2_pru0_gpi2 12 I
pr2_pru0_gpo2 13 O
gpio8_5 14 IO
Driver off 15 I
F8 vout1_d6 vout1_d6 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu8 2 O
vin2a_d22
vin1a_d22		 3 I
vin1a_d22 4 I
obs4 5 O
obs20 6 O
pr2_edc_latch1_in 10 I
pr2_pru0_gpi3 12 I
pr2_pru0_gpo3 13 O
gpio8_6 14 IO
Driver off 15 I
E7 vout1_d7 vout1_d7 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu9 2 O
vin2a_d23
vin1a_d23		 3 I
vin1a_d23 4 I
pr2_edc_sync0_out 10 O
pr2_pru0_gpi4 12 I
pr2_pru0_gpo4 13 O
gpio8_7 14 IO
Driver off 15 I
E8 vout1_d8 vout1_d8 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 2 I
vin2a_d8
vin1a_d8		 3 I
vin1a_d8 4 I
pr2_edc_sync1_out 10 O
pr2_pru0_gpi5 12 I
pr2_pru0_gpo5 13 O
gpio8_8 14 IO
Driver off 15 I
D9 vout1_d9 vout1_d9 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 2 O
vin2a_d9
vin1a_d9		 3 I
vin1a_d9 4 I
pr2_edio_latch_in 10 I
pr2_pru0_gpi6 12 I
pr2_pru0_gpo6 13 O
gpio8_9 14 IO
Driver off 15 I
D7 vout1_d10 vout1_d10 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu3 2 O
vin2a_d10
vin1a_d10		 3 I
vin1a_d10 4 I
obs5 5 O
obs21 6 O
obs_irq2 7 O
pr2_edio_sof 10 O
pr2_pru0_gpi7 12 I
pr2_pru0_gpo7 13 O
gpio8_10 14 IO
Driver off 15 I
D8 vout1_d11 vout1_d11 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu10 2 O
vin2a_d11
vin1a_d11		 3 I
vin1a_d11 4 I
obs6 5 O
obs22 6 O
obs_dmarq2 7 O
pr2_uart0_cts_n 10 I
pr2_pru0_gpi8 12 I
pr2_pru0_gpo8 13 O
gpio8_11 14 IO
Driver off 15 I
A5 vout1_d12 vout1_d12 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu11 2 O
vin2a_d12
vin1a_d12		 3 I
vin1a_d12 4 I
obs7 5 O
obs23 6 O
pr2_uart0_rts_n 10 O
pr2_pru0_gpi9 12 I
pr2_pru0_gpo9 13 O
gpio8_12 14 IO
Driver off 15 I
C6 vout1_d13 vout1_d13 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu12 2 O
vin2a_d13
vin1a_d13		 3 I
vin1a_d13 4 I
obs8 5 O
obs24 6 O
pr2_uart0_rxd 10 I
pr2_pru0_gpi10 12 I
pr2_pru0_gpo10 13 O
gpio8_13 14 IO
Driver off 15 I
C8 vout1_d14 vout1_d14 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu13 2 O
vin2a_d14
vin1a_d14		 3 I
vin1a_d14 4 I
obs9 5 O
obs25 6 O
pr2_uart0_txd 10 O
pr2_pru0_gpi11 12 I
pr2_pru0_gpo11 13 O
gpio8_14 14 IO
Driver off 15 I
C7 vout1_d15 vout1_d15 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu14 2 O
vin2a_d15
vin1a_d15		 3 I
vin1a_d15 4 I
obs10 5 O
obs26 6 O
pr2_ecap0_ecap_capin_apwm_o 10 IO
pr2_pru0_gpi12 12 I
pr2_pru0_gpo12 13 O
gpio8_15 14 IO
Driver off 15 I
B7 vout1_d16 vout1_d16 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart7_rxd 2 I
vin2a_d0
vin1a_d0		 3 I
vin1a_d0 4 I
pr2_edio_data_in0 10 I
pr2_edio_data_out0 11 O
pr2_pru0_gpi13 12 I
pr2_pru0_gpo13 13 O
gpio8_16 14 IO
Driver off 15 I
B8 vout1_d17 vout1_d17 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart7_txd 2 O
vin2a_d1
vin1a_d1		 3 I
vin1a_d1 4 I
pr2_edio_data_in1 10 I
pr2_edio_data_out1 11 O
pr2_pru0_gpi14 12 I
pr2_pru0_gpo14 13 O
gpio8_17 14 IO
Driver off 15 I
A7 vout1_d18 vout1_d18 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu4 2 O
vin2a_d2
vin1a_d2		 3 I
vin1a_d2 4 I
obs11 5 O
obs27 6 O
pr2_edio_data_in2 10 I
pr2_edio_data_out2 11 O
pr2_pru0_gpi15 12 I
pr2_pru0_gpo15 13 O
gpio8_18 14 IO
Driver off 15 I
A8 vout1_d19 vout1_d19 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu15 2 O
vin2a_d3
vin1a_d3		 3 I
vin1a_d3 4 I
obs12 5 O
obs28 6 O
pr2_edio_data_in3 10 I
pr2_edio_data_out3 11 O
pr2_pru0_gpi16 12 I
pr2_pru0_gpo16 13 O
gpio8_19 14 IO
Driver off 15 I
C9 vout1_d20 vout1_d20 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu16 2 O
vin2a_d4
vin1a_d4		 3 I
vin1a_d4 4 I
obs13 5 O
obs29 6 O
pr2_edio_data_in4 10 I
pr2_edio_data_out4 11 O
pr2_pru0_gpi17 12 I
pr2_pru0_gpo17 13 O
gpio8_20 14 IO
Driver off 15 I
A9 vout1_d21 vout1_d21 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu17 2 O
vin2a_d5
vin1a_d5		 3 I
vin1a_d5 4 I
obs14 5 O
obs30 6 O
pr2_edio_data_in5 10 I
pr2_edio_data_out5 11 O
pr2_pru0_gpi18 12 I
pr2_pru0_gpo18 13 O
gpio8_21 14 IO
Driver off 15 I
B9 vout1_d22 vout1_d22 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu18 2 O
vin2a_d6
vin1a_d6		 3 I
vin1a_d6 4 I
obs15 5 O
obs31 6 O
pr2_edio_data_in6 10 I
pr2_edio_data_out6 11 O
pr2_pru0_gpi19 12 I
pr2_pru0_gpo19 13 O
gpio8_22 14 IO
Driver off 15 I
A10 vout1_d23 vout1_d23 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu19 2 O
vin2a_d7
vin1a_d7		 3 I
vin1a_d7 4 I
spi3_cs3 8 IO
pr2_edio_data_in7 10 I
pr2_edio_data_out7 11 O
pr2_pru0_gpi20 12 I
pr2_pru0_gpo20 13 O
gpio8_23 14 IO
Driver off 15 I
B10 vout1_de vout1_de No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_de0
vin1a_de0		 3 I
vin1a_de0 4 I
spi3_d1 8 IO
gpio4_20 14 IO
Driver off 15 I
B11 vout1_fld vout1_fld No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_clk0
vin1a_clk0		 3 I
vin1a_clk0 4 I
spi3_cs1 8 IO
gpio4_21 14 IO
Driver off 15 I
C11 vout1_hsync vout1_hsync No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_hsync0
vin1a_hsync0		 3 I
vin1a_hsync0 4 I
spi3_d0 8 IO
gpio4_22 14 IO
Driver off 15 I
E11 vout1_vsync vout1_vsync No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_vsync0
vin1a_vsync0		 3 I
vin1a_vsync0 4 I
spi3_sclk 8 IO
pr2_pru1_gpi17 12 I
pr2_pru1_gpo17 13 O
gpio4_23 14 IO
Driver off 15 I
A1, A14, A2, A23, A28, A6, AA14, AA15, AA20, AA8, AA9, AB14, AB20, AD1, AD24, AG1, AH1, AH2, AH20, AH28, B1, D13, D19, E13, E19, F1, F7, G7, G8, G9, H12, J12, J15, J28, K1, K15, K24, K25, K4, K5, L13, L14, M19, N14, N15, N19, N24, N25, P28, R1, R12, R13, R21, T10, T11, T12, T14, T15, T17, T18, T21, U14, U15, U17, U20, U21, V15, V17, W1, W15, W24, W25, W28 vss vss GND
AA10, AH8 vssa_csi vssa_csi GND
AD19, AE19 vssa_hdmi vssa_hdmi GND
AF15 vssa_osc0 vssa_osc0 GND
AC14 vssa_osc1 vssa_osc1 GND
AD13, AE13 vssa_pcie vssa_pcie GND
AE10 vssa_sata vssa_sata GND
AA11, AB11 vssa_usb vssa_usb GND
AD10 vssa_usb3 vssa_usb3 GND
R15 vssa_video vssa_video GND
AD17 Wakeup0 Wakeup0 0 I 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
dcan1_rx 1 I
gpio1_0
sys_nirq2		 14 I
Driver off 15 I
AC16 Wakeup3 Wakeup3 0 I 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
sys_nirq1 1 I
gpio1_3
dcan2_rx		 14 I
Driver off 15 I
AE15 xi_osc0 xi_osc0 0 I 1.8 vdda_osc No LVCMOS Analog NA
AC15 xi_osc1 xi_osc1 0 I 1.8 vdda_osc No LVCMOS Analog NA
AD15 xo_osc0 xo_osc0 0 O 1.8 vdda_osc No LVCMOS Analog NA
AC13 xo_osc1 xo_osc1 0 A 1.8 vdda_osc No LVCMOS Analog NA
D18 xref_clk0 xref_clk0 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr8 1 IO
mcasp1_axr4 2 IO
mcasp1_ahclkx 3 O
mcasp5_ahclkx 4 O
vin1a_d0 7 I
hdq0 8 IO
clkout2 9 O
timer13 10 IO
pr2_mii1_col 11 I
pr2_pru1_gpi5 12 I
pr2_pru1_gpo5 13 O
gpio6_17 14 IO
Driver off 15 I
E17 xref_clk1 xref_clk1 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr9 1 IO
mcasp1_axr5 2 IO
mcasp2_ahclkx 3 O
mcasp6_ahclkx 4 O
vin1a_clk0 7 I
timer14 10 IO
pr2_mii1_crs 11 I
pr2_pru1_gpi6 12 I
pr2_pru1_gpo6 13 O
gpio6_18 14 IO
Driver off 15 I
B26 xref_clk2 xref_clk2 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr10 1 IO
mcasp1_axr6 2 IO
mcasp3_ahclkx 3 O
mcasp7_ahclkx 4 O
vout2_clk No 6 O
vin2a_clk0
vin1a_clk0		 8 I
timer15 10 IO
gpio6_19 14 IO
Driver off 15 I
C23 xref_clk3 xref_clk3 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr11 1 IO
mcasp1_axr7 2 IO
mcasp4_ahclkx 3 O
mcasp8_ahclkx 4 O
vout2_de No 6 O
hdq0 7 IO
vin2a_de0
vin1a_de0		 8 I
clkout3 9 O
timer16 10 IO
gpio6_20 14 IO
Driver off 15 I
  1. NA in this table stands for Not Applicable.
  2. For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions.
  3. The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
  4. The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the Device TRM.
  5. IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
  6. Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
    For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
  7. This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
  8. In PUx / PDy, x and y = 60 to 200 μA.
    The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.

4.3 Multiplexing Characteristics

Table 4-3 describes the device multiplexing (no characteristics are available in this table).

NOTE

This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal Descriptions.

NOTE

For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section of the Device TRM.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

NOTE

In some cases Table 4-3 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

NOTE

Dual rank support is not available on this device, but signal names are retained for consistency with the AM57xx family of devices.

CAUTION

The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the corresponding tables.

Table 4-3 Multiplexing Characteristics(1)

ADDRESS REGISTER NAME BALL NUMBER MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15
Y23 ddr1_d26
Y19 ddr1_d21
AE15 xi_osc0
AH24 ddr1_nck
AG15 ljcb_clkp
AF24 ddr1_d4
V25 ddr1_ecc_d6
AB16 ddr1_csn1
AG19 hdmi1_data2x
AF21 ddr1_a4
AG5 csi2_1_dx0
W23 ddr1_ecc_d3
Y27 ddr1_dqsn3
AC24 ddr1_d14
AF28 ddr1_d11
AA23 ddr1_d24
AD18 ddr1_a15
AH16 hdmi1_clocky
AH5 csi2_1_dy0
AC20 ddr1_a2
AA24 ddr1_d27
W19 ddr1_ecc_d2
AG21 ddr1_rst
AE28 ddr1_dqsn1
AC11 usb_txn0 pcie_txn1
AG25 ddr1_dqsn0
AC17 ddr1_odt1
AG4 csi2_0_dy3
W20 ddr1_d17
AF14 rtc_iso
AA27 ddr1_dqm3
AF25 ddr1_d0
AF2 csi2_0_dx2
AF23 ddr1_d6
AG18 hdmi1_data1x
AH6 csi2_1_dy1
AG10 sata1_txn0
AF20 ddr1_rasn
V26 ddr1_dqm_ecc
V20 ddr1_d16
AH13 pcie_rxp0
AC18 ddr1_casn
AG9 sata1_rxp0
AH23 ddr1_csn0
AE11 usb2_dp
Y24 ddr1_d28
AH15 ljcb_clkn
AD20 ddr1_a0
AA25 ddr1_d30
AA1 mlbp_dat_p
AD14 rtc_osc_xo
AC25 ddr1_d13
AB23 ddr1_dqm1
AE1 csi2_0_dx0
AH19 hdmi1_data2y
AB27 ddr1_d22
AG14 pcie_txn0
Y28 ddr1_dqs3
AB19 ddr1_a3
AH10 sata1_txp0
AG24 ddr1_ck
AE24 ddr1_d5
AC15 xi_osc1
AC21 ddr1_a12
AB1 mlbp_clk_p
AF12 usb_rxn0 pcie_rxn1
AH9 sata1_rxn0
AC26 ddr1_dqm2
AA28 ddr1_d31
AD23 ddr1_dqm0
AE27 ddr1_dqs1
AF27 ddr1_d9
V24 ddr1_ecc_d5
AG27 ddr1_d10
AF22 ddr1_a8
AA2 mlbp_dat_n
AH21 ddr1_wen
AE21 ddr1_a7
AC12 usb1_dm
Y20 ddr1_d23
AC27 ddr1_d20
AE23 ddr1_d7
AG22 ddr1_cke
AD27 ddr1_dqs2
AH14 pcie_txp0
AH26 ddr1_d3
AD21 ddr1_a10
Y25 ddr1_ecc_d4
AE17 ddr1_a14
AG7 csi2_1_dy2
AH18 hdmi1_data1y
AH22 ddr1_a5
W22 ddr1_ecc_d0
V23 ddr1_ecc_d1
AE12 usb_rxp0 pcie_rxp1
AE14 rtc_osc_xi_clkin32
AF3 csi2_0_dy2
AB2 mlbp_clk_n
AG23 ddr1_a6
AG6 csi2_1_dx1
AB18 ddr1_ba2
AG17 hdmi1_data0x
AF26 ddr1_d1
AD11 usb_txp0 pcie_txp1
AC1 mlbp_sig_p
V27 ddr1_dqs_ecc
AF17 ddr1_ba0
AE26 ddr1_d12
AC19 ddr1_a1
AG13 pcie_rxn0
AB28 ddr1_d18
Y26 ddr1_ecc_d7
AH3 csi2_0_dx4
AD22 ddr1_a11
AD28 ddr1_dqsn2
AD2 csi2_0_dy0
AE18 ddr1_ba1
AE20 ddr1_odt0
AF11 usb2_dm
AD15 xo_osc0
AH7 csi2_1_dx2
AE22 ddr1_a9
Y18 ddr1_vref0
AC13 xo_osc1
AC2 mlbp_sig_n
AD12 usb1_dp
Y22 ddr1_d25
AH17 hdmi1_data0y
AH4 csi2_0_dx3
AE2 csi2_0_dy1
AG26 ddr1_d2
AH25 ddr1_dqs0
AF18 ddr1_a13
AC28 ddr1_d19
AG3 csi2_0_dy4
V28 ddr1_dqsn_ecc
AC23 ddr1_d8
F22 porz
AG16 hdmi1_clockx
AF1 csi2_0_dx1
AA26 ddr1_d29
AD25 ddr1_d15
0x1400 CTRL_CORE_PAD_GPMC_AD0 M6 gpmc_ad0 vin1a_d0 vout3_d0 gpio1_6 sysboot0
0x1404 CTRL_CORE_PAD_GPMC_AD1 M2 gpmc_ad1 vin1a_d1 vout3_d1 gpio1_7 sysboot1
0x1408 CTRL_CORE_PAD_GPMC_AD2 L5 gpmc_ad2 vin1a_d2 vout3_d2 gpio1_8 sysboot2
0x140C CTRL_CORE_PAD_GPMC_AD3 M1 gpmc_ad3 vin1a_d3 vout3_d3 gpio1_9 sysboot3
0x1410 CTRL_CORE_PAD_GPMC_AD4 L6 gpmc_ad4 vin1a_d4 vout3_d4 gpio1_10 sysboot4
0x1414 CTRL_CORE_PAD_GPMC_AD5 L4 gpmc_ad5 vin1a_d5 vout3_d5 gpio1_11 sysboot5
0x1418 CTRL_CORE_PAD_GPMC_AD6 L3 gpmc_ad6 vin1a_d6 vout3_d6 gpio1_12 sysboot6
0x141C CTRL_CORE_PAD_GPMC_AD7 L2 gpmc_ad7 vin1a_d7 vout3_d7 gpio1_13 sysboot7
0x1420 CTRL_CORE_PAD_GPMC_AD8 L1 gpmc_ad8 vin1a_d8 vout3_d8 gpio7_18 sysboot8
0x1424 CTRL_CORE_PAD_GPMC_AD9 K2 gpmc_ad9 vin1a_d9 vout3_d9 gpio7_19 sysboot9
0x1428 CTRL_CORE_PAD_GPMC_AD10 J1 gpmc_ad10 vin1a_d10 vout3_d10 gpio7_28 sysboot10
0x142C CTRL_CORE_PAD_GPMC_AD11 J2 gpmc_ad11 vin1a_d11 vout3_d11 gpio7_29 sysboot11
0x1430 CTRL_CORE_PAD_GPMC_AD12 H1 gpmc_ad12 vin1a_d12 vout3_d12 gpio1_18 sysboot12
0x1434 CTRL_CORE_PAD_GPMC_AD13 J3 gpmc_ad13 vin1a_d13 vout3_d13 gpio1_19 sysboot13
0x1438 CTRL_CORE_PAD_GPMC_AD14 H2 gpmc_ad14 vin1a_d14 vout3_d14 gpio1_20 sysboot14
0x143C CTRL_CORE_PAD_GPMC_AD15 H3 gpmc_ad15 vin1a_d15 vout3_d15 gpio1_21 sysboot15
0x1440 CTRL_CORE_PAD_GPMC_A0 R6 gpmc_a0 vin1a_d16 vout3_d16 vin2a_d0 vin1a_d0 vin1b_d0 i2c4_scl uart5_rxd gpio7_3 gpmc_a26 gpmc_a16 Driver off
0x1444 CTRL_CORE_PAD_GPMC_A1 T9 gpmc_a1 vin1a_d17 vout3_d17 vin2a_d1 vin1a_d1 vin1b_d1 i2c4_sda uart5_txd gpio7_4 Driver off
0x1448 CTRL_CORE_PAD_GPMC_A2 T6 gpmc_a2 vin1a_d18 vout3_d18 vin2a_d2 vin1a_d2 vin1b_d2 uart7_rxd uart5_ctsn gpio7_5 Driver off
0x144C CTRL_CORE_PAD_GPMC_A3 T7 gpmc_a3 qspi1_cs2 vin1a_d19 vout3_d19 vin2a_d3 vin1a_d3 vin1b_d3 uart7_txd uart5_rtsn gpio7_6 Driver off
0x1450 CTRL_CORE_PAD_GPMC_A4 P6 gpmc_a4 qspi1_cs3 vin1a_d20 vout3_d20 vin2a_d4 vin1a_d4 vin1b_d4 i2c5_scl uart6_rxd gpio1_26 Driver off
0x1454 CTRL_CORE_PAD_GPMC_A5 R9 gpmc_a5 vin1a_d21 vout3_d21 vin2a_d5 vin1a_d5 vin1b_d5 i2c5_sda uart6_txd gpio1_27 Driver off
0x1458 CTRL_CORE_PAD_GPMC_A6 R5 gpmc_a6 vin1a_d22 vout3_d22 vin2a_d6 vin1a_d6 vin1b_d6 uart8_rxd uart6_ctsn gpio1_28 Driver off
0x145C CTRL_CORE_PAD_GPMC_A7 P5 gpmc_a7 vin1a_d23 vout3_d23 vin2a_d7 vin1a_d7 vin1b_d7 uart8_txd uart6_rtsn gpio1_29 Driver off
0x1460 CTRL_CORE_PAD_GPMC_A8 N7 gpmc_a8 vin1a_hsync0 vout3_hsync vin1b_hsync1 timer12 spi4_sclk gpio1_30 Driver off
0x1464 CTRL_CORE_PAD_GPMC_A9 R4 gpmc_a9 vin1a_vsync0 vout3_vsync vin1b_vsync1 timer11 spi4_d1 gpio1_31 Driver off
0x1468 CTRL_CORE_PAD_GPMC_A10 N9 gpmc_a10 vin1a_de0 vout3_de vin1b_clk1 timer10 spi4_d0 gpio2_0 Driver off
0x146C CTRL_CORE_PAD_GPMC_A11 P9 gpmc_a11 vin1a_fld0 vout3_fld vin2a_fld0 vin1a_fld0 vin1b_de1 timer9 spi4_cs0 gpio2_1 Driver off
0x1470 CTRL_CORE_PAD_GPMC_A12 P4 gpmc_a12 vin2a_clk0 vin1a_clk0 gpmc_a0 vin1b_fld1 timer8 spi4_cs1 dma_evt1 gpio2_2 Driver off
0x1474 CTRL_CORE_PAD_GPMC_A13 R3 gpmc_a13 qspi1_rtclk vin2a_hsync0 vin1a_hsync0 timer7 spi4_cs2 dma_evt2 gpio2_3 Driver off
0x1478 CTRL_CORE_PAD_GPMC_A14 T2 gpmc_a14 qspi1_d3 vin2a_vsync0 vin1a_vsync0 timer6 spi4_cs3 gpio2_4 Driver off
0x147C CTRL_CORE_PAD_GPMC_A15 U2 gpmc_a15 qspi1_d2 vin2a_d8 vin1a_d8 timer5 gpio2_5 Driver off
0x1480 CTRL_CORE_PAD_GPMC_A16 U1 gpmc_a16 qspi1_d0 vin2a_d9 vin1a_d9 gpio2_6 Driver off
0x1484 CTRL_CORE_PAD_GPMC_A17 P3 gpmc_a17 qspi1_d1 vin2a_d10 vin1a_d10 gpio2_7 Driver off
0x1488 CTRL_CORE_PAD_GPMC_A18 R2 gpmc_a18 qspi1_sclk vin2a_d11 vin1a_d11 gpio2_8 Driver off
0x148C CTRL_CORE_PAD_GPMC_A19 K7 gpmc_a19 mmc2_dat4 gpmc_a13 vin2a_d12 vin1a_d12 vin2b_d0 vin1b_d0 gpio2_9 Driver off
0x1490 CTRL_CORE_PAD_GPMC_A20 M7 gpmc_a20 mmc2_dat5 gpmc_a14 vin2a_d13 vin1a_d13 vin2b_d1 vin1b_d1 gpio2_10 Driver off
0x1494 CTRL_CORE_PAD_GPMC_A21 J5 gpmc_a21 mmc2_dat6 gpmc_a15 vin2a_d14 vin1a_d14 vin2b_d2 vin1b_d2 gpio2_11 Driver off
0x1498 CTRL_CORE_PAD_GPMC_A22 K6 gpmc_a22 mmc2_dat7 gpmc_a16 vin2a_d15 vin1a_d15 vin2b_d3 vin1b_d3 gpio2_12 Driver off
0x149C CTRL_CORE_PAD_GPMC_A23 J7 gpmc_a23 mmc2_clk gpmc_a17 vin2a_fld0 vin1a_fld0 vin2b_d4 vin1b_d4 gpio2_13 Driver off
0x14A0 CTRL_CORE_PAD_GPMC_A24 J4 gpmc_a24 mmc2_dat0 gpmc_a18 vin1a_d8 vin2b_d5 vin1b_d5 gpio2_14 Driver off
0x14A4 CTRL_CORE_PAD_GPMC_A25 J6 gpmc_a25 mmc2_dat1 gpmc_a19 vin1a_d9 vin2b_d6 vin1b_d6 gpio2_15 Driver off
0x14A8 CTRL_CORE_PAD_GPMC_A26 H4 gpmc_a26 mmc2_dat2 gpmc_a20 vin1a_d10 vin2b_d7 vin1b_d7 gpio2_16 Driver off
0x14AC CTRL_CORE_PAD_GPMC_A27 H5 gpmc_a27 mmc2_dat3 gpmc_a21 vin1a_d11 vin2b_hsync1 vin1b_hsync1 gpio2_17 Driver off
0x14B0 CTRL_CORE_PAD_GPMC_CS1 H6 gpmc_cs1 mmc2_cmd gpmc_a22 vin2a_de0 vin1a_de0 vin2b_vsync1 vin1b_vsync1 gpio2_18 Driver off
0x14B4 CTRL_CORE_PAD_GPMC_CS0 T1 gpmc_cs0 gpio2_19 Driver off
0x14B8 CTRL_CORE_PAD_GPMC_CS2 P2 gpmc_cs2 qspi1_cs0 gpio2_20 gpmc_a23 gpmc_a13 Driver off
0x14BC CTRL_CORE_PAD_GPMC_CS3 P1 gpmc_cs3 qspi1_cs1 vin1a_clk0 vout3_clk gpmc_a1 gpio2_21 gpmc_a24 gpmc_a14 Driver off
0x14C0 CTRL_CORE_PAD_GPMC_CLK P7 gpmc_clk gpmc_cs7 clkout1 gpmc_wait1 vin2a_hsync0 vin1a_hsync0 vin2a_de0 vin1a_de0 vin2b_clk1 vin1b_clk1 timer4 i2c3_scl dma_evt1 gpio2_22 gpmc_a20 Driver off
0x14C4 CTRL_CORE_PAD_GPMC_ADVN_ALE N1 gpmc_advn_ale gpmc_cs6 clkout2 gpmc_wait1 vin2a_vsync0 vin1a_vsync0 gpmc_a2 gpmc_a23 timer3 i2c3_sda dma_evt2 gpio2_23 gpmc_a19 Driver off
0x14C8 CTRL_CORE_PAD_GPMC_OEN_REN M5 gpmc_oen_ren gpio2_24 Driver off
0x14CC CTRL_CORE_PAD_GPMC_WEN M3 gpmc_wen gpio2_25 Driver off
0x14D0 CTRL_CORE_PAD_GPMC_BEN0 N6 gpmc_ben0 gpmc_cs4 vin2b_de1 vin1b_de1 timer2 dma_evt3 gpio2_26 gpmc_a21 Driver off
0x14D4 CTRL_CORE_PAD_GPMC_BEN1 M4 gpmc_ben1 gpmc_cs5 vin2b_clk1 vin1b_clk1 gpmc_a3 vin2b_fld1 vin1b_fld1 timer1 dma_evt4 gpio2_27 gpmc_a22 Driver off
0x14D8 CTRL_CORE_PAD_GPMC_WAIT0 N2 gpmc_wait0 gpio2_28 gpmc_a25 gpmc_a15 Driver off
0x1554 CTRL_CORE_PAD_VIN2A_CLK0 E1 vin2a_clk0 vout2_fld emu5 kbd_row0 eQEP1A_in pr1_edio_data_in0 pr1_edio_data_out0 gpio3_28 gpmc_a27 gpmc_a17 Driver off
0x1558 CTRL_CORE_PAD_VIN2A_DE0 G2 vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de emu6 kbd_row1 eQEP1B_in pr1_edio_data_in1 pr1_edio_data_out1 gpio3_29 Driver off
0x155C CTRL_CORE_PAD_VIN2A_FLD0 H7 vin2a_fld0 vin2b_clk1 vout2_clk emu7 eQEP1_index pr1_edio_data_in2 pr1_edio_data_out2 gpio3_30 gpmc_a27 gpmc_a18 Driver off
0x1560 CTRL_CORE_PAD_VIN2A_HSYNC0 G1 vin2a_hsync0 vin2b_hsync1 vout2_hsync emu8 uart9_rxd spi4_sclk kbd_row2 eQEP1_strobe pr1_uart0_cts_n pr1_edio_data_in3 pr1_edio_data_out3 gpio3_31 gpmc_a27 Driver off
0x1564 CTRL_CORE_PAD_VIN2A_VSYNC0 G6 vin2a_vsync0 vin2b_vsync1 vout2_vsync emu9 uart9_txd spi4_d1 kbd_row3 ehrpwm1A pr1_uart0_rts_n pr1_edio_data_in4 pr1_edio_data_out4 gpio4_0 Driver off
0x1568 CTRL_CORE_PAD_VIN2A_D0 F2 vin2a_d0 vout2_d23 emu10 uart9_ctsn spi4_d0 kbd_row4 ehrpwm1B pr1_uart0_rxd pr1_edio_data_in5 pr1_edio_data_out5 gpio4_1 Driver off
0x156C CTRL_CORE_PAD_VIN2A_D1 F3 vin2a_d1 vout2_d22 emu11 uart9_rtsn spi4_cs0 kbd_row5 ehrpwm1_tripzone_input pr1_uart0_txd pr1_edio_data_in6 pr1_edio_data_out6 gpio4_2 Driver off
0x1570 CTRL_CORE_PAD_VIN2A_D2 D1 vin2a_d2 vout2_d21 emu12 uart10_rxd kbd_row6 eCAP1_in_PWM1_out pr1_ecap0_ecap_capin_apwm_o pr1_edio_data_in7 pr1_edio_data_out7 gpio4_3 Driver off
0x1574 CTRL_CORE_PAD_VIN2A_D3 E2 vin2a_d3 vout2_d20 emu13 uart10_txd kbd_col0 ehrpwm1_synci pr1_edc_latch0_in pr1_pru1_gpi0 pr1_pru1_gpo0 gpio4_4 Driver off
0x1578 CTRL_CORE_PAD_VIN2A_D4 D2 vin2a_d4 vout2_d19 emu14 uart10_ctsn kbd_col1 ehrpwm1_synco pr1_edc_sync0_out pr1_pru1_gpi1 pr1_pru1_gpo1 gpio4_5 Driver off
0x157C CTRL_CORE_PAD_VIN2A_D5 F4 vin2a_d5 vout2_d18 emu15 uart10_rtsn kbd_col2 eQEP2A_in pr1_edio_sof pr1_pru1_gpi2 pr1_pru1_gpo2 gpio4_6 Driver off
0x1580 CTRL_CORE_PAD_VIN2A_D6 C1 vin2a_d6 vout2_d17 emu16 mii1_rxd1 kbd_col3 eQEP2B_in pr1_mii_mt1_clk pr1_pru1_gpi3 pr1_pru1_gpo3 gpio4_7 Driver off
0x1584 CTRL_CORE_PAD_VIN2A_D7 E4 vin2a_d7 vout2_d16 emu17 mii1_rxd2 kbd_col4 eQEP2_index pr1_mii1_txen pr1_pru1_gpi4 pr1_pru1_gpo4 gpio4_8 Driver off
0x1588 CTRL_CORE_PAD_VIN2A_D8 F5 vin2a_d8 vout2_d15 emu18 mii1_rxd3 kbd_col5 eQEP2_strobe pr1_mii1_txd3 pr1_pru1_gpi5 pr1_pru1_gpo5 gpio4_9 gpmc_a26 Driver off
0x158C CTRL_CORE_PAD_VIN2A_D9 E6 vin2a_d9 vout2_d14 emu19 mii1_rxd0 kbd_col6 ehrpwm2A pr1_mii1_txd2 pr1_pru1_gpi6 pr1_pru1_gpo6 gpio4_10 gpmc_a25 Driver off
0x1590 CTRL_CORE_PAD_VIN2A_D10 D3 vin2a_d10 mdio_mclk vout2_d13 kbd_col7 ehrpwm2B pr1_mdio_mdclk pr1_pru1_gpi7 pr1_pru1_gpo7 gpio4_11 gpmc_a24 Driver off
0x1594 CTRL_CORE_PAD_VIN2A_D11 F6 vin2a_d11 mdio_d vout2_d12 kbd_row7 ehrpwm2_tripzone_input pr1_mdio_data pr1_pru1_gpi8 pr1_pru1_gpo8 gpio4_12 gpmc_a23 Driver off
0x1598 CTRL_CORE_PAD_VIN2A_D12 D5 vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk kbd_col8 eCAP2_in_PWM2_out pr1_mii1_txd1 pr1_pru1_gpi9 pr1_pru1_gpo9 gpio4_13 Driver off
0x159C CTRL_CORE_PAD_VIN2A_D13 C2 vin2a_d13 rgmii1_txctl vout2_d10 mii1_rxdv kbd_row8 eQEP3A_in pr1_mii1_txd0 pr1_pru1_gpi10 pr1_pru1_gpo10 gpio4_14 Driver off
0x15A0 CTRL_CORE_PAD_VIN2A_D14 C3 vin2a_d14 rgmii1_txd3 vout2_d9 mii1_txclk eQEP3B_in pr1_mii_mr1_clk pr1_pru1_gpi11 pr1_pru1_gpo11 gpio4_15 Driver off
0x15A4 CTRL_CORE_PAD_VIN2A_D15 C4 vin2a_d15 rgmii1_txd2 vout2_d8 mii1_txd0 eQEP3_index pr1_mii1_rxdv pr1_pru1_gpi12 pr1_pru1_gpo12 gpio4_16 Driver off
0x15A8 CTRL_CORE_PAD_VIN2A_D16 B2 vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 mii1_txd1 eQEP3_strobe pr1_mii1_rxd3 pr1_pru1_gpi13 pr1_pru1_gpo13 gpio4_24 Driver off
0x15AC CTRL_CORE_PAD_VIN2A_D17 D6 vin2a_d17 vin2b_d6 rgmii1_txd0 vout2_d6 mii1_txd2 ehrpwm3A pr1_mii1_rxd2 pr1_pru1_gpi14 pr1_pru1_gpo14 gpio4_25 Driver off
0x15B0 CTRL_CORE_PAD_VIN2A_D18 C5 vin2a_d18 vin2b_d5 rgmii1_rxc vout2_d5 mii1_txd3 ehrpwm3B pr1_mii1_rxd1 pr1_pru1_gpi15 pr1_pru1_gpo15 gpio4_26 Driver off
0x15B4 CTRL_CORE_PAD_VIN2A_D19 A3 vin2a_d19 vin2b_d4 rgmii1_rxctl vout2_d4 mii1_txer ehrpwm3_tripzone_input pr1_mii1_rxd0 pr1_pru1_gpi16 pr1_pru1_gpo16 gpio4_27 Driver off
0x15B8 CTRL_CORE_PAD_VIN2A_D20 B3 vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 mii1_rxer eCAP3_in_PWM3_out pr1_mii1_rxer pr1_pru1_gpi17 pr1_pru1_gpo17 gpio4_28 Driver off
0x15BC CTRL_CORE_PAD_VIN2A_D21 B4 vin2a_d21 vin2b_d2 rgmii1_rxd2 vout2_d2 mii1_col pr1_mii1_rxlink pr1_pru1_gpi18 pr1_pru1_gpo18 gpio4_29 Driver off
0x15C0 CTRL_CORE_PAD_VIN2A_D22 B5 vin2a_d22 vin2b_d1 rgmii1_rxd1 vout2_d1 mii1_crs pr1_mii1_col pr1_pru1_gpi19 pr1_pru1_gpo19 gpio4_30 Driver off
0x15C4 CTRL_CORE_PAD_VIN2A_D23 A4 vin2a_d23 vin2b_d0 rgmii1_rxd0 vout2_d0 mii1_txen pr1_mii1_crs pr1_pru1_gpi20 pr1_pru1_gpo20 gpio4_31 Driver off
0x15C8 CTRL_CORE_PAD_VOUT1_CLK D11 vout1_clk vin2a_fld0 vin1a_fld0 vin1a_fld0 spi3_cs0 gpio4_19 Driver off
0x15CC CTRL_CORE_PAD_VOUT1_DE B10 vout1_de vin2a_de0 vin1a_de0 vin1a_de0 spi3_d1 gpio4_20 Driver off
0x15D0 CTRL_CORE_PAD_VOUT1_FLD B11 vout1_fld vin2a_clk0 vin1a_clk0 vin1a_clk0 spi3_cs1 gpio4_21 Driver off
0x15D4 CTRL_CORE_PAD_VOUT1_HSYNC C11 vout1_hsync vin2a_hsync0 vin1a_hsync0 vin1a_hsync0 spi3_d0 gpio4_22 Driver off
0x15D8 CTRL_CORE_PAD_VOUT1_VSYNC E11 vout1_vsync vin2a_vsync0 vin1a_vsync0 vin1a_vsync0 spi3_sclk pr2_pru1_gpi17 pr2_pru1_gpo17 gpio4_23 Driver off
0x15DC CTRL_CORE_PAD_VOUT1_D0 F11 vout1_d0 uart5_rxd vin2a_d16 vin1a_d16 vin1a_d16 spi3_cs2 pr1_uart0_cts_n pr2_pru1_gpi18 pr2_pru1_gpo18 gpio8_0 Driver off
0x15E0 CTRL_CORE_PAD_VOUT1_D1 G10 vout1_d1 uart5_txd vin2a_d17 vin1a_d17 vin1a_d17 pr1_uart0_rts_n pr2_pru1_gpi19 pr2_pru1_gpo19 gpio8_1 Driver off
0x15E4 CTRL_CORE_PAD_VOUT1_D2 F10 vout1_d2 emu2 vin2a_d18 vin1a_d18 vin1a_d18 obs0 obs16 obs_irq1 pr1_uart0_rxd pr2_pru1_gpi20 pr2_pru1_gpo20 gpio8_2 Driver off
0x15E8 CTRL_CORE_PAD_VOUT1_D3 G11 vout1_d3 emu5 vin2a_d19 vin1a_d19 vin1a_d19 obs1 obs17 obs_dmarq1 pr1_uart0_txd pr2_pru0_gpi0 pr2_pru0_gpo0 gpio8_3 Driver off
0x15EC CTRL_CORE_PAD_VOUT1_D4 E9 vout1_d4 emu6 vin2a_d20 vin1a_d20 vin1a_d20 obs2 obs18 pr1_ecap0_ecap_capin_apwm_o pr2_pru0_gpi1 pr2_pru0_gpo1 gpio8_4 Driver off
0x15F0 CTRL_CORE_PAD_VOUT1_D5 F9 vout1_d5 emu7 vin2a_d21 vin1a_d21 vin1a_d21 obs3 obs19 pr2_edc_latch0_in pr2_pru0_gpi2 pr2_pru0_gpo2 gpio8_5 Driver off
0x15F4 CTRL_CORE_PAD_VOUT1_D6 F8 vout1_d6 emu8 vin2a_d22 vin1a_d22 vin1a_d22 obs4 obs20 pr2_edc_latch1_in pr2_pru0_gpi3 pr2_pru0_gpo3 gpio8_6 Driver off
0x15F8 CTRL_CORE_PAD_VOUT1_D7 E7 vout1_d7 emu9 vin2a_d23 vin1a_d23 vin1a_d23 pr2_edc_sync0_out pr2_pru0_gpi4 pr2_pru0_gpo4 gpio8_7 Driver off
0x15FC CTRL_CORE_PAD_VOUT1_D8 E8 vout1_d8 uart6_rxd vin2a_d8 vin1a_d8 vin1a_d8 pr2_edc_sync1_out pr2_pru0_gpi5 pr2_pru0_gpo5 gpio8_8 Driver off
0x1600 CTRL_CORE_PAD_VOUT1_D9 D9 vout1_d9 uart6_txd vin2a_d9 vin1a_d9 vin1a_d9 pr2_edio_latch_in pr2_pru0_gpi6 pr2_pru0_gpo6 gpio8_9 Driver off
0x1604 CTRL_CORE_PAD_VOUT1_D10 D7 vout1_d10 emu3 vin2a_d10 vin1a_d10 vin1a_d10 obs5 obs21 obs_irq2 pr2_edio_sof pr2_pru0_gpi7 pr2_pru0_gpo7 gpio8_10 Driver off
0x1608 CTRL_CORE_PAD_VOUT1_D11 D8 vout1_d11 emu10 vin2a_d11 vin1a_d11 vin1a_d11 obs6 obs22 obs_dmarq2 pr2_uart0_cts_n pr2_pru0_gpi8 pr2_pru0_gpo8 gpio8_11 Driver off
0x160C CTRL_CORE_PAD_VOUT1_D12 A5 vout1_d12 emu11 vin2a_d12 vin1a_d12 vin1a_d12 obs7 obs23 pr2_uart0_rts_n pr2_pru0_gpi9 pr2_pru0_gpo9 gpio8_12 Driver off
0x1610 CTRL_CORE_PAD_VOUT1_D13 C6 vout1_d13 emu12 vin2a_d13 vin1a_d13 vin1a_d13 obs8 obs24 pr2_uart0_rxd pr2_pru0_gpi10 pr2_pru0_gpo10 gpio8_13 Driver off
0x1614 CTRL_CORE_PAD_VOUT1_D14 C8 vout1_d14 emu13 vin2a_d14 vin1a_d14 vin1a_d14 obs9 obs25 pr2_uart0_txd pr2_pru0_gpi11 pr2_pru0_gpo11 gpio8_14 Driver off
0x1618 CTRL_CORE_PAD_VOUT1_D15 C7 vout1_d15 emu14 vin2a_d15 vin1a_d15 vin1a_d15 obs10 obs26 pr2_ecap0_ecap_capin_apwm_o pr2_pru0_gpi12 pr2_pru0_gpo12 gpio8_15 Driver off
0x161C CTRL_CORE_PAD_VOUT1_D16 B7 vout1_d16 uart7_rxd vin2a_d0 vin1a_d0 vin1a_d0 pr2_edio_data_in0 pr2_edio_data_out0 pr2_pru0_gpi13 pr2_pru0_gpo13 gpio8_16 Driver off
0x1620 CTRL_CORE_PAD_VOUT1_D17 B8 vout1_d17 uart7_txd vin2a_d1 vin1a_d1 vin1a_d1 pr2_edio_data_in1 pr2_edio_data_out1 pr2_pru0_gpi14 pr2_pru0_gpo14 gpio8_17 Driver off
0x1624 CTRL_CORE_PAD_VOUT1_D18 A7 vout1_d18 emu4 vin2a_d2 vin1a_d2 vin1a_d2 obs11 obs27 pr2_edio_data_in2 pr2_edio_data_out2 pr2_pru0_gpi15 pr2_pru0_gpo15 gpio8_18 Driver off
0x1628 CTRL_CORE_PAD_VOUT1_D19 A8 vout1_d19 emu15 vin2a_d3 vin1a_d3 vin1a_d3 obs12 obs28 pr2_edio_data_in3 pr2_edio_data_out3 pr2_pru0_gpi16 pr2_pru0_gpo16 gpio8_19 Driver off
0x162C CTRL_CORE_PAD_VOUT1_D20 C9 vout1_d20 emu16 vin2a_d4 vin1a_d4 vin1a_d4 obs13 obs29 pr2_edio_data_in4 pr2_edio_data_out4 pr2_pru0_gpi17 pr2_pru0_gpo17 gpio8_20 Driver off
0x1630 CTRL_CORE_PAD_VOUT1_D21 A9 vout1_d21 emu17 vin2a_d5 vin1a_d5 vin1a_d5 obs14 obs30 pr2_edio_data_in5 pr2_edio_data_out5 pr2_pru0_gpi18 pr2_pru0_gpo18 gpio8_21 Driver off
0x1634 CTRL_CORE_PAD_VOUT1_D22 B9 vout1_d22 emu18 vin2a_d6 vin1a_d6 vin1a_d6 obs15 obs31 pr2_edio_data_in6 pr2_edio_data_out6 pr2_pru0_gpi19 pr2_pru0_gpo19 gpio8_22 Driver off
0x1638 CTRL_CORE_PAD_VOUT1_D23 A10 vout1_d23 emu19 vin2a_d7 vin1a_d7 vin1a_d7 spi3_cs3 pr2_edio_data_in7 pr2_edio_data_out7 pr2_pru0_gpi20 pr2_pru0_gpo20 gpio8_23 Driver off
0x163C CTRL_CORE_PAD_MDIO_MCLK V1 mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin1b_clk1 pr1_mii0_col pr2_pru1_gpi0 pr2_pru1_gpo0 gpio5_15 Driver off
0x1640 CTRL_CORE_PAD_MDIO_D U4 mdio_d uart3_ctsn mii0_txer vin2a_d0 vin1b_d0 pr1_mii0_rxlink pr2_pru1_gpi1 pr2_pru1_gpo1 gpio5_16 Driver off
0x1644 CTRL_CORE_PAD_RMII_MHZ_50_CLK U3 RMII_MHZ_50_CLK vin2a_d11 pr2_pru1_gpi2 pr2_pru1_gpo2 gpio5_17 Driver off
0x1648 CTRL_CORE_PAD_UART3_RXD V2 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin1b_d1 spi3_sclk pr1_mii0_rxdv pr2_pru1_gpi3 pr2_pru1_gpo3 gpio5_18 Driver off
0x164C CTRL_CORE_PAD_UART3_TXD Y1 uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin1b_d2 spi3_d1 spi4_cs1 pr1_mii_mr0_clk pr2_pru1_gpi4 pr2_pru1_gpo4 gpio5_19 Driver off
0x1650 CTRL_CORE_PAD_RGMII0_TXC W9 rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin1b_d3 spi3_d0 spi4_cs2 pr1_mii0_rxd3 pr2_pru1_gpi5 pr2_pru1_gpo5 gpio5_20 Driver off
0x1654 CTRL_CORE_PAD_RGMII0_TXCTL V9 rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin1b_d4 spi3_cs0 spi4_cs3 pr1_mii0_rxd2 pr2_pru1_gpi6 pr2_pru1_gpo6 gpio5_21 Driver off
0x1658 CTRL_CORE_PAD_RGMII0_TXD3 V7 rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin1b_de1 spi4_sclk uart4_rxd pr1_mii0_crs pr2_pru1_gpi7 pr2_pru1_gpo7 gpio5_22 Driver off
0x165C CTRL_CORE_PAD_RGMII0_TXD2 U7 rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsync0 vin1b_hsync1 spi4_d1 uart4_txd pr1_mii0_rxer pr2_pru1_gpi8 pr2_pru1_gpo8 gpio5_23 Driver off
0x1660 CTRL_CORE_PAD_RGMII0_TXD1 V6 rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsync0 vin1b_vsync1 spi4_d0 uart4_ctsn pr1_mii0_rxd1 pr2_pru1_gpi9 pr2_pru1_gpo9 gpio5_24 Driver off
0x1664 CTRL_CORE_PAD_RGMII0_TXD0 U6 rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 spi4_cs0 uart4_rtsn pr1_mii0_rxd0 pr2_pru1_gpi10 pr2_pru1_gpo10 gpio5_25 Driver off
0x1668 CTRL_CORE_PAD_RGMII0_RXC U5 rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin1b_d5 pr1_mii_mt0_clk pr2_pru1_gpi11 pr2_pru1_gpo11 gpio5_26 Driver off
0x166C CTRL_CORE_PAD_RGMII0_RXCTL V5 rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin1b_d6 pr1_mii0_txd3 pr2_pru1_gpi12 pr2_pru1_gpo12 gpio5_27 Driver off
0x1670 CTRL_CORE_PAD_RGMII0_RXD3 V4 rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin1b_d7 pr1_mii0_txd2 pr2_pru1_gpi13 pr2_pru1_gpo13 gpio5_28 Driver off
0x1674 CTRL_CORE_PAD_RGMII0_RXD2 V3 rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 pr1_mii0_txen pr2_pru1_gpi14 pr2_pru1_gpo14 gpio5_29 Driver off
0x1678 CTRL_CORE_PAD_RGMII0_RXD1 Y2 rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 pr1_mii0_txd1 pr2_pru1_gpi15 pr2_pru1_gpo15 gpio5_30 Driver off
0x167C CTRL_CORE_PAD_RGMII0_RXD0 W2 rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin1b_fld1 pr1_mii0_txd0 pr2_pru1_gpi16 pr2_pru1_gpo16 gpio5_31 Driver off
0x1680 CTRL_CORE_PAD_USB1_DRVVBUS AB10 usb1_drvvbus timer16 gpio6_12 Driver off
0x1684 CTRL_CORE_PAD_USB2_DRVVBUS AC10 usb2_drvvbus timer15 gpio6_13 Driver off
0x1688 CTRL_CORE_PAD_GPIO6_14 E21 gpio6_14 mcasp1_axr8 dcan2_tx uart10_rxd vout2_hsync vin2a_hsync0 vin1a_hsync0 i2c3_sda timer1 gpio6_14 Driver off
0x168C CTRL_CORE_PAD_GPIO6_15 F20 gpio6_15 mcasp1_axr9 dcan2_rx uart10_txd vout2_vsync vin2a_vsync0 vin1a_vsync0 i2c3_scl timer2 gpio6_15 Driver off
0x1690 CTRL_CORE_PAD_GPIO6_16 F21 gpio6_16 mcasp1_axr10 vout2_fld vin2a_fld0 vin1a_fld0 clkout1 timer3 gpio6_16 Driver off
0x1694 CTRL_CORE_PAD_XREF_CLK0 D18 xref_clk0 mcasp2_axr8 mcasp1_axr4 mcasp1_ahclkx mcasp5_ahclkx vin1a_d0 hdq0 clkout2 timer13 pr2_mii1_col pr2_pru1_gpi5 pr2_pru1_gpo5 gpio6_17 Driver off
0x1698 CTRL_CORE_PAD_XREF_CLK1 E17 xref_clk1 mcasp2_axr9 mcasp1_axr5 mcasp2_ahclkx mcasp6_ahclkx vin1a_clk0 timer14 pr2_mii1_crs pr2_pru1_gpi6 pr2_pru1_gpo6 gpio6_18 Driver off
0x169C CTRL_CORE_PAD_XREF_CLK2 B26 xref_clk2 mcasp2_axr10 mcasp1_axr6 mcasp3_ahclkx mcasp7_ahclkx vout2_clk vin2a_clk0 vin1a_clk0 timer15 gpio6_19 Driver off
0x16A0 CTRL_CORE_PAD_XREF_CLK3 C23 xref_clk3 mcasp2_axr11 mcasp1_axr7 mcasp4_ahclkx mcasp8_ahclkx vout2_de hdq0 vin2a_de0 vin1a_de0 clkout3 timer16 gpio6_20 Driver off
0x16A4 CTRL_CORE_PAD_MCASP1_ACLKX C14 mcasp1_aclkx vin1a_fld0 i2c3_sda pr2_mdio_mdclk pr2_pru1_gpi7 pr2_pru1_gpo7 gpio7_31 Driver off
0x16A8 CTRL_CORE_PAD_MCASP1_FSX D14 mcasp1_fsx vin1a_de0 i2c3_scl pr2_mdio_data gpio7_30 Driver off
0x16AC CTRL_CORE_PAD_MCASP1_ACLKR B14 mcasp1_aclkr mcasp7_axr2 vout2_d0 vin2a_d0 vin1a_d0 i2c4_sda gpio5_0 Driver off
0x16B0 CTRL_CORE_PAD_MCASP1_FSR J14 mcasp1_fsr mcasp7_axr3 vout2_d1 vin2a_d1 vin1a_d1 i2c4_scl gpio5_1 Driver off
0x16B4 CTRL_CORE_PAD_MCASP1_AXR0 G12 mcasp1_axr0 uart6_rxd vin1a_vsync0 i2c5_sda pr2_mii0_rxer pr2_pru1_gpi8 pr2_pru1_gpo8 gpio5_2 Driver off
0x16B8 CTRL_CORE_PAD_MCASP1_AXR1 F12 mcasp1_axr1 uart6_txd vin1a_hsync0 i2c5_scl pr2_mii_mt0_clk pr2_pru1_gpi9 pr2_pru1_gpo9 gpio5_3 Driver off
0x16BC CTRL_CORE_PAD_MCASP1_AXR2 G13 mcasp1_axr2 mcasp6_axr2 uart6_ctsn vout2_d2 vin2a_d2 vin1a_d2 gpio5_4 Driver off
0x16C0 CTRL_CORE_PAD_MCASP1_AXR3 J11 mcasp1_axr3 mcasp6_axr3 uart6_rtsn vout2_d3 vin2a_d3 vin1a_d3 gpio5_5 Driver off
0x16C4 CTRL_CORE_PAD_MCASP1_AXR4 E12 mcasp1_axr4 mcasp4_axr2 vout2_d4 vin2a_d4 vin1a_d4 gpio5_6 Driver off
0x16C8 CTRL_CORE_PAD_MCASP1_AXR5 F13 mcasp1_axr5 mcasp4_axr3 vout2_d5 vin2a_d5 vin1a_d5 gpio5_7 Driver off
0x16CC CTRL_CORE_PAD_MCASP1_AXR6 C12 mcasp1_axr6 mcasp5_axr2 vout2_d6 vin2a_d6 vin1a_d6 gpio5_8 Driver off
0x16D0 CTRL_CORE_PAD_MCASP1_AXR7 D12 mcasp1_axr7 mcasp5_axr3 vout2_d7 vin2a_d7 vin1a_d7 timer4 gpio5_9 Driver off
0x16D4 CTRL_CORE_PAD_MCASP1_AXR8 B12 mcasp1_axr8 mcasp6_axr0 spi3_sclk vin1a_d15 timer5 pr2_mii0_txen pr2_pru1_gpi10 pr2_pru1_gpo10 gpio5_10 Driver off
0x16D8 CTRL_CORE_PAD_MCASP1_AXR9 A11 mcasp1_axr9 mcasp6_axr1 spi3_d1 vin1a_d14 timer6 pr2_mii0_txd3 pr2_pru1_gpi11 pr2_pru1_gpo11 gpio5_11 Driver off
0x16DC CTRL_CORE_PAD_MCASP1_AXR10 B13 mcasp1_axr10 mcasp6_aclkx mcasp6_aclkr spi3_d0 vin1a_d13 timer7 pr2_mii0_txd2 pr2_pru1_gpi12 pr2_pru1_gpo12 gpio5_12 Driver off
0x16E0 CTRL_CORE_PAD_MCASP1_AXR11 A12 mcasp1_axr11 mcasp6_fsx mcasp6_fsr spi3_cs0 vin1a_d12 timer8 pr2_mii0_txd1 pr2_pru1_gpi13 pr2_pru1_gpo13 gpio4_17 Driver off
0x16E4 CTRL_CORE_PAD_MCASP1_AXR12 E14 mcasp1_axr12 mcasp7_axr0 spi3_cs1 vin1a_d11 timer9 pr2_mii0_txd0 pr2_pru1_gpi14 pr2_pru1_gpo14 gpio4_18 Driver off
0x16E8 CTRL_CORE_PAD_MCASP1_AXR13 A13 mcasp1_axr13 mcasp7_axr1 vin1a_d10 timer10 pr2_mii_mr0_clk pr2_pru1_gpi15 pr2_pru1_gpo15 gpio6_4 Driver off
0x16EC CTRL_CORE_PAD_MCASP1_AXR14 G14 mcasp1_axr14 mcasp7_aclkx mcasp7_aclkr vin1a_d9 timer11 pr2_mii0_rxdv pr2_pru1_gpi16 pr2_pru1_gpo16 gpio6_5 Driver off
0x16F0 CTRL_CORE_PAD_MCASP1_AXR15 F14 mcasp1_axr15 mcasp7_fsx mcasp7_fsr vin1a_d8 timer12 pr2_mii0_rxd3 pr2_pru0_gpi20 pr2_pru0_gpo20 gpio6_6 Driver off
0x16F4 CTRL_CORE_PAD_MCASP2_ACLKX A19 mcasp2_aclkx vin1a_d7 pr2_mii0_rxd2 pr2_pru0_gpi18 pr2_pru0_gpo18 Driver off
0x16F8 CTRL_CORE_PAD_MCASP2_FSX A18 mcasp2_fsx vin1a_d6 pr2_mii0_rxd1 pr2_pru0_gpi19 pr2_pru0_gpo19 Driver off
0x16FC CTRL_CORE_PAD_MCASP2_ACLKR E15 mcasp2_aclkr mcasp8_axr2 vout2_d8 vin2a_d8 vin1a_d8 Driver off
0x1700 CTRL_CORE_PAD_MCASP2_FSR A20 mcasp2_fsr mcasp8_axr3 vout2_d9 vin2a_d9 vin1a_d9 Driver off
0x1704 CTRL_CORE_PAD_MCASP2_AXR0 B15 mcasp2_axr0 vout2_d10 vin2a_d10 vin1a_d10 Driver off
0x1708 CTRL_CORE_PAD_MCASP2_AXR1 A15 mcasp2_axr1 vout2_d11 vin2a_d11 vin1a_d11 Driver off
0x170C CTRL_CORE_PAD_MCASP2_AXR2 C15 mcasp2_axr2 mcasp3_axr2 vin1a_d5 pr2_mii0_rxd0 pr2_pru0_gpi16 pr2_pru0_gpo16 gpio6_8 Driver off
0x1710 CTRL_CORE_PAD_MCASP2_AXR3 A16 mcasp2_axr3 mcasp3_axr3 vin1a_d4 pr2_mii0_rxlink pr2_pru0_gpi17 pr2_pru0_gpo17 gpio6_9 Driver off
0x1714 CTRL_CORE_PAD_MCASP2_AXR4 D15 mcasp2_axr4 mcasp8_axr0 vout2_d12 vin2a_d12 vin1a_d12 gpio1_4 Driver off
0x1718 CTRL_CORE_PAD_MCASP2_AXR5 B16 mcasp2_axr5 mcasp8_axr1 vout2_d13 vin2a_d13 vin1a_d13 gpio6_7 Driver off
0x171C CTRL_CORE_PAD_MCASP2_AXR6 B17 mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr vout2_d14 vin2a_d14 vin1a_d14 gpio2_29 Driver off
0x1720 CTRL_CORE_PAD_MCASP2_AXR7 A17 mcasp2_axr7 mcasp8_fsx mcasp8_fsr vout2_d15 vin2a_d15 vin1a_d15 gpio1_5 Driver off
0x1724 CTRL_CORE_PAD_MCASP3_ACLKX B18 mcasp3_aclkx mcasp3_aclkr mcasp2_axr12 uart7_rxd vin1a_d3 pr2_mii0_crs pr2_pru0_gpi12 pr2_pru0_gpo12 gpio5_13 Driver off
0x1728 CTRL_CORE_PAD_MCASP3_FSX F15 mcasp3_fsx mcasp3_fsr mcasp2_axr13 uart7_txd vin1a_d2 pr2_mii0_col pr2_pru0_gpi13 pr2_pru0_gpo13 gpio5_14 Driver off
0x172C CTRL_CORE_PAD_MCASP3_AXR0 B19 mcasp3_axr0 mcasp2_axr14 uart7_ctsn uart5_rxd vin1a_d1 pr2_mii1_rxer pr2_pru0_gpi14 pr2_pru0_gpo14 Driver off
0x1730 CTRL_CORE_PAD_MCASP3_AXR1 C17 mcasp3_axr1 mcasp2_axr15 uart7_rtsn uart5_txd vin1a_d0 vin1a_fld0 pr2_mii1_rxlink pr2_pru0_gpi15 pr2_pru0_gpo15 Driver off
0x1734 CTRL_CORE_PAD_MCASP4_ACLKX C18 mcasp4_aclkx mcasp4_aclkr spi3_sclk uart8_rxd i2c4_sda vout2_d16 vin2a_d16 vin1a_d16 vin1a_d15 Driver off
0x1738 CTRL_CORE_PAD_MCASP4_FSX A21 mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd i2c4_scl vout2_d17 vin2a_d17 vin1a_d17 vin1a_d14 Driver off
0x173C CTRL_CORE_PAD_MCASP4_AXR0 G16 mcasp4_axr0 spi3_d0 uart8_ctsn uart4_rxd vout2_d18 vin2a_d18 vin1a_d18 vin1a_d13 Driver off
0x1740 CTRL_CORE_PAD_MCASP4_AXR1 D17 mcasp4_axr1 spi3_cs0 uart8_rtsn uart4_txd vout2_d19 vin2a_d19 vin1a_d19 vin1a_d12 pr2_pru1_gpi0 pr2_pru1_gpo0 Driver off
0x1744 CTRL_CORE_PAD_MCASP5_ACLKX AA3 mcasp5_aclkx mcasp5_aclkr spi4_sclk uart9_rxd i2c5_sda vout2_d20 vin2a_d20 vin1a_d20 vin1a_d11 pr2_pru1_gpi1 pr2_pru1_gpo1 Driver off
0x1748 CTRL_CORE_PAD_MCASP5_FSX AB9 mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl vout2_d21 vin2a_d21 vin1a_d21 vin1a_d10 pr2_pru1_gpi2 pr2_pru1_gpo2 Driver off
0x174C CTRL_CORE_PAD_MCASP5_AXR0 AB3 mcasp5_axr0 spi4_d0 uart9_ctsn uart3_rxd vout2_d22 vin2a_d22 vin1a_d22 vin1a_d9 pr2_mdio_mdclk pr2_pru1_gpi3 pr2_pru1_gpo3 Driver off
0x1750 CTRL_CORE_PAD_MCASP5_AXR1 AA4 mcasp5_axr1 spi4_cs0 uart9_rtsn uart3_txd vout2_d23 vin2a_d23 vin1a_d23 vin1a_d8 pr2_mdio_data pr2_pru1_gpi4 pr2_pru1_gpo4 Driver off
0x1754 CTRL_CORE_PAD_MMC1_CLK W6 mmc1_clk gpio6_21 Driver off
0x1758 CTRL_CORE_PAD_MMC1_CMD Y6 mmc1_cmd gpio6_22 Driver off
0x175C CTRL_CORE_PAD_MMC1_DAT0 AA6 mmc1_dat0 gpio6_23 Driver off
0x1760 CTRL_CORE_PAD_MMC1_DAT1 Y4 mmc1_dat1 gpio6_24 Driver off
0x1764 CTRL_CORE_PAD_MMC1_DAT2 AA5 mmc1_dat2 gpio6_25 Driver off
0x1768 CTRL_CORE_PAD_MMC1_DAT3 Y3 mmc1_dat3 gpio6_26 Driver off
0x176C CTRL_CORE_PAD_MMC1_SDCD W7 mmc1_sdcd uart6_rxd i2c4_sda gpio6_27 Driver off
0x1770 CTRL_CORE_PAD_MMC1_SDWP Y9 mmc1_sdwp uart6_txd i2c4_scl gpio6_28 Driver off
0x1774 CTRL_CORE_PAD_GPIO6_10 AC5 gpio6_10 mdio_mclk i2c3_sda vin2b_hsync1 vin1a_clk0 ehrpwm2A pr2_mii_mt1_clk pr2_pru0_gpi0 pr2_pru0_gpo0 gpio6_10 Driver off
0x1778 CTRL_CORE_PAD_GPIO6_11 AB4 gpio6_11 mdio_d i2c3_scl vin2b_vsync1 vin1a_de0 ehrpwm2B pr2_mii1_txen pr2_pru0_gpi1 pr2_pru0_gpo1 gpio6_11 Driver off
0x177C CTRL_CORE_PAD_MMC3_CLK AD4 mmc3_clk vin2b_d7 vin1a_d7 ehrpwm2_tripzone_input pr2_mii1_txd3 pr2_pru0_gpi2 pr2_pru0_gpo2 gpio6_29 Driver off
0x1780 CTRL_CORE_PAD_MMC3_CMD AC4 mmc3_cmd spi3_sclk vin2b_d6 vin1a_d6 eCAP2_in_PWM2_out pr2_mii1_txd2 pr2_pru0_gpi3 pr2_pru0_gpo3 gpio6_30 Driver off
0x1784 CTRL_CORE_PAD_MMC3_DAT0 AC7 mmc3_dat0 spi3_d1 uart5_rxd vin2b_d5 vin1a_d5 eQEP3A_in pr2_mii1_txd1 pr2_pru0_gpi4 pr2_pru0_gpo4 gpio6_31 Driver off
0x1788 CTRL_CORE_PAD_MMC3_DAT1 AC6 mmc3_dat1 spi3_d0 uart5_txd vin2b_d4 vin1a_d4 eQEP3B_in pr2_mii1_txd0 pr2_pru0_gpi5 pr2_pru0_gpo5 gpio7_0 Driver off
0x178C CTRL_CORE_PAD_MMC3_DAT2 AC9 mmc3_dat2 spi3_cs0 uart5_ctsn vin2b_d3 vin1a_d3 eQEP3_index pr2_mii_mr1_clk pr2_pru0_gpi6 pr2_pru0_gpo6 gpio7_1 Driver off
0x1790 CTRL_CORE_PAD_MMC3_DAT3 AC3 mmc3_dat3 spi3_cs1 uart5_rtsn vin2b_d2 vin1a_d2 eQEP3_strobe pr2_mii1_rxdv pr2_pru0_gpi7 pr2_pru0_gpo7 gpio7_2 Driver off
0x1794 CTRL_CORE_PAD_MMC3_DAT4 AC8 mmc3_dat4 spi4_sclk uart10_rxd vin2b_d1 vin1a_d1 ehrpwm3A pr2_mii1_rxd3 pr2_pru0_gpi8 pr2_pru0_gpo8 gpio1_22 Driver off
0x1798 CTRL_CORE_PAD_MMC3_DAT5 AD6 mmc3_dat5 spi4_d1 uart10_txd vin2b_d0 vin1a_d0 ehrpwm3B pr2_mii1_rxd2 pr2_pru0_gpi9 pr2_pru0_gpo9 gpio1_23 Driver off
0x179C CTRL_CORE_PAD_MMC3_DAT6 AB8 mmc3_dat6 spi4_d0 uart10_ctsn vin2b_de1 vin1a_hsync0 ehrpwm3_tripzone_input pr2_mii1_rxd1 pr2_pru0_gpi10 pr2_pru0_gpo10 gpio1_24 Driver off
0x17A0 CTRL_CORE_PAD_MMC3_DAT7 AB5 mmc3_dat7 spi4_cs0 uart10_rtsn vin2b_clk1 vin1a_vsync0 eCAP3_in_PWM3_out pr2_mii1_rxd0 pr2_pru0_gpi11 pr2_pru0_gpo11 gpio1_25 Driver off
0x17A4 CTRL_CORE_PAD_SPI1_SCLK A25 spi1_sclk gpio7_7 Driver off
0x17A8 CTRL_CORE_PAD_SPI1_D1 F16 spi1_d1 gpio7_8 Driver off
0x17AC CTRL_CORE_PAD_SPI1_D0 B25 spi1_d0 gpio7_9 Driver off
0x17B0 CTRL_CORE_PAD_SPI1_CS0 A24 spi1_cs0 gpio7_10 Driver off
0x17B4 CTRL_CORE_PAD_SPI1_CS1 A22 spi1_cs1 sata1_led spi2_cs1 gpio7_11 Driver off
0x17B8 CTRL_CORE_PAD_SPI1_CS2 B21 spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 Driver off
0x17BC CTRL_CORE_PAD_SPI1_CS3 B20 spi1_cs3 uart4_txd mmc3_sdwp spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 Driver off
0x17C0 CTRL_CORE_PAD_SPI2_SCLK A26 spi2_sclk uart3_rxd gpio7_14 Driver off
0x17C4 CTRL_CORE_PAD_SPI2_D1 B22 spi2_d1 uart3_txd gpio7_15 Driver off
0x17C8 CTRL_CORE_PAD_SPI2_D0 G17 spi2_d0 uart3_ctsn uart5_rxd gpio7_16 Driver off
0x17CC CTRL_CORE_PAD_SPI2_CS0 B24 spi2_cs0 uart3_rtsn uart5_txd gpio7_17 Driver off
0x17D0 CTRL_CORE_PAD_DCAN1_TX G20 dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 Driver off
0x17D4 CTRL_CORE_PAD_DCAN1_RX G19 dcan1_rx uart8_txd mmc2_sdwp sata1_led hdmi1_cec gpio1_15 Driver off
0x17E0 CTRL_CORE_PAD_UART1_RXD B27 uart1_rxd mmc4_sdcd gpio7_22 Driver off
0x17E4 CTRL_CORE_PAD_UART1_TXD C26 uart1_txd mmc4_sdwp gpio7_23 Driver off
0x17E8 CTRL_CORE_PAD_UART1_CTSN E25 uart1_ctsn uart9_rxd mmc4_clk gpio7_24 Driver off
0x17EC CTRL_CORE_PAD_UART1_RTSN C27 uart1_rtsn uart9_txd mmc4_cmd gpio7_25 Driver off
0x17F0 CTRL_CORE_PAD_UART2_RXD D28 uart2_rxd uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd uart1_dcdn gpio7_26 Driver off
0x17F4 CTRL_CORE_PAD_UART2_TXD D26 uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 Driver off
0x17F8 CTRL_CORE_PAD_UART2_CTSN D27 uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 Driver off
0x17FC CTRL_CORE_PAD_UART2_RTSN C28 uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 Driver off
0x1800 CTRL_CORE_PAD_I2C1_SDA C21 i2c1_sda Driver off
0x1804 CTRL_CORE_PAD_I2C1_SCL C20 i2c1_scl Driver off
0x1808 CTRL_CORE_PAD_I2C2_SDA C25 i2c2_sda hdmi1_ddc_scl Driver off
0x180C CTRL_CORE_PAD_I2C2_SCL F17 i2c2_scl hdmi1_ddc_sda Driver off
0x1818 CTRL_CORE_PAD_WAKEUP0 AD17 Wakeup0 dcan1_rx gpio1_0 sys_nirq2 Driver off
0x1824 CTRL_CORE_PAD_WAKEUP3 AC16 Wakeup3 sys_nirq1 gpio1_3 dcan2_rx Driver off
0x1828 CTRL_CORE_PAD_ON_OFF Y11 on_off
0x182C CTRL_CORE_PAD_RTC_PORZ AB17 rtc_porz
0x1830 CTRL_CORE_PAD_TMS F18 tms
0x1834 CTRL_CORE_PAD_TDI D23 tdi gpio8_27
0x1838 CTRL_CORE_PAD_TDO F19 tdo gpio8_28
0x183C CTRL_CORE_PAD_TCLK E20 tclk
0x1840 CTRL_CORE_PAD_TRSTN D20 trstn
0x1844 CTRL_CORE_PAD_RTCK E18 rtck gpio8_29
0x1848 CTRL_CORE_PAD_EMU0 G21 emu0 gpio8_30
0x184C CTRL_CORE_PAD_EMU1 D24 emu1 gpio8_31
0x185C CTRL_CORE_PAD_RESETN E23 resetn
0x1860 CTRL_CORE_PAD_NMIN_DSP D21 nmin_dsp
0x1864 CTRL_CORE_PAD_RSTOUTN F23 rstoutn
  1. NA in table stands for Not Applicable.

4.4 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options.

Texas Instruments has developed an application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their device-based product design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pinmultiplexing configuration selected for a design only uses valid IO Sets supported by the device.

  1. SIGNAL NAME: The name of the signal passing through the pin.
  2. DESCRIPTION: Description of the signal
  3. TYPE: Signal direction and type:
    • I = Input
    • O = Output
    • IO = Input or output
    • D = Open drain
    • DS = Differential
    • A = Analog
    • PWR = Power
    • GND = Ground
  4. BALL: Associated ball(s) bottom

NOTE

For more information, see the Control Module / Control Module Register Manual section of the device TRM.

4.4.1 Video Input Ports (VIP)

CAUTION

The IO timings provided in Section 7, Timing Requirements and Switching Characteristics are valid only for VIN1 and VIN2 if signals within a single IOSET are used. The IOSETs are defined in Table 7-4.

NOTE

For more information, see the Video Input Port (VIP) section of the device TRM.

Table 4-4 VIP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Video Input 1
vin1a_clk0 Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. I AC5 / B11 / E17 / P1 / P4 / B26
vin1a_d0 Video Input 1 Port A Data input I AD6 / B7 / C17 / D18 / M6 / R6 / B14
vin1a_d1 Video Input 1 Port A Data input I AC8 / B19 / B8 / M2 / T9 / J14
vin1a_d2 Video Input 1 Port A Data input I A7 / AC3 / F15 / L5 / T6 / G13
vin1a_d3 Video Input 1 Port A Data input I A8 / AC9 / B18 / M1 / T7 / J11
vin1a_d4 Video Input 1 Port A Data input I A16 / AC6 / C9 / L6 / P6 / E12
vin1a_d5 Video Input 1 Port A Data input I A9 / AC7 / C15 / L4 / R9 / F13
vin1a_d6 Video Input 1 Port A Data input I A18 / AC4 / B9 / L3 / R5 / C12
vin1a_d7 Video Input 1 Port A Data input I A10 / A19 / AD4 / L2 / P5 / D12
vin1a_d8 Video Input 1 Port A Data input I AA4 / E8 / F14 / L1 / U2 / J4 / E15
vin1a_d9 Video Input 1 Port A Data input I AB3 / D9 / G14 / K2 / U1 / J6 / A20
vin1a_d10 Video Input 1 Port A Data input I A13 / AB9 / D7 / J1 / P3 / H4 / B15
vin1a_d11 Video Input 1 Port A Data input I AA3 / D8 / E14 / J2 / R2 / H5 / A15
vin1a_d12 Video Input 1 Port A Data input I A12 / A5 / D17 / H1 / K7 / D15
vin1a_d13 Video Input 1 Port A Data input I B13 / C6 / G16 / J3 / M7 / B16
vin1a_d14 Video Input 1 Port A Data input I A11 / A21 / C8 / H2 / J5 / B17
vin1a_d15 Video Input 1 Port A Data input I B12 / C18 / C7 / H3 / K6 / A17
vin1a_d16 Video Input 1 Port A Data input I F11 / R6 / C18
vin1a_d17 Video Input 1 Port A Data input I G10 / T9 / A21
vin1a_d18 Video Input 1 Port A Data input I F10 / T6 / G16
vin1a_d19 Video Input 1 Port A Data input I G11 / T7 / D17
vin1a_d20 Video Input 1 Port A Data input I E9 / P6 / AA3
vin1a_d21 Video Input 1 Port A Data input I F9 / R9 / AB9
vin1a_d22 Video Input 1 Port A Data input I F8 / R5 / AB3
vin1a_d23 Video Input 1 Port A Data input I E7 / P5 / AA4
vin1a_de0 Video Input 1 Port A Field ID input I AB4 / B10 / D14 / N9 / H6 / C23 / P7
vin1a_fld0 Video Input 1 Port A Field ID input I C14 / C17 / D11 / P9 / J7 / F21
vin1a_hsync0 Video Input 1 Port A Horizontal Sync input I AB8 / C11 / F12 / N7 / R3 / P7 / E21
vin1a_vsync0 Video Input 1 Port A Vertical Sync input I AB5 / E11 / G12 / R4 / T2 / N1 / F20
vin1b_clk1 Video Input 1 Port B Clock input I N9 / V1 / M4 / P7
vin1b_d0 Video Input 1 Port B Data input I R6 / U4 / K7
vin1b_d1 Video Input 1 Port B Data input I T9 / V2 / M7
vin1b_d2 Video Input 1 Port B Data input I T6 / Y1 / J5
vin1b_d3 Video Input 1 Port B Data input I T7 / W9 / K6
vin1b_d4 Video Input 1 Port B Data input I P6 / V9 / J7
vin1b_d5 Video Input 1 Port B Data input I R9 / U5 / J4
vin1b_d6 Video Input 1 Port B Data input I R5 / V5 / J6
vin1b_d7 Video Input 1 Port B Data input I P5 / V4 / H4
vin1b_de1 Video Input 1 Port B Field ID input I P9 / V7 / N6
vin1b_fld1 Video Input 1 Port B Field ID input I P4 / W2 / M4
vin1b_hsync1 Video Input 1 Port B Horizontal Sync input I N7 / U7 / H5
vin1b_vsync1 Video Input 1 Port B Vertical Sync input I R4 / V6 / H6
Video Input 2
vin2a_clk0 Video Input 2 Port A Clock input. I B11 / B26 / E1 / P4 / V1
vin2a_d0 Video Input 2 Port A Data input I B14 / B7 / F2 / R6 / U4
vin2a_d1 Video Input 2 Port A Data input I B8 / F3 / J14 / T9 / V2
vin2a_d2 Video Input 2 Port A Data input I A7 / D1 / G13 / T6 / Y1
vin2a_d3 Video Input 2 Port A Data input I A8 / E2 / J11 / T7 / W9
vin2a_d4 Video Input 2 Port A Data input I C9 / D2 / E12 / P6 / V9
vin2a_d5 Video Input 2 Port A Data input I A9 / F13 / F4 / R9 / U5
vin2a_d6 Video Input 2 Port A Data input I B9 / C1 / C12 / R5 / V5
vin2a_d7 Video Input 2 Port A Data input I A10 / D12 / E4 / P5 / V4
vin2a_d8 Video Input 2 Port A Data input I E15 / E8 / F5 / U2 / V3
vin2a_d9 Video Input 2 Port A Data input I A20 / D9 / E6 / U1 / Y2
vin2a_d10 Video Input 2 Port A Data input IO B15 / D3 / D7 / P3 / U6
vin2a_d11 Video Input 2 Port A Data input IO A15 / D8 / F6 / R2 / U3
vin2a_d12 Video Input 2 Port A Data input I A5 / D15 / D5 / K7
vin2a_d13 Video Input 2 Port A Data input I B16 / C2 / C6 / M7
vin2a_d14 Video Input 2 Port A Data input I B17 / C3 / C8 / J5
vin2a_d15 Video Input 2 Port A Data input I A17 / C4 / C7 / K6
vin2a_d16 Video Input 2 Port A Data input I B2 / C18 / F11
vin2a_d17 Video Input 2 Port A Data input I A21 / D6 / G10
vin2a_d18 Video Input 2 Port A Data input I C5 / F10 / G16
vin2a_d19 Video Input 2 Port A Data input I A3 / D17 / G11
vin2a_d20 Video Input 2 Port A Data input I AA3 / B3 / E9
vin2a_d21 Video Input 2 Port A Data input I AB9 / B4 / F9
vin2a_d22 Video Input 2 Port A Data input I AB3 / B5 / F8
vin2a_d23 Video Input 2 Port A Data input I A4 / AA4 / E7
vin2a_de0 Video Input 2 Port A Field ID input I B10 / C23 / G2 / H6 / P7 / V7
vin2a_fld0 Video Input 2 Port A Field ID input I D11 / F21 / G2 / H7 / J7 / P9 / W2
vin2a_hsync0 Video Input 2 Port A Horizontal Sync input I C11 / E21 / G1 / P7 / R3 / U7
vin2a_vsync0 Video Input 2 Port A Vertical Sync input I E11 / F20 / G6 / N1 / T2 / V6
vin2b_clk1 Video Input 2 Port B Clock input I AB5 / H7 / M4 / P7
vin2b_d0 Video Input 2 Port B Data input I A4 / AD6 / K7
vin2b_d1 Video Input 2 Port B Data input I AC8 / B5 / M7
vin2b_d2 Video Input 2 Port B Data input I AC3 / B4 / J5
vin2b_d3 Video Input 2 Port B Data input I AC9 / B3 / K6
vin2b_d4 Video Input 2 Port B Data input I A3 / AC6 / J7
vin2b_d5 Video Input 2 Port B Data input I AC7 / C5 / J4
vin2b_d6 Video Input 2 Port B Data input I AC4 / D6 / J6
vin2b_d7 Video Input 2 Port B Data input I AD4 / B2 / H4
vin2b_de1 Video Input 2 Port B Field ID input I AB8 / G2 / N6
vin2b_fld1 Video Input 2 Port B Field ID input I G2 / M4
vin2b_hsync1 Video Input 2 Port B Horizontal Sync input I AC5 / G1 / H5
vin2b_vsync1 Video Input 2 Port B Vertical Sync input I AB4 / G6 / H6

4.4.2 Display Subsystem – Video Output Ports

CAUTION

The IO timings provided in Section 7 Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 7-16.

Table 4-5 DSS Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
DPI Video Output 1
vout1_clk Video Output 1 Clock output O D11
vout1_de Video Output 1 Data Enable output O B10
vout1_fld Video Output 1 Field ID output. This signal is not used for embedded sync modes. O B11
vout1_hsync Video Output 1 Horizontal Sync output. This signal is not used for embedded sync modes. O C11
vout1_vsync Video Output 1 Vertical Sync output. This signal is not used for embedded sync modes. O E11
vout1_d0 Video Output 1 Data output O F11
vout1_d1 Video Output 1 Data output O G10
vout1_d2 Video Output 1 Data output O F10
vout1_d3 Video Output 1 Data output O G11
vout1_d4 Video Output 1 Data output O E9
vout1_d5 Video Output 1 Data output O F9
vout1_d6 Video Output 1 Data output O F8
vout1_d7 Video Output 1 Data output O E7
vout1_d8 Video Output 1 Data output O E8
vout1_d9 Video Output 1 Data output O D9
vout1_d10 Video Output 1 Data output O D7
vout1_d11 Video Output 1 Data output O D8
vout1_d12 Video Output 1 Data output O A5
vout1_d13 Video Output 1 Data output O C6
vout1_d14 Video Output 1 Data output O C8
vout1_d15 Video Output 1 Data output O C7
vout1_d16 Video Output 1 Data output O B7
vout1_d17 Video Output 1 Data output O B8
vout1_d18 Video Output 1 Data output O A7
vout1_d19 Video Output 1 Data output O A8
vout1_d20 Video Output 1 Data output O C9
vout1_d21 Video Output 1 Data output O A9
vout1_d22 Video Output 1 Data output O B9
vout1_d23 Video Output 1 Data output O A10
DPI Video Output 2
vout2_clk Video Output 2 Clock output O H7 / B26
vout2_de Video Output 2 Data Enable output O G2 / C23
vout2_fld Video Output 2 Field ID output. This signal is not used for embedded sync modes. O E1 / F21
vout2_hsync Video Output 2 Horizontal Sync output. This signal is not used for embedded sync modes. O G1 / E21
vout2_vsync Video Output 2 Vertical Sync output. This signal is not used for embedded sync modes. O G6 / F20
vout2_d0 Video Output 2 Data output O A4 / B14
vout2_d1 Video Output 2 Data output O B5 / J14
vout2_d2 Video Output 2 Data output O B4 / G13
vout2_d3 Video Output 2 Data output O B3 / J11
vout2_d4 Video Output 2 Data output O A3 / E12
vout2_d5 Video Output 2 Data output O C5 / F13
vout2_d6 Video Output 2 Data output O D6 / C12
vout2_d7 Video Output 2 Data output O B2 / D12
vout2_d8 Video Output 2 Data output O C4 / E15
vout2_d9 Video Output 2 Data output O C3 / A20
vout2_d10 Video Output 2 Data output O C2 / B15
vout2_d11 Video Output 2 Data output O D5 / A15
vout2_d12 Video Output 2 Data output O F6 / D15
vout2_d13 Video Output 2 Data output O D3 / B16
vout2_d14 Video Output 2 Data output O E6 / B17
vout2_d15 Video Output 2 Data output O F5 / A17
vout2_d16 Video Output 2 Data output O E4 / C18
vout2_d17 Video Output 2 Data output O C1 / A21
vout2_d18 Video Output 2 Data output O F4 / G16
vout2_d19 Video Output 2 Data output O D2 / D17
vout2_d20 Video Output 2 Data output O E2 / AA3
vout2_d21 Video Output 2 Data output O D1 / AB9
vout2_d22 Video Output 2 Data output O F3 / AB3
vout2_d23 Video Output 2 Data output O F2 / AA4
DPI Video Output 3
vout3_clk Video Output 3 Clock output O P1
vout3_d0 Video Output 3 Data output O M6
vout3_d1 Video Output 3 Data output O M2
vout3_d2 Video Output 3 Data output O L5
vout3_d3 Video Output 3 Data output O M1
vout3_d4 Video Output 3 Data output O L6
vout3_d5 Video Output 3 Data output O L4
vout3_d6 Video Output 3 Data output O L3
vout3_d7 Video Output 3 Data output O L2
vout3_d8 Video Output 3 Data output O L1
vout3_d9 Video Output 3 Data output O K2
vout3_d10 Video Output 3 Data output O J1
vout3_d11 Video Output 3 Data output O J2
vout3_d12 Video Output 3 Data output O H1
vout3_d13 Video Output 3 Data output O J3
vout3_d14 Video Output 3 Data output O H2
vout3_d15 Video Output 3 Data output O H3
vout3_d16 Video Output 3 Data output O R6
vout3_d17 Video Output 3 Data output O T9
vout3_d18 Video Output 3 Data output O T6
vout3_d19 Video Output 3 Data output O T7
vout3_d20 Video Output 3 Data output O P6
vout3_d21 Video Output 3 Data output O R9
vout3_d22 Video Output 3 Data output O R5
vout3_d23 Video Output 3 Data output O P5
vout3_de Video Output 3 Data Enable output O N9
vout3_fld Video Output 3 Field ID output. This signal is not used for embedded sync modes. O P9
vout3_hsync Video Output 3 Horizontal Sync output. This signal is not used for embedded sync modes. O N7
vout3_vsync Video Output 3 Vertical Sync output. This signal is not used for embedded sync modes. O R4

4.4.3 Display Subsystem – High-Definition Multimedia Interface (HDMI)

NOTE

For more information, see the Display Subsystem / Display Subsystem Overview of the device TRM.

Table 4-6 HDMI Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
hdmi1_cec HDMI consumer electronic control IOD B20/ G19
hdmi1_hpd HDMI display hot plug detect IO B21/ G20
hdmi1_ddc_scl HDMI display data channel clock IOD C25
hdmi1_ddc_sda HDMI display data channel data IOD F17
hdmi1_clockx HDMI clock differential positive or negative ODS AG16
hdmi1_clocky HDMI clock differential positive or negative ODS AH16
hdmi1_data2x HDMI data 2 differential positive or negative ODS AG19
hdmi1_data2y HDMI data 2 differential positive or negative ODS AH19
hdmi1_data1x HDMI data 1 differential positive or negative ODS AG18
hdmi1_data1y HDMI data 1 differential positive or negative ODS AH18
hdmi1_data0x HDMI data 0 differential positive or negative ODS AG17
hdmi1_data0y HDMI data 0 differential positive or negative ODS AH17

4.4.4 Camera Serial Interface 2 CAL bridge (CSI2)

NOTE

For more information, see the CAL Subsystem / CAL Subsystem Overview of the device TRM.

Table 4-7 CSI 2 Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
csi2_0_dx0 Serial data/clock input - line 0 (position 1) I AE1
csi2_0_dy0 Serial data/clock input - line 0 (position 1) I AD2
csi2_0_dx1 Serial data/clock input - line 1 (position 2) I AF1
csi2_0_dy1 Serial data/clock input - line 1 (position 2) I AE2
csi2_0_dx2 Serial data/clock input - line 2 (position 3) I AF2
csi2_0_dy2 Serial data/clock input - line 2 (position 3) I AF3
csi2_0_dx3 Serial data/clock input - line 3 (position 4) I AH4
csi2_0_dy3 Serial data/clock input - line 3 (position 4) I AG4
csi2_0_dx4 Serial data input only - line 4 (position 5) (1) I AH3
csi2_0_dy4 Serial data input only - line 4 (position 5) (1) I AG3
csi2_1_dx0 Serial data/clock input - line 0 (position 1) I AG5
csi2_1_dy0 Serial data/clock input - line 0 (position 1) I AH5
csi2_1_dx1 Serial data/clock input - line 1 (position 2) I AG6
csi2_1_dy1 Serial data/clock input - line 1 (position 2) I AH6
csi2_1_dx2 Serial data/clock input - line 2 (position 3) I AH7
csi2_1_dy2 Serial data/clock input - line 2 (position 3) I AG7
  1. Line 4 (position 5) supports only data. For more information see CAL Subsystem of the device TRM.

4.4.5 External Memory Interface (EMIF)

NOTE

For more information, see the Memory Subsystem / EMIF Controller section of the device TRM.

NOTE

Dual rank support is not available on this device, but signal names are retained for consistency with the AM57xx family of devices.

NOTE

The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-8, EMIF Signal Descriptions, not to be confused with DDR1 type of SDRAM memories.

Table 4-8 EMIF Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
ddr1_csn0 EMIF1 Chip Select 0 O AH23
ddr1_csn1 EMIF1 Chip Select 1 O AB16
ddr1_cke EMIF1 Clock Enable O AG22
ddr1_ck EMIF1 Clock O AG24
ddr1_nck EMIF1 Negative Clock O AH24
ddr1_odt0 EMIF1 On-Die Termination for Chip Select 0 O AE20
ddr1_odt1 EMIF1 On-Die Termination for Chip Select 1 O AC17
ddr1_casn EMIF1 Column Address Strobe O AC18
ddr1_rasn EMIF1 Row Address Strobe O AF20
ddr1_wen EMIF1 Write Enable O AH21
ddr1_rst EMIF1 Reset output (DDR3-SDRAM only) O AG21
ddr1_ba0 EMIF1 Bank Address O AF17
ddr1_ba1 EMIF1 Bank Address O AE18
ddr1_ba2 EMIF1 Bank Address O AB18
ddr1_a0 EMIF1 Address Bus O AD20
ddr1_a1 EMIF1 Address Bus O AC19
ddr1_a2 EMIF1 Address Bus O AC20
ddr1_a3 EMIF1 Address Bus O AB19
ddr1_a4 EMIF1 Address Bus O AF21
ddr1_a5 EMIF1 Address Bus O AH22
ddr1_a6 EMIF1 Address Bus O AG23
ddr1_a7 EMIF1 Address Bus O AE21
ddr1_a8 EMIF1 Address Bus O AF22
ddr1_a9 EMIF1 Address Bus O AE22
ddr1_a10 EMIF1 Address Bus O AD21
ddr1_a11 EMIF1 Address Bus O AD22
ddr1_a12 EMIF1 Address Bus O AC21
ddr1_a13 EMIF1 Address Bus O AF18
ddr1_a14 EMIF1 Address Bus O AE17
ddr1_a15 EMIF1 Address Bus O AD18
ddr1_d0 EMIF1 Data Bus IO AF25
ddr1_d1 EMIF1 Data Bus IO AF26
ddr1_d2 EMIF1 Data Bus IO AG26
ddr1_d3 EMIF1 Data Bus IO AH26
ddr1_d4 EMIF1 Data Bus IO AF24
ddr1_d5 EMIF1 Data Bus IO AE24
ddr1_d6 EMIF1 Data Bus IO AF23
ddr1_d7 EMIF1 Data Bus IO AE23
ddr1_d8 EMIF1 Data Bus IO AC23
ddr1_d9 EMIF1 Data Bus IO AF27
ddr1_d10 EMIF1 Data Bus IO AG27
ddr1_d11 EMIF1 Data Bus IO AF28
ddr1_d12 EMIF1 Data Bus IO AE26
ddr1_d13 EMIF1 Data Bus IO AC25
ddr1_d14 EMIF1 Data Bus IO AC24
ddr1_d15 EMIF1 Data Bus IO AD25
ddr1_d16 EMIF1 Data Bus IO V20
ddr1_d17 EMIF1 Data Bus IO W20
ddr1_d18 EMIF1 Data Bus IO AB28
ddr1_d19 EMIF1 Data Bus IO AC28
ddr1_d20 EMIF1 Data Bus IO AC27
ddr1_d21 EMIF1 Data Bus IO Y19
ddr1_d22 EMIF1 Data Bus IO AB27
ddr1_d23 EMIF1 Data Bus IO Y20
ddr1_d24 EMIF1 Data Bus IO AA23
ddr1_d25 EMIF1 Data Bus IO Y22
ddr1_d26 EMIF1 Data Bus IO Y23
ddr1_d27 EMIF1 Data Bus IO AA24
ddr1_d28 EMIF1 Data Bus IO Y24
ddr1_d29 EMIF1 Data Bus IO AA26
ddr1_d30 EMIF1 Data Bus IO AA25
ddr1_d31 EMIF1 Data Bus IO AA28
ddr1_ecc_d0 EMIF1 ECC Data Bus IO W22
ddr1_ecc_d1 EMIF1 ECC Data Bus IO V23
ddr1_ecc_d2 EMIF1 ECC Data Bus IO W19
ddr1_ecc_d3 EMIF1 ECC Data Bus IO W23
ddr1_ecc_d4 EMIF1 ECC Data Bus IO Y25
ddr1_ecc_d5 EMIF1 ECC Data Bus IO V24
ddr1_ecc_d6 EMIF1 ECC Data Bus IO V25
ddr1_ecc_d7 EMIF1 ECC Data Bus IO Y26
ddr1_dqm0 EMIF1 Data Mask O AD23
ddr1_dqm1 EMIF1 Data Mask O AB23
ddr1_dqm2 EMIF1 Data Mask O AC26
ddr1_dqm3 EMIF1 Data Mask O AA27
ddr1_dqm_ecc EMIF1 ECC Data Mask O V26
ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AH25
ddr1_dqsn0 Data strobe 0 invert IO AG25
ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AE27
ddr1_dqsn1 Data strobe 1 invert IO AE28
ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AD27
ddr1_dqsn2 Data strobe 2 invert IO AD28
ddr1_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO Y28
ddr1_dqsn3 Data strobe 3 invert IO Y27
ddr1_dqs_ecc EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading. IO V27
ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe IO V28
ddr1_vref0 Reference Power Supply EMIF1 A Y18

4.4.6 General-Purpose Memory Controller (GPMC)

NOTE

For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the device TRM.

Table 4-9 GPMC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
gpmc_ad0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode IO M6
gpmc_ad1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode IO M2
gpmc_ad2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode IO L5
gpmc_ad3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode IO M1
gpmc_ad4 GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode IO L6
gpmc_ad5 GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode IO L4
gpmc_ad6 GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode IO L3
gpmc_ad7 GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode IO L2
gpmc_ad8 GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode IO L1
gpmc_ad9 GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode IO K2
gpmc_ad10 GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode IO J1
gpmc_ad11 GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode IO J2
gpmc_ad12 GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode IO H1
gpmc_ad13 GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode IO J3
gpmc_ad14 GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode IO H2
gpmc_ad15 GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode IO H3
gpmc_a0 GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories O R6 / P4
gpmc_a1 GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode O T9 / P1
gpmc_a2 GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode O T6 / N1
gpmc_a3 GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode O T7 / M4
gpmc_a4 GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D multiplexed mode O P6
gpmc_a5 GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D multiplexed mode O R9
gpmc_a6 GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D multiplexed mode O R5
gpmc_a7 GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D multiplexed mode O P5
gpmc_a8 GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D multiplexed mode O N7
gpmc_a9 GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D multiplexed mode O R4
gpmc_a10 GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D multiplexed mode O N9
gpmc_a11 GPMC address 11 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O P9
gpmc_a12 GPMC address 12 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O P4
gpmc_a13 GPMC address 13 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O R3 / K7 / P2
gpmc_a14 GPMC address 14 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O T2 / M7 / P1
gpmc_a15 GPMC address 15 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O U2 / J5 / N2
gpmc_a16 GPMC address 16 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O U1 / K6 / R6
gpmc_a17 GPMC address 17 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O P3 / J7 / E1
gpmc_a18 GPMC address 18 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O R2 / J4 / H7
gpmc_a19 GPMC address 19 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O K7 / J6
gpmc_a20 GPMC address 20 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O M7 / H4
gpmc_a21 GPMC address 21 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O J5 / H5
gpmc_a22 GPMC address 22 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O K6 / H6
gpmc_a23 GPMC address 23 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O F6 / J7 / N1 / P2
gpmc_a24 GPMC address 24 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O D3 / J4 / P1
gpmc_a25 GPMC address 25 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O E6 / J6 / N2
gpmc_a26 GPMC address 26 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O F5 / H4 / R6
gpmc_a27 GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D multiplexed mode O G1 / H5 / E1 / H7
gpmc_cs0 GPMC Chip Select 0 (active low) O T1
gpmc_cs1 GPMC Chip Select 1 (active low) O H6
gpmc_cs2 GPMC Chip Select 2 (active low) O P2
gpmc_cs3 GPMC Chip Select 3 (active low) O P1
gpmc_cs4 GPMC Chip Select 4 (active low) O N6
gpmc_cs5 GPMC Chip Select 5 (active low) O M4
gpmc_cs6 GPMC Chip Select 6 (active low) O N1
gpmc_cs7 GPMC Chip Select 7 (active low) O P7
gpmc_clk(1)(2) GPMC Clock output IO P7
gpmc_advn_ale GPMC address valid active low or address latch enable O N1
gpmc_oen_ren GPMC output enable active low or read enable O M5
gpmc_wen GPMC write enable active low O M3
gpmc_ben0 GPMC lower-byte enable active low O N6
gpmc_ben1 GPMC upper-byte enable active low O M4
gpmc_wait0 GPMC external indication of wait 0 I N2
gpmc_wait1 GPMC external indication of wait 1 I P7 / N1
  1. This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
  2. The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the associated timing. See Table 7-23 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-25 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.

4.4.7 Timers

NOTE

For more information, see the Timers section of the device TRM.

Table 4-10 Timers Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
timer1 PWM output/event trigger input IO M4 / E21
timer2 PWM output/event trigger input IO N6 / F20
timer3 PWM output/event trigger input IO N1 / F21
timer4 PWM output/event trigger input IO P7 / D12
timer5 PWM output/event trigger input IO U2 / B12
timer6 PWM output/event trigger input IO T2 / A11
timer7 PWM output/event trigger input IO R3 / B13
timer8 PWM output/event trigger input IO P4 / A12
timer9 PWM output/event trigger input IO P9 / E14
timer10 PWM output/event trigger input IO N9 / A13
timer11 PWM output/event trigger input IO R4 / G14
timer12 PWM output/event trigger input IO N7 / F14
timer13 PWM output/event trigger input IO D18
timer14 PWM output/event trigger input IO E17
timer15 PWM output/event trigger input IO AC10 / B26
timer16 PWM output/event trigger input IO AB10 / C23

4.4.8 Inter-Integrated Circuit Interface (I2C)

NOTE

For more information, see the Serial Communication Interface / Multimaster High-Speed I2C Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM.

NOTE

I2C1 and I2C2 do NOT support HS-mode.

Table 4-11 I2C Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Inter-Integrated Circuit Interface 1 (I2C1)
i2c1_scl I2C1 Clock IOD C20
i2c1_sda I2C1 Data IOD C21
Inter-Integrated Circuit Interface 2 (I2C2)
i2c2_scl I2C2 Clock IOD F17
i2c2_sda I2C2 Data IOD C25
Inter-Integrated Circuit Interface 3 (I2C3)
i2c3_scl I2C3 Clock IOD P7/ D14/ AB4/ F20
i2c3_sda I2C3 Data IOD N1/ C14/ AC5/ E21
Inter-Integrated Circuit Interface 4 (I2C4)
i2c4_scl I2C4 Clock IOD R6/ J14/ A21/ Y9
i2c4_sda I2C4 Data IOD T9/ B14/ C18/ W7
Inter-Integrated Circuit Interface 5 (I2C5)
i2c5_scl I2C5 Clock IOD AB9/ P6/F12
i2c5_sda I2C5 Data IOD AA3/ R9/G12

4.4.9 HDQ / 1-Wire Interface (HDQ1W)

NOTE

For more information, see the Serial Communication Interface / HDQ/1-Wire section of the device TRM.

Table 4-12 HDQ / 1-Wire Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
hdq0 HDQ or 1-wire protocol single interface pin IOD D18/ C23

4.4.10 Universal Asynchronous Receiver Transmitter (UART)

NOTE

For more information see the Serial Communication Interface / UART/IrDA/CIR section of the device TRM.

Table 4-13 UART Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Universal Asynchronous Receiver/Transmitter 1 (UART1)
uart1_dcdn UART1 Data Carrier Detect active low I D28
uart1_dsrn UART1 Data Set Ready Active Low I D26
uart1_dtrn UART1 Data Terminal Ready Active Low O D27
uart1_rin UART1 Ring Indicator I C28
uart1_rxd UART1 Receive Data I B27
uart1_txd UART1 Transmit Data O C26
uart1_ctsn UART1 clear to send active low I E25
uart1_rtsn UART1 request to send active low O C27
Universal Asynchronous Receiver/Transmitter 2 (UART2)
uart2_rxd UART2 Receive Data I D28
uart2_txd UART2 Transmit Data O D26
uart2_ctsn UART2 clear to send active low I D27
uart2_rtsn UART2 request to send active low O C28
Universal Asynchronous Receiver/Transmitter 3 (UART3)/IrDA
uart3_rxd UART3 Receive Data I V2/ AB3/ A26 / D27
uart3_txd UART3 Transmit Data O Y1/ AA4/ B22/ C28
uart3_ctsn UART3 clear to send active low I U4/ W9/ G17/ D28
uart3_rtsn UART3 request to send active low O V1/ V9/ D26/ B24
uart3_rctx Remote control data O D28
uart3_sd Infrared transceiver configure/shutdown O D26
uart3_irrx Infrared data input. Also functions as uart3_rxd Receive Data Input when IrDA mode is not used. I D27
uart3_irtx Infrared data output O C28
Universal Asynchronous Receiver/Transmitter 4 (UART4)
uart4_rxd UART4 Receive Data I V7/ G16/ B21
uart4_txd UART4 Transmit Data O U7/ D17/ B20
uart4_ctsn UART4 clear to send active low I V6
uart4_rtsn UART4 request to send active low O U6
Universal Asynchronous Receiver/Transmitter 5 (UART5)
uart5_rxd UART5 Receive Data I R6/ F11/ B19/ AC7/ G17
uart5_txd UART5 Transmit Data O T9/ G10/ C17/ AC6/ B24
uart5_ctsn UART5 clear to send active low I T6 / AC9
uart5_rtsn UART5 request to send active low O T7 / AC3
Universal Asynchronous Receiver/Transmitter 6 (UART6)
uart6_rxd UART6 Receive Data I P6/ E8/ G12/ W7
uart6_txd UART6 Transmit Data O R9/ D9/ F12/ Y9
uart6_ctsn UART6 clear to send active low I R5 / G13
uart6_rtsn UART6 request to send active low O P5 / J11
Universal Asynchronous Receiver/Transmitter 7 (UART7)
uart7_rxd UART7 Receive Data I B18 / B7 / T6
uart7_txd UART7 Transmit Data O B8 / F15 / T7
uart7_ctsn UART7 clear to send active low I B19
uart7_rtsn UART7 request to send active low O C17
Universal Asynchronous Receiver/Transmitter 8 (UART8)
uart8_rxd UART8 Receive Data I C18 / G20 / R5
uart8_txd UART8 Transmit Data O A21 / G19 / P5
uart8_ctsn UART8 clear to send active low I G16
uart8_rtsn UART8 request to send active low O D17
Universal Asynchronous Receiver/Transmitter 9 (UART9)
uart9_rxd UART9 Receive Data I G1/ AA3/ E25
uart9_txd UART9 Transmit Data O G6/ AB9/ C27
uart9_ctsn UART9 clear to send active low I F2 / AB3
uart9_rtsn UART9 request to send active low O F3/ AA4
Universal Asynchronous Receiver/Transmitter 10 (UART10)
uart10_rxd UART10 Receive Data I D1/ E21/ AC8/ D27
uart10_txd UART10 Transmit Data O E2/ F20/ AD6/ C28
uart10_ctsn UART10 clear to send active low I D2 / AB8
uart10_rtsn UART10 request to send active low O F4 / AB5

4.4.11 Multichannel Serial Peripheral Interface (McSPI)

CAUTION

The I/O timing provided in Section 7, Timing Requirements and Switching Characteristics are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETS are defined in Table 7-42.

NOTE

For more information, see the Serial Communication Interface / Multichannel Serial Peripheral Interface (McSPI) section of the device TRM.

Table 4-14 SPI Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Serial Peripheral Interface 1
spi1_sclk(1) SPI1 Clock IO A25
spi1_d1 SPI1 Data. Can be configured as either MISO or MOSI. IO F16
spi1_d0 SPI1 Data. Can be configured as either MISO or MOSI. IO B25
spi1_cs0 SPI1 Chip Select IO A24
spi1_cs1 SPI1 Chip Select IO A22
spi1_cs2 SPI1 Chip Select IO B21
spi1_cs3 SPI1 Chip Select IO B20
Serial Peripheral Interface 2
spi2_sclk(1) SPI2 Clock IO A26
spi2_d1 SPI2 Data. Can be configured as either MISO or MOSI. IO B22
spi2_d0 SPI2 Data. Can be configured as either MISO or MOSI. IO G17
spi2_cs0 SPI2 Chip Select IO B24
spi2_cs1 SPI2 Chip Select IO A22
spi2_cs2 SPI2 Chip Select IO B21
spi2_cs3 SPI2 Chip Select IO B20
Serial Peripheral Interface 3
spi3_sclk(1) SPI3 Clock IO AC4 / B12 / C18 / E11 / V2
spi3_d1 SPI3 Data. Can be configured as either MISO or MOSI. IO A11 / A21 / AC7 / B10 / Y1
spi3_d0 SPI3 Data. Can be configured as either MISO or MOSI. IO AC6 / B13 / C11 / G16 / W9
spi3_cs0 SPI3 Chip Select IO A12 / AC9 / D11 / D17 / V9
spi3_cs1 SPI3 Chip Select IO AC3 / B11 / E14
spi3_cs2 SPI3 Chip Select IO F11
spi3_cs3 SPI3 Chip Select IO A10
Serial Peripheral Interface 4
spi4_sclk(1) SPI4 Clock IO N7/ G1/ AA3/ V7/ AC8
spi4_d1 SPI4 Data. Can be configured as either MISO or MOSI. IO R4/ G6/ AB9/ U7/ AD6
spi4_d0 SPI4 Data. Can be configured as either MISO or MOSI. IO N9/ F2/ AB3/ V6/ AB8
spi4_cs0 SPI4 Chip Select IO P9/ F3/ AA4/ U6/ AB5
spi4_cs1 SPI4 Chip Select IO P4 / Y1
spi4_cs2 SPI4 Chip Select IO R3 / W9
spi4_cs3 SPI4 Chip Select IO T2 / V9
  1. This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

4.4.12 Quad Serial Peripheral Interface (QSPI)

NOTE

For more information see the Serial Communication Interface / Quad Serial Peripheral Interface section of the device TRM.

Table 4-15 QSPI Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
qspi1_sclk QSPI1 Serial Clock IO R2
qspi1_rtclk QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer to PCB Guidelines for QSPI1 I R3
qspi1_d0 QSPI1 Data[0].This pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase. IO U1
qspi1_d1 QSPI1 Data[1].Input read data in all modes. IO P3
qspi1_d2 QSPI1 Data[2].This pin is used only in quad read mode as input data pin during read phase IO U2
qspi1_d3 QSPI1 Data[3].This pin is used only in quad read mode as input data pin during read phase IO T2
qspi1_cs0 QSPI1 Chip Select[0].This pin is Used for QSPI1 boot modes. O P2
qspi1_cs1 QSPI1 Chip Select[1] O P1
qspi1_cs2 QSPI1 Chip Select[2] O T7
qspi1_cs3 QSPI1 Chip Select[3] O P6

4.4.13 Multichannel Audio Serial Port (McASP)

NOTE

For more information, see the Serial Communication Interface / Multichannel Audio Serial Port (McASP) section of the device TRM.

Table 4-16 McASP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Multichannel Audio Serial Port 1
mcasp1_axr0 McASP1 Transmit/Receive Data IO G12
mcasp1_axr1 McASP1 Transmit/Receive Data IO F12
mcasp1_axr2 McASP1 Transmit/Receive Data IO G13
mcasp1_axr3 McASP1 Transmit/Receive Data IO J11
mcasp1_axr4 McASP1 Transmit/Receive Data IO D18/ E12
mcasp1_axr5 McASP1 Transmit/Receive Data IO E17 / F13
mcasp1_axr6 McASP1 Transmit/Receive Data IO B26 / C12
mcasp1_axr7 McASP1 Transmit/Receive Data IO C23 / D12
mcasp1_axr8 McASP1 Transmit/Receive Data IO E21 / B12
mcasp1_axr9 McASP1 Transmit/Receive Data IO F20/ A11
mcasp1_axr10 McASP1 Transmit/Receive Data IO F21 / B13
mcasp1_axr11 McASP1 Transmit/Receive Data IO A12
mcasp1_axr12 McASP1 Transmit/Receive Data IO E14
mcasp1_axr13 McASP1 Transmit/Receive Data IO A13
mcasp1_axr14 McASP1 Transmit/Receive Data IO G14
mcasp1_axr15 McASP1 Transmit/Receive Data IO F14
mcasp1_fsx McASP1 Transmit Frame Sync IO D14
mcasp1_aclkr(1) McASP1 Receive Bit Clock IO B14
mcasp1_fsr McASP1 Receive Frame Sync IO J14
mcasp1_ahclkx McASP1 Transmit High-Frequency Master Clock O D18
mcasp1_aclkx(1) McASP1 Transmit Bit Clock IO C14
Multichannel Audio Serial Port 2
mcasp2_axr0 McASP2 Transmit/Receive Data IO B15
mcasp2_axr1 McASP2 Transmit/Receive Data IO A15
mcasp2_axr2 McASP2 Transmit/Receive Data IO C15
mcasp2_axr3 McASP2 Transmit/Receive Data IO A16
mcasp2_axr4 McASP2 Transmit/Receive Data IO D15
mcasp2_axr5 McASP2 Transmit/Receive Data IO B16
mcasp2_axr6 McASP2 Transmit/Receive Data IO B17
mcasp2_axr7 McASP2 Transmit/Receive Data IO A17
mcasp2_axr8 McASP2 Transmit/Receive Data IO D18
mcasp2_axr9 McASP2 Transmit/Receive Data IO E17
mcasp2_axr10 McASP2 Transmit/Receive Data IO B26
mcasp2_axr11 McASP2 Transmit/Receive Data IO C23
mcasp2_axr12 McASP2 Transmit/Receive Data IO B18
mcasp2_axr13 McASP2 Transmit/Receive Data IO F15
mcasp2_axr14 McASP2 Transmit/Receive Data IO B19
mcasp2_axr15 McASP2 Transmit/Receive Data IO C17
mcasp2_fsx McASP2 Transmit Frame Sync IO A18
mcasp2_aclkr(1) McASP2 Receive Bit Clock IO E15
mcasp2_fsr McASP2 Receive Frame Sync IO A20
mcasp2_ahclkx McASP2 Transmit High-Frequency Master Clock O E17
mcasp2_aclkx(1) McASP2 Transmit Bit Clock IO A19
Multichannel Audio Serial Port 3
mcasp3_axr0 McASP3 Transmit/Receive Data IO B19
mcasp3_axr1 McASP3 Transmit/Receive Data IO C17
mcasp3_axr2 McASP3 Transmit/Receive Data IO C15
mcasp3_axr3 McASP3 Transmit/Receive Data IO A16
mcasp3_fsx McASP3 Transmit Frame Sync IO F15
mcasp3_ahclkx McASP3 Transmit High-Frequency Master Clock O B26
mcasp3_aclkx(1) McASP3 Transmit Bit Clock IO B18
mcasp3_aclkr(1) McASP3 Receive Bit Clock IO B18
mcasp3_fsr McASP3 Receive Frame Sync IO F15
Multichannel Audio Serial Port 4
mcasp4_axr0 McASP4 Transmit/Receive Data IO G16
mcasp4_axr1 McASP4 Transmit/Receive Data IO D17
mcasp4_axr2 McASP4 Transmit/Receive Data IO E12
mcasp4_axr3 McASP4 Transmit/Receive Data IO F13
mcasp4_fsx McASP4 Transmit Frame Sync IO A21
mcasp4_ahclkx McASP4 Transmit High-Frequency Master Clock O C23
mcasp4_aclkx(1) McASP4 Transmit Bit Clock IO C18
mcasp4_aclkr(1) McASP4 Receive Bit Clock IO C18
mcasp4_fsr McASP4 Receive Frame Sync IO A21
Multichannel Audio Serial Port 5
mcasp5_axr0 McASP5 Transmit/Receive Data IO AB3
mcasp5_axr1 McASP5 Transmit/Receive Data IO AA4
mcasp5_axr2 McASP5 Transmit/Receive Data IO C12
mcasp5_axr3 McASP5 Transmit/Receive Data IO D12
mcasp5_fsx McASP5 Transmit Frame Sync IO AB9
mcasp5_ahclkx McASP5 Transmit High-Frequency Master Clock O D18
mcasp5_aclkx(1) McASP5 Transmit Bit Clock IO AA3
mcasp5_aclkr(1) McASP5 Receive Bit Clock IO AA3
mcasp5_fsr McASP5 Receive Frame Sync IO AB9
Multichannel Audio Serial Port 6
mcasp6_axr0 McASP6 Transmit/Receive Data IO B12
mcasp6_axr1 McASP6 Transmit/Receive Data IO A11
mcasp6_axr2 McASP6 Transmit/Receive Data IO G13
mcasp6_axr3 McASP6 Transmit/Receive Data IO J11
mcasp6_ahclkx McASP6 Transmit High-Frequency Master Clock O E17
mcasp6_aclkx(1) McASP6 Transmit Bit Clock IO B13
mcasp6_fsx McASP6 Transmit Frame Sync IO A12
mcasp6_aclkr(1) McASP6 Receive Bit Clock IO B13
mcasp6_fsr McASP6 Receive Frame Sync IO A12
Multichannel Audio Serial Port 7
mcasp7_axr0 McASP7 Transmit/Receive Data IO E14
mcasp7_axr1 McASP7 Transmit/Receive Data IO A13
mcasp7_axr2 McASP7 Transmit/Receive Data IO B14
mcasp7_axr3 McASP7 Transmit/Receive Data IO J14
mcasp7_ahclkx McASP7 Transmit High-Frequency Master Clock O B26
mcasp7_aclkx(1) McASP7 Transmit Bit Clock IO G14
mcasp7_fsx McASP7 Transmit Frame Sync IO F14
mcasp7_aclkr(1) McASP7 Receive Bit Clock IO G14
mcasp7_fsr McASP7 Receive Frame Sync IO F14
Multichannel Audio Serial Port 8
mcasp8_axr0 McASP8 Transmit/Receive Data IO D15
mcasp8_axr1 McASP8 Transmit/Receive Data IO B16
mcasp8_axr2 McASP8 Transmit/Receive Data IO E15
mcasp8_axr3 McASP8 Transmit/Receive Data IO A20
mcasp8_ahclkx McASP8 Transmit High-Frequency Master Clock O C23
mcasp8_aclkx(1) McASP8 Transmit Bit Clock IO B17
mcasp8_fsx McASP8 Transmit Frame Sync IO A17
mcasp8_aclkr(1) McASP8 Receive Bit Clock IO B17
mcasp8_fsr McASP8 Receive Frame Sync IO A17
  1. This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

4.4.14 Universal Serial Bus (USB)

NOTE

For more information, see: Serial Communication Interface / SuperSpeed USB DRD Subsystem section of the device TRM.

Table 4-17 Universal Serial Bus Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Universal Serial Bus 1
usb1_dp USB1 USB2.0 differential signal pair (positive) IODS AD12
usb1_dm USB1 USB2.0 differential signal pair (negative) IODS AC12
usb1_drvvbus USB1 Drive VBUS signal O AB10
usb_rxn0(1) USB1 USB3.0 receiver negative lane IDS AF12
usb_rxp0(1) USB1 USB3.0 receiver positive lane IDS AE12
usb_txn0(1) USB1 USB3.0 transmitter negative lane ODS AC11
usb_txp0(1) USB1 USB3.0 transmitter positive lane ODS AD11
Universal Serial Bus 2
usb2_dp USB2 USB2.0 differential signal pair (positive) IODS AE11
usb2_dm USB2 USB2.0 differential signal pair (negative) IODS AF11
usb2_drvvbus USB2 Drive VBUS signal O AC10
  1. Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register involved.

4.4.15 SATA

NOTE

For more information, see the Serial Communication Interfaces / SATA section of the device TRM.

Table 4-18 SATA Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
sata1_rxn0 SATA differential negative receiver lane 0 IDS AH9
sata1_rxp0 SATA differential positive receiver lane 0 IDS AG9
sata1_txn0 SATA differential negative transmitter lane 0 ODS AG10
sata1_txp0 SATA differential positive transmitter lane 0 ODS AH10
sata1_led SATA channel activity indicator O A22 / G19

4.4.16 Peripheral Component Interconnect Express (PCIe)

NOTE

For more information, see the Serial Communication Interfaces / PCIe Controllers and the Shared PHY Component Subsystems / PCIe Shared PHY Subsystem sections of the device TRM.

Table 4-19 PCIe Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
pcie_rxn0 PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only. IOS AG13
pcie_rxp0 PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only. IOS AH13
pcie_txn0 PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only. ODS AG14
pcie_txp0 PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only. ODS AH14
pcie_rxn1 PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IOS AF12
pcie_rxp1 PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IOS AE12
pcie_txn1 PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AC11
pcie_txp1 PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AD11
ljcb_clkp PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (positive) IODS AG15
ljcb_clkn PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (negative) IODS AH15

4.4.17 Controller Area Network Interface (DCAN)

NOTE

For more information, see the Serial Communication Interface / DCAN section of the device TRM.

Table 4-20 DCAN Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
DCAN 1
dcan1_tx DCAN1 transmit data pin IO G20
dcan1_rx DCAN1 receive data pin IO G19 / AD17
DCAN 2
dcan2_tx DCAN2 transmit data pin IO E21/B21
dcan2_rx DCAN2 receive data pin IO F20/ B20/AC16

4.4.18 Ethernet Interface (GMAC_SW)

CAUTION

The I/O timing provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 7-69, Table 7-72, Table 7-77 and Table 7-84.

NOTE

For more information, see the Serial Communication Interfaces / Ethernet Controller section of the device TRM.

Table 4-21 GMAC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
rgmii0_txc RGMII0 Transmit Clock O W9
rgmii0_txctl RGMII0 Transmit Enable O V9
rgmii0_txd3 RGMII0 Transmit Data O V7
rgmii0_txd2 RGMII0 Transmit Data O U7
rgmii0_txd1 RGMII0 Transmit Data O V6
rgmii0_txd0 RGMII0 Transmit Data O U6
rgmii0_rxc RGMII0 Receive Clock I U5
rgmii0_rxctl RGMII0 Receive Control I V5
rgmii0_rxd3 RGMII0 Receive Data I V4
rgmii0_rxd2 RGMII0 Receive Data I V3
rgmii0_rxd1 RGMII0 Receive Data I Y2
rgmii0_rxd0 RGMII0 Receive Data I W2
rgmii1_txc RGMII1 Transmit Clock O D5
rgmii1_txctl RGMII1 Transmit Enable O C2
rgmii1_txd3 RGMII1 Transmit Data O C3
rgmii1_txd2 RGMII1 Transmit Data O C4
rgmii1_txd1 RGMII1 Transmit Data O B2
rgmii1_txd0 RGMII1 Transmit Data O D6
rgmii1_rxc RGMII1 Receive Clock I C5
rgmii1_rxctl RGMII1 Receive Control I A3
rgmii1_rxd3 RGMII1 Receive Data I B3
rgmii1_rxd2 RGMII1 Receive Data I B4
rgmii1_rxd1 RGMII1 Receive Data I B5
rgmii1_rxd0 RGMII1 Receive Data I A4
mii1_rxd1 MII1 Receive Data I C1
mii1_rxd2 MII1 Receive Data I E4
mii1_rxd3 MII1 Receive Data I F5
mii1_rxd0 MII1 Receive Data I E6
mii1_rxclk MII1 Receive Clock I D5
mii1_rxdv MII1 Receive Data Valid I C2
mii1_txclk MII1 Transmit Clock I C3
mii1_txd0 MII1 Transmit Data O C4
mii1_txd1 MII1 Transmit Data O B2
mii1_txd2 MII1 Transmit Data O D6
mii1_txd3 MII1 Transmit Data O C5
mii1_txer MII1 Transmit Error I A3
mii1_rxer MII1 Receive Data Error I B3
mii1_col MII1 Collision Detect (Sense) I B4
mii1_crs MII1 Carrier Sense I B5
mii1_txen MII1 Transmit Data Enable O A4
mii0_rxd1 MII0 Receive Data I V6
mii0_rxd2 MII0 Receive Data I V9
mii0_rxd3 MII0 Receive Data I W9
mii0_rxd0 MII0 Receive Data I U6
mii0_rxclk MII0 Receive Clock I Y1
mii0_rxdv MII0 Receive Data Valid I V2
mii0_txclk MII0 Transmit Clock I U5
mii0_txd0 MII0 Transmit Data O W2
mii0_txd1 MII0 Transmit Data O Y2
mii0_txd2 MII0 Transmit Data O V4
mii0_txd3 MII0 Transmit Data O V5
mii0_txer MII0 Transmit Error I U4
mii0_rxer MII0 Receive Data Error I U7
mii0_col MII0 Collision Detect (Sense) I V1
mii0_crs MII0 Carrier Sense I V7
mii0_txen MII0 Transmit Data Enable O V3
rmii1_crs RMII1 Carrier Sense I V2
rmii1_rxer RMII1 Receive Data Error I Y1
rmii1_rxd1 RMII1 Receive Data I W9
rmii1_rxd0 RMII1 Receive Data I V9
rmii1_txen RMII1 Transmit Data Enable O U5
rmii1_txd1 RMII1 Transmit Data O V5
rmii1_txd0 RMII1 Transmit Data O V4
rmii0_crs RMII0 Carrier Sense I V7
rmii0_rxer RMII0 Receive Data Error I U7
rmii0_rxd1 RMII0 Receive Data I V6
rmii0_rxd0 RMII0 Receive Data I U6
rmii0_txen RMII0 Transmit Data Enable O V3
rmii0_txd1 RMII0 Transmit Data O Y2
rmii0_txd0 RMII0 Transmit Data O W2
mdio_mclk Management Data Serial Clock O AC5 / V1 / B21 / D3
mdio_d Management Data IO AB4 / U4 / B20 / F6

4.4.19 Media Local Bus (MLB) Interface

NOTE

Media Local Bus (MLB) is not available on this device, and must be left unconnected.

Table 4-22 MLB Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
mlbp_sig_p Media Local Bus (MLB) Subsystem signal differential pair (positive) IODS AC1
mlbp_sig_n Media Local Bus (MLB) Subsystem signal differential pair (negative) IODS AC2
mlbp_dat_p Media Local Bus (MLB) Subsystem data differential pair (positive) IODS AA1
mlbp_dat_n Media Local Bus (MLB) Subsystem data differential pair (negative) IODS AA2
mlbp_clk_p Media Local Bus (MLB) Subsystem clock differential pair (positive) IOS AB1
mlbp_clk_n Media Local Bus (MLB) Subsystem clock differential pair (negative) IOS AB2

4.4.20 eMMC/SD/SDIO

NOTE

For more information, see the HS MMC/SDIO section of the device TRM.

Table 4-23 eMMC/SD/SDIO Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Multi Media Card 1
mmc1_clk(1) MMC1 clock IO W6
mmc1_cmd MMC1 command IO Y6
mmc1_sdcd MMC1 Card Detect I W7
mmc1_sdwp MMC1 Write Protect I Y9
mmc1_dat0 MMC1 data bit 0 IO AA6
mmc1_dat1 MMC1 data bit 1 IO Y4
mmc1_dat2 MMC1 data bit 2 IO AA5
mmc1_dat3 MMC1 data bit 3 IO Y3
Multi Media Card 2
mmc2_clk(1) MMC2 clock IO J7
mmc2_cmd MMC2 command IO H6
mmc2_sdcd MMC2 Card Detect I G20
mmc2_sdwp MMC2 Write Protect I G19
mmc2_dat0 MMC2 data bit 0 IO J4
mmc2_dat1 MMC2 data bit 1 IO J6
mmc2_dat2 MMC2 data bit 2 IO H4
mmc2_dat3 MMC2 data bit 3 IO H5
mmc2_dat4 MMC2 data bit 4 IO K7
mmc2_dat5 MMC2 data bit 5 IO M7
mmc2_dat6 MMC2 data bit 6 IO J5
mmc2_dat7 MMC2 data bit 7 IO K6
Multi Media Card 3
mmc3_clk(1) MMC3 clock IO AD4
mmc3_cmd MMC3 command IO AC4
mmc3_sdcd MMC3 Card Detect I B21
mmc3_sdwp MMC3 Write Protect I B20
mmc3_dat0 MMC3 data bit 0 IO AC7
mmc3_dat1 MMC3 data bit 1 IO AC6
mmc3_dat2 MMC3 data bit 2 IO AC9
mmc3_dat3 MMC3 data bit 3 IO AC3
mmc3_dat4 MMC3 data bit 4 IO AC8
mmc3_dat5 MMC3 data bit 5 IO AD6
mmc3_dat6 MMC3 data bit 6 IO AB8
mmc3_dat7 MMC3 data bit 7 IO AB5
Multi Media Card 4
mmc4_clk(1) MMC4 clock IO E25
mmc4_cmd MMC4 command IO C27
mmc4_sdcd MMC4 Card Detect I B27
mmc4_sdwp MMC4 Write Protect I C26
mmc4_dat0 MMC4 data bit 0 IO D28
mmc4_dat1 MMC4 data bit 1 IO D26
mmc4_dat2 MMC4 data bit 2 IO D27
mmc4_dat3 MMC4 data bit 3 IO C28
  1. By default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal loopback clock' instead of the default 'pad loopback clock'. If the 'pad loopback clock' is used, series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

4.4.21 General-Purpose Interface (GPIO)

NOTE

For more information, see the General-Purpose Interface section of the device TRM.

Table 4-24 GPIOs Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
GPIO 1
gpio1_0 General-Purpose Input I AD17
gpio1_3 General-Purpose Input I AC16
gpio1_4 General-Purpose Input/Output IO D15
gpio1_5 General-Purpose Input/Output IO A17
gpio1_6 General-Purpose Input/Output IO M6
gpio1_7 General-Purpose Input/Output IO M2
gpio1_8 General-Purpose Input/Output IO L5
gpio1_9 General-Purpose Input/Output IO M1
gpio1_10 General-Purpose Input/Output IO L6
gpio1_11 General-Purpose Input/Output IO L4
gpio1_12 General-Purpose Input/Output IO L3
gpio1_13 General-Purpose Input/Output IO L2
gpio1_14 General-Purpose Input/Output IO G20
gpio1_15 General-Purpose Input/Output IO G19
gpio1_16 General-Purpose Input/Output IO D27
gpio1_17 General-Purpose Input/Output IO C28
gpio1_18 General-Purpose Input/Output IO H1
gpio1_19 General-Purpose Input/Output IO J3
gpio1_20 General-Purpose Input/Output IO H2
gpio1_21 General-Purpose Input/Output IO H3
gpio1_22 General-Purpose Input/Output IO AC8
gpio1_23 General-Purpose Input/Output IO AD6
gpio1_24 General-Purpose Input/Output IO AB8
gpio1_25 General-Purpose Input/Output IO AB5
gpio1_26 General-Purpose Input/Output IO P6
gpio1_27 General-Purpose Input/Output IO R9
gpio1_28 General-Purpose Input/Output IO R5
gpio1_29 General-Purpose Input/Output IO P5
gpio1_30 General-Purpose Input/Output IO N7
gpio1_31 General-Purpose Input/Output IO R4
GPIO 2
gpio2_0 General-Purpose Input/Output IO N9
gpio2_1 General-Purpose Input/Output IO P9
gpio2_2 General-Purpose Input/Output IO P4
gpio2_3 General-Purpose Input/Output IO R3
gpio2_4 General-Purpose Input/Output IO T2
gpio2_5 General-Purpose Input/Output IO U2
gpio2_6 General-Purpose Input/Output IO U1
gpio2_7 General-Purpose Input/Output IO P3
gpio2_8 General-Purpose Input/Output IO R2
gpio2_9 General-Purpose Input/Output IO K7
gpio2_10 General-Purpose Input/Output IO M7
gpio2_11 General-Purpose Input/Output IO J5
gpio2_12 General-Purpose Input/Output IO K6
gpio2_13 General-Purpose Input/Output IO J7
gpio2_14 General-Purpose Input/Output IO J4
gpio2_15 General-Purpose Input/Output IO J6
gpio2_16 General-Purpose Input/Output IO H4
gpio2_17 General-Purpose Input/Output IO H5
gpio2_18 General-Purpose Input/Output IO H6
gpio2_19 General-Purpose Input/Output IO T1
gpio2_20 General-Purpose Input/Output IO P2
gpio2_21 General-Purpose Input/Output IO P1
gpio2_22 General-Purpose Input/Output IO P7
gpio2_23 General-Purpose Input/Output IO N1
gpio2_24 General-Purpose Input/Output IO M5
gpio2_25 General-Purpose Input/Output IO M3
gpio2_26 General-Purpose Input/Output IO N6
gpio2_27 General-Purpose Input/Output IO M4
gpio2_28 General-Purpose Input/Output IO N2
gpio2_29 General-Purpose Input/Output IO B17
GPIO 3
gpio3_28 General-Purpose Input/Output IO E1
gpio3_29 General-Purpose Input/Output IO G2
gpio3_30 General-Purpose Input/Output IO H7
gpio3_31 General-Purpose Input/Output IO G1
GPIO 4
gpio4_0 General-Purpose Input/Output IO G6
gpio4_1 General-Purpose Input/Output IO F2
gpio4_2 General-Purpose Input/Output IO F3
gpio4_3 General-Purpose Input/Output IO D1
gpio4_4 General-Purpose Input/Output IO E2
gpio4_5 General-Purpose Input/Output IO D2
gpio4_6 General-Purpose Input/Output IO F4
gpio4_7 General-Purpose Input/Output IO C1
gpio4_8 General-Purpose Input/Output IO E4
gpio4_9 General-Purpose Input/Output IO F5
gpio4_10 General-Purpose Input/Output IO E6
gpio4_11 General-Purpose Input/Output IO D3
gpio4_12 General-Purpose Input/Output IO F6
gpio4_13 General-Purpose Input/Output IO D5
gpio4_14 General-Purpose Input/Output IO C2
gpio4_15 General-Purpose Input/Output IO C3
gpio4_16 General-Purpose Input/Output IO C4
gpio4_17 General-Purpose Input/Output IO A12
gpio4_18 General-Purpose Input/Output IO E14
gpio4_19 General-Purpose Input/Output IO D11
gpio4_20 General-Purpose Input/Output IO B10
gpio4_21 General-Purpose Input/Output IO B11
gpio4_22 General-Purpose Input/Output IO C11
gpio4_23 General-Purpose Input/Output IO E11
gpio4_24 General-Purpose Input/Output IO B2
gpio4_25 General-Purpose Input/Output IO D6
gpio4_26 General-Purpose Input/Output IO C5
gpio4_27 General-Purpose Input/Output IO A3
gpio4_28 General-Purpose Input/Output IO B3
gpio4_29 General-Purpose Input/Output IO B4
gpio4_30 General-Purpose Input/Output IO B5
gpio4_31 General-Purpose Input/Output IO A4
GPIO 5
gpio5_0 General-Purpose Input/Output IO B14
gpio5_1 General-Purpose Input/Output IO J14
gpio5_2 General-Purpose Input/Output IO G12
gpio5_3 General-Purpose Input/Output IO F12
gpio5_4 General-Purpose Input/Output IO G13
gpio5_5 General-Purpose Input/Output IO J11
gpio5_6 General-Purpose Input/Output IO E12
gpio5_7 General-Purpose Input/Output IO F13
gpio5_8 General-Purpose Input/Output IO C12
gpio5_9 General-Purpose Input/Output IO D12
gpio5_10 General-Purpose Input/Output IO B12
gpio5_11 General-Purpose Input/Output IO A11
gpio5_12 General-Purpose Input/Output IO B13
gpio5_13 General-Purpose Input/Output IO B18
gpio5_14 General-Purpose Input/Output IO F15
gpio5_15 General-Purpose Input/Output IO V1
gpio5_16 General-Purpose Input/Output IO U4
gpio5_17 General-Purpose Input/Output IO U3
gpio5_18 General-Purpose Input/Output IO V2
gpio5_19 General-Purpose Input/Output IO Y1
gpio5_20 General-Purpose Input/Output IO W9
gpio5_21 General-Purpose Input/Output IO V9
gpio5_22 General-Purpose Input/Output IO V7
gpio5_23 General-Purpose Input/Output IO U7
gpio5_24 General-Purpose Input/Output IO V6
gpio5_25 General-Purpose Input/Output IO U6
gpio5_26 General-Purpose Input/Output IO U5
gpio5_27 General-Purpose Input/Output IO V5
gpio5_28 General-Purpose Input/Output IO V4
gpio5_29 General-Purpose Input/Output IO V3
gpio5_30 General-Purpose Input/Output IO Y2
gpio5_31 General-Purpose Input/Output IO W2
GPIO 6
gpio6_4 General-Purpose Input/Output IO A13
gpio6_5 General-Purpose Input/Output IO G14
gpio6_6 General-Purpose Input/Output IO F14
gpio6_7 General-Purpose Input/Output IO B16
gpio6_8 General-Purpose Input/Output IO C15
gpio6_9 General-Purpose Input/Output IO A16
gpio6_10 General-Purpose Input/Output IO AC5
gpio6_11 General-Purpose Input/Output IO AB4
gpio6_12 General-Purpose Input/Output IO AB10
gpio6_13 General-Purpose Input/Output IO AC10
gpio6_14 General-Purpose Input/Output IO E21
gpio6_15 General-Purpose Input/Output IO F20
gpio6_16 General-Purpose Input/Output IO F21
gpio6_17 General-Purpose Input/Output IO D18
gpio6_18 General-Purpose Input/Output IO E17
gpio6_19 General-Purpose Input/Output IO B26
gpio6_20 General-Purpose Input/Output IO C23
gpio6_21 General-Purpose Input/Output IO W6
gpio6_22 General-Purpose Input/Output IO Y6
gpio6_23 General-Purpose Input/Output IO AA6
gpio6_24 General-Purpose Input/Output IO Y4
gpio6_25 General-Purpose Input/Output IO AA5
gpio6_26 General-Purpose Input/Output IO Y3
gpio6_27 General-Purpose Input/Output IO W7
gpio6_28 General-Purpose Input/Output IO Y9
gpio6_29 General-Purpose Input/Output IO AD4
gpio6_30 General-Purpose Input/Output IO AC4
gpio6_31 General-Purpose Input/Output IO AC7
GPIO 7
gpio7_0 General-Purpose Input/Output IO AC6
gpio7_1 General-Purpose Input/Output IO AC9
gpio7_2 General-Purpose Input/Output IO AC3
gpio7_3 General-Purpose Input/Output IO R6
gpio7_4 General-Purpose Input/Output IO T9
gpio7_5 General-Purpose Input/Output IO T6
gpio7_6 General-Purpose Input/Output IO T7
gpio7_7 General-Purpose Input/Output IO A25
gpio7_8 General-Purpose Input/Output IO F16
gpio7_9 General-Purpose Input/Output IO B25
gpio7_10 General-Purpose Input/Output IO A24
gpio7_11 General-Purpose Input/Output IO A22
gpio7_12 General-Purpose Input/Output IO B21
gpio7_13 General-Purpose Input/Output IO B20
gpio7_14 General-Purpose Input/Output IO A26
gpio7_15 General-Purpose Input/Output IO B22
gpio7_16 General-Purpose Input/Output IO G17
gpio7_17 General-Purpose Input/Output IO B24
gpio7_18 General-Purpose Input/Output IO L1
gpio7_19 General-Purpose Input/Output IO K2
gpio7_22 General-Purpose Input/Output IO B27
gpio7_23 General-Purpose Input/Output IO C26
gpio7_24 General-Purpose Input/Output IO E25
gpio7_25 General-Purpose Input/Output IO C27
gpio7_26 General-Purpose Input/Output IO D28
gpio7_27 General-Purpose Input/Output IO D26
gpio7_28 General-Purpose Input/Output IO J1
gpio7_29 General-Purpose Input/Output IO J2
gpio7_30 General-Purpose Input/Output IO D14
gpio7_31 General-Purpose Input/Output IO C14
GPIO 8
gpio8_0 General-Purpose Input/Output IO F11
gpio8_1 General-Purpose Input/Output IO G10
gpio8_2 General-Purpose Input/Output IO F10
gpio8_3 General-Purpose Input/Output IO G11
gpio8_4 General-Purpose Input/Output IO E9
gpio8_5 General-Purpose Input/Output IO F9
gpio8_6 General-Purpose Input/Output IO F8
gpio8_7 General-Purpose Input/Output IO E7
gpio8_8 General-Purpose Input/Output IO E8
gpio8_9 General-Purpose Input/Output IO D9
gpio8_10 General-Purpose Input/Output IO D7
gpio8_11 General-Purpose Input/Output IO D8
gpio8_12 General-Purpose Input/Output IO A5
gpio8_13 General-Purpose Input/Output IO C6
gpio8_14 General-Purpose Input/Output IO C8
gpio8_15 General-Purpose Input/Output IO C7
gpio8_16 General-Purpose Input/Output IO B7
gpio8_17 General-Purpose Input/Output IO B8
gpio8_18 General-Purpose Input/Output IO A7
gpio8_19 General-Purpose Input/Output IO A8
gpio8_20 General-Purpose Input/Output IO C9
gpio8_21 General-Purpose Input/Output IO A9
gpio8_22 General-Purpose Input/Output IO B9
gpio8_23 General-Purpose Input/Output IO A10
gpio8_27 General-Purpose Input I D23
gpio8_28 General-Purpose Input/Output IO F19
gpio8_29 General-Purpose Input/Output IO E18
gpio8_30 General-Purpose Input/Output IO G21
gpio8_31 General-Purpose Input/Output IO D24

4.4.22 Keyboard controller (KBD)

NOTE

For more information, see Keyboard Controller section of the device TRM.

Table 4-25 Keyboard Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
kbd_row0 Keypad row 0 I E1
kbd_row1 Keypad row 1 I G2
kbd_row2 Keypad row 2 I G1
kbd_row3 Keypad row 3 I G6
kbd_row4 Keypad row 4 I F2
kbd_row5 Keypad row 5 I F3
kbd_row6 Keypad row 6 I D1
kbd_row7 Keypad row 7 I F6
kbd_row8 Keypad row 8 I C2
kbd_col0 Keypad column 0 O E2
kbd_col1 Keypad column 1 O D2
kbd_col2 Keypad column 2 O F4
kbd_col3 Keypad column 3 O C1
kbd_col4 Keypad column 4 O E4
kbd_col5 Keypad column 5 O F5
kbd_col6 Keypad column 6 O E6
kbd_col7 Keypad column 7 O D3
kbd_col8 Keypad column 8 O D5

4.4.23 Pulse Width Modulation (PWM) Interface

NOTE

For more information, see the Pulse-Width Modulation (PWM) SS section of the device TRM.

Table 4-26 PWM Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
PWMSS1
eQEP1A_in EQEP1 Quadrature Input A I E1
eQEP1B_in EQEP1 Quadrature Input B I G2
eQEP1_index EQEP1 Index Input IO H7
eQEP1_strobe EQEP1 Strobe Input IO G1
ehrpwm1A EHRPWM1 Output A O G6
ehrpwm1B EHRPWM1 Output B O F2
ehrpwm1_tripzone_input EHRPWM1 Trip Zone Input IO F3
eCAP1_in_PWM1_out ECAP1 Capture Iniput / PWM Output IO D1
ehrpwm1_synci EHRPWM1 Sync Input I E2
ehrpwm1_synco EHRPWM1 Sync Output O D2
PWMSS2
eQEP2A_in EQEP2 Quadrature Input A I F4
eQEP2B_in EQEP2 Quadrature Input B I C1
eQEP2_index EQEP2 Index Input IO E4
eQEP2_strobe EQEP2 Strobe Input IO F5
ehrpwm2A EHRPWM2 Output A O AC5 / E6
ehrpwm2B EHRPWM2 Output B O AB4 / D3
ehrpwm2_tripzone_input EHRPWM2 Trip Zone Input IO AD4 / F6
eCAP2_in_PWM2_out ECAP2 Capture Iniput / PWM Output IO AC4 / D5
PWMSS3
eQEP3A_in EQEP3 Quadrature Input A I AC7 / C2
eQEP3B_in EQEP3 Quadrature Input B I AC6 / C3
eQEP3_index EQEP3 Index Input IO AC9 / C4
eQEP3_strobe EQEP3 Strobe Input IO AC3 / B2
ehrpwm3A EHRPWM3 Output A O AC8 / D6
ehrpwm3B EHRPWM3 Output B O AD6 / C5
ehrpwm3_tripzone_input EHRPWM3 Trip Zone Input IO AB8 / A3
eCAP3_in_PWM3_out ECAP3 Capture Iniput / PWM Output IO AB5 / B3

4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

CAUTION

The I/O timing provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 7-152 and Table 7-153.

NOTE

For more information see the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem section of the device TRM.

Table 4-27 PRU-ICSS Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL BOTTOM
PRU-ICSS 1
pr1_pru1_gpi0 PRU1 General-Purpose Input I E2
pr1_pru1_gpi1 PRU1 General-Purpose Input I D2
pr1_pru1_gpi10 PRU1 General-Purpose Input I C2
pr1_pru1_gpi11 PRU1 General-Purpose Input I C3
pr1_pru1_gpi12 PRU1 General-Purpose Input I C4
pr1_pru1_gpi13 PRU1 General-Purpose Input I B2
pr1_pru1_gpi14 PRU1 General-Purpose Input I D6
pr1_pru1_gpi15 PRU1 General-Purpose Input I C5
pr1_pru1_gpi16 PRU1 General-Purpose Input I A3
pr1_pru1_gpi17 PRU1 General-Purpose Input I B3
pr1_pru1_gpi18 PRU1 General-Purpose Input I B4
pr1_pru1_gpi19 PRU1 General-Purpose Input I B5
pr1_pru1_gpi2 PRU1 General-Purpose Input I F4
pr1_pru1_gpi20 PRU1 General-Purpose Input I A4
pr1_pru1_gpi3 PRU1 General-Purpose Input I C1
pr1_pru1_gpi4 PRU1 General-Purpose Input I E4
pr1_pru1_gpi5 PRU1 General-Purpose Input I F5
pr1_pru1_gpi6 PRU1 General-Purpose Input I E6
pr1_pru1_gpi7 PRU1 General-Purpose Input I D3
pr1_pru1_gpi8 PRU1 General-Purpose Input I F6
pr1_pru1_gpi9 PRU1 General-Purpose Input I D5
pr1_pru1_gpo0 PRU1 General-Purpose Output O E2
pr1_pru1_gpo1 PRU1 General-Purpose Output O D2
pr1_pru1_gpo10 PRU1 General-Purpose Output O C2
pr1_pru1_gpo11 PRU1 General-Purpose Output O C3
pr1_pru1_gpo12 PRU1 General-Purpose Output O C4
pr1_pru1_gpo13 PRU1 General-Purpose Output O B2
pr1_pru1_gpo14 PRU1 General-Purpose Output O D6
pr1_pru1_gpo15 PRU1 General-Purpose Output O C5
pr1_pru1_gpo16 PRU1 General-Purpose Output O A3
pr1_pru1_gpo17 PRU1 General-Purpose Output O B3
pr1_pru1_gpo18 PRU1 General-Purpose Output O B4
pr1_pru1_gpo19 PRU1 General-Purpose Output O B5
pr1_pru1_gpo2 PRU1 General-Purpose Output O F4
pr1_pru1_gpo20 PRU1 General-Purpose Output O A4
pr1_pru1_gpo3 PRU1 General-Purpose Output O C1
pr1_pru1_gpo4 PRU1 General-Purpose Output O E4
pr1_pru1_gpo5 PRU1 General-Purpose Output O F5
pr1_pru1_gpo6 PRU1 General-Purpose Output O E6
pr1_pru1_gpo7 PRU1 General-Purpose Output O D3
pr1_pru1_gpo8 PRU1 General-Purpose Output O F6
pr1_pru1_gpo9 PRU1 General-Purpose Output O D5
pr1_edc_latch0_in Latch Input 0 I E2
pr1_edc_sync0_out SYNC 0 Output O D2
pr1_edio_data_in0 Ethernet Digital Input I E1
pr1_edio_data_in1 Ethernet Digital Input I G2
pr1_edio_data_in2 Ethernet Digital Input I H7
pr1_edio_data_in3 Ethernet Digital Input I G1
pr1_edio_data_in4 Ethernet Digital Input I G6
pr1_edio_data_in5 Ethernet Digital Input I F2
pr1_edio_data_in6 Ethernet Digital Input I F3
pr1_edio_data_in7 Ethernet Digital Input I D1
pr1_edio_data_out0 Ethernet Digital Output O E1
pr1_edio_data_out1 Ethernet Digital Output O G2
pr1_edio_data_out2 Ethernet Digital Output O H7
pr1_edio_data_out3 Ethernet Digital Output O G1
pr1_edio_data_out4 Ethernet Digital Output O G6
pr1_edio_data_out5 Ethernet Digital Output O F2
pr1_edio_data_out6 Ethernet Digital Output O F3
pr1_edio_data_out7 Ethernet Digital Output O D1
pr1_edio_sof Start Of Frame O F4
pr1_mdio_data MDIO Data IO F6
pr1_mdio_mdclk MDIO Clock O D3
pr1_mii0_col MII0 Collision Detect I V1
pr1_mii0_crs MII0 Carrier Sense I V7
pr1_mii0_rxd0 MII0 Receive Data I U6
pr1_mii0_rxd1 MII0 Receive Data I V6
pr1_mii0_rxd2 MII0 Receive Data I V9
pr1_mii0_rxd3 MII0 Receive Data I W9
pr1_mii0_rxdv MII0 Data Valid I V2
pr1_mii0_rxer MII0 Receive Error I U7
pr1_mii0_rxlink MII0 Receive Link I U4
pr1_mii0_txd0 MII0 Transmit Data O W2
pr1_mii0_txd1 MII0 Transmit Data O Y2
pr1_mii0_txd2 MII0 Transmit Data O V4
pr1_mii0_txd3 MII0 Transmit Data O V5
pr1_mii0_txen MII0 Transmit Enable O V3
pr1_mii_mr0_clk MII0 Receive Clock I Y1
pr1_mii_mt0_clk MII0 Transmit Clock I U5
pr1_mii1_col MII1 Collision Detect I B5
pr1_mii1_crs MII1 Carrier Sense I A4
pr1_mii1_rxd0 MII1 Receive Data I A3
pr1_mii1_rxd1 MII1 Receive Data I C5
pr1_mii1_rxd2 MII1 Receive Data I D6
pr1_mii1_rxd3 MII1 Receive Data I B2
pr1_mii1_rxdv MII1 Data Valid I C4
pr1_mii1_rxer MII1 Receive Error I B3
pr1_mii1_rxlink MII1 Receive Link I B4
pr1_mii1_txd0 MII1 Transmit Data O C2
pr1_mii1_txd1 MII1 Transmit Data O D5
pr1_mii1_txd2 MII1 Transmit Data O E6
pr1_mii1_txd3 MII1 Transmit Data O F5
pr1_mii1_txen MII1 Transmit Enable O E4
pr1_mii_mr1_clk MII1 Receive Clock I C3
pr1_mii_mt1_clk MII1 Transmit Clock I C1
pr1_uart0_cts_n UART Clear-To-Send I F11,G1
pr1_uart0_rts_n UART Ready-To-Send O G10,G6
pr1_uart0_rxd UART Receive Data I F10,F2
pr1_uart0_txd UART Transmit Data O F3,G11
pr1_ecap0_ecap_capin_apwm_o Capture Input / PWM output IO D1,E9
PRU-ICSS 2
pr2_pru0_gpi0 PRU0 General-Purpose Input I AC5,G11
pr2_pru0_gpi1 PRU0 General-Purpose Input I AB4,E9
pr2_pru0_gpi10 PRU0 General-Purpose Input I AB8,C6
pr2_pru0_gpi11 PRU0 General-Purpose Input I AB5,C8
pr2_pru0_gpi12 PRU0 General-Purpose Input I B18,C7
pr2_pru0_gpi13 PRU0 General-Purpose Input I B7,F15
pr2_pru0_gpi14 PRU0 General-Purpose Input I B19,B8
pr2_pru0_gpi15 PRU0 General-Purpose Input I A7,C17
pr2_pru0_gpi16 PRU0 General-Purpose Input I A8,C15
pr2_pru0_gpi17 PRU0 General-Purpose Input I A16,C9
pr2_pru0_gpi18 PRU0 General-Purpose Input I A19,A9
pr2_pru0_gpi19 PRU0 General-Purpose Input I A18,B9
pr2_pru0_gpi2 PRU0 General-Purpose Input I AD4,F9
pr2_pru0_gpi20 PRU0 General-Purpose Input I A10,F14
pr2_pru0_gpi3 PRU0 General-Purpose Input I AC4,F8
pr2_pru0_gpi4 PRU0 General-Purpose Input I AC7,E7
pr2_pru0_gpi5 PRU0 General-Purpose Input I AC6,E8
pr2_pru0_gpi6 PRU0 General-Purpose Input I AC9,D9
pr2_pru0_gpi7 PRU0 General-Purpose Input I AC3,D7
pr2_pru0_gpi8 PRU0 General-Purpose Input I AC8,D8
pr2_pru0_gpi9 PRU0 General-Purpose Input I A5,AD6
pr2_pru1_gpi0 PRU1 General-Purpose Input I D17,V1
pr2_pru1_gpi1 PRU1 General-Purpose Input I AA3,U4
pr2_pru1_gpi10 PRU1 General-Purpose Input I B12,U6
pr2_pru1_gpi11 PRU1 General-Purpose Input I A11,U5
pr2_pru1_gpi12 PRU1 General-Purpose Input I B13,V5
pr2_pru1_gpi13 PRU1 General-Purpose Input I A12,V4
pr2_pru1_gpi14 PRU1 General-Purpose Input I E14,V3
pr2_pru1_gpi15 PRU1 General-Purpose Input I A13,Y2
pr2_pru1_gpi16 PRU1 General-Purpose Input I G14,W2
pr2_pru1_gpi17 PRU1 General-Purpose Input I E11
pr2_pru1_gpi18 PRU1 General-Purpose Input I F11
pr2_pru1_gpi19 PRU1 General-Purpose Input I G10
pr2_pru1_gpi2 PRU1 General-Purpose Input I AB9,U3
pr2_pru1_gpi20 PRU1 General-Purpose Input I F10
pr2_pru1_gpi3 PRU1 General-Purpose Input I AB3,V2
pr2_pru1_gpi4 PRU1 General-Purpose Input I AA4,Y1
pr2_pru1_gpi5 PRU1 General-Purpose Input I D18,W9
pr2_pru1_gpi6 PRU1 General-Purpose Input I E17,V9
pr2_pru1_gpi7 PRU1 General-Purpose Input I C14,V7
pr2_pru1_gpi8 PRU1 General-Purpose Input I G12,U7
pr2_pru1_gpi9 PRU1 General-Purpose Input I F12,V6
pr2_pru0_gpo0 PRU0 General-Purpose Output O AC5,G11
pr2_pru0_gpo1 PRU0 General-Purpose Output O AB4,E9
pr2_pru0_gpo10 PRU0 General-Purpose Output O AB8,C6
pr2_pru0_gpo11 PRU0 General-Purpose Output O AB5,C8
pr2_pru0_gpo12 PRU0 General-Purpose Output O B18,C7
pr2_pru0_gpo13 PRU0 General-Purpose Output O B7,F15
pr2_pru0_gpo14 PRU0 General-Purpose Output O B19,B8
pr2_pru0_gpo15 PRU0 General-Purpose Output O A7,C17
pr2_pru0_gpo16 PRU0 General-Purpose Output O A8,C15
pr2_pru0_gpo17 PRU0 General-Purpose Output O A16,C9
pr2_pru0_gpo18 PRU0 General-Purpose Output O A19,A9
pr2_pru0_gpo19 PRU0 General-Purpose Output O A18,B9
pr2_pru0_gpo2 PRU0 General-Purpose Output O AD4,F9
pr2_pru0_gpo20 PRU0 General-Purpose Output O A10,F14
pr2_pru0_gpo3 PRU0 General-Purpose Output O AC4,F8
pr2_pru0_gpo4 PRU0 General-Purpose Output O AC7,E7
pr2_pru0_gpo5 PRU0 General-Purpose Output O AC6,E8
pr2_pru0_gpo6 PRU0 General-Purpose Output O AC9,D9
pr2_pru0_gpo7 PRU0 General-Purpose Output O AC3,D7
pr2_pru0_gpo8 PRU0 General-Purpose Output O AC8,D8
pr2_pru0_gpo9 PRU0 General-Purpose Output O A5,AD6
pr2_pru1_gpo0 PRU1 General-Purpose Output O D17,V1
pr2_pru1_gpo1 PRU1 General-Purpose Output O AA3,U4
pr2_pru1_gpo10 PRU1 General-Purpose Output O B12,U6
pr2_pru1_gpo11 PRU1 General-Purpose Output O A11,U5
pr2_pru1_gpo12 PRU1 General-Purpose Output O B13,V5
pr2_pru1_gpo13 PRU1 General-Purpose Output O A12,V4
pr2_pru1_gpo14 PRU1 General-Purpose Output O E14,V3
pr2_pru1_gpo15 PRU1 General-Purpose Output O A13,Y2
pr2_pru1_gpo16 PRU1 General-Purpose Output O G14,W2
pr2_pru1_gpo17 PRU1 General-Purpose Output O E11
pr2_pru1_gpo18 PRU1 General-Purpose Output O F11
pr2_pru1_gpo19 PRU1 General-Purpose Output O G10
pr2_pru1_gpo2 PRU1 General-Purpose Output O AB9,U3
pr2_pru1_gpo20 PRU1 General-Purpose Output O F10
pr2_pru1_gpo3 PRU1 General-Purpose Output O AB3,V2
pr2_pru1_gpo4 PRU1 General-Purpose Output O AA4,Y1
pr2_pru1_gpo5 PRU1 General-Purpose Output O D18,W9
pr2_pru1_gpo6 PRU1 General-Purpose Output O E17,V9
pr2_pru1_gpo7 PRU1 General-Purpose Output O C14,V7
pr2_pru1_gpo8 PRU1 General-Purpose Output O G12,U7
pr2_pru1_gpo9 PRU1 General-Purpose Output O F12,V6
pr2_edc_latch0_in Latch Input 0 I F9
pr2_edc_latch1_in Latch Input 1 I F8
pr2_edc_sync0_out SYNC 0 Output O E7
pr2_edc_sync1_out SYNC 1 Output O E8
pr2_edio_data_in0 Ethernet Digital Input I B7
pr2_edio_data_in1 Ethernet Digital Input I B8
pr2_edio_data_in2 Ethernet Digital Input I A7
pr2_edio_data_in3 Ethernet Digital Input I A8
pr2_edio_data_in4 Ethernet Digital Input I C9
pr2_edio_data_in5 Ethernet Digital Input I A9
pr2_edio_data_in6 Ethernet Digital Input I B9
pr2_edio_data_in7 Ethernet Digital Input I A10
pr2_edio_data_out0 Ethernet Digital Output O B7
pr2_edio_data_out1 Ethernet Digital Output O B8
pr2_edio_data_out2 Ethernet Digital Output O A7
pr2_edio_data_out3 Ethernet Digital Output O A8
pr2_edio_data_out4 Ethernet Digital Output O C9
pr2_edio_data_out5 Ethernet Digital Output O A9
pr2_edio_data_out6 Ethernet Digital Output O B9
pr2_edio_data_out7 Ethernet Digital Output O A10
pr2_edio_latch_in Latch Input I D9
pr2_edio_sof Start Of Frame O D7
pr2_mdio_data MDIO Data IO AA4,D14
pr2_mdio_mdclk MDIO Clock O AB3,C14
pr2_mii0_col MII0 Collision Detect I F15
pr2_mii0_crs MII0 Carrier Sense I B18
pr2_mii0_rxd0 MII0 Receive Data I C15
pr2_mii0_rxd1 MII0 Receive Data I A18
pr2_mii0_rxd2 MII0 Receive Data I A19
pr2_mii0_rxd3 MII0 Receive Data I F14
pr2_mii0_rxdv MII0 Data Valid I G14
pr2_mii0_rxer MII0 Receive Error I G12
pr2_mii0_rxlink MII0 Receive Link I A16
pr2_mii0_txd0 MII0 Transmit Data O E14
pr2_mii0_txd1 MII0 Transmit Data O A12
pr2_mii0_txd2 MII0 Transmit Data O B13
pr2_mii0_txd3 MII0 Transmit Data O A11
pr2_mii0_txen MII0 Transmit Enable O B12
pr2_mii_mr0_clk MII0 Receive Clock I A13
pr2_mii_mt0_clk MII0 Transmit Clock I F12
pr2_mii1_col MII1 Collision Detect I D18
pr2_mii1_crs MII1 Carrier Sense I E17
pr2_mii1_rxd0 MII1 Receive Data I AB5
pr2_mii1_rxd1 MII1 Receive Data I AB8
pr2_mii1_rxd2 MII1 Receive Data I AD6
pr2_mii1_rxd3 MII1 Receive Data I AC8
pr2_mii1_rxdv MII1 Data Valid I AC3
pr2_mii1_rxer MII1 Receive Error I B19
pr2_mii1_rxlink MII1 Receive Link I C17
pr2_mii1_txd0 MII1 Transmit Data O AC6
pr2_mii1_txd1 MII1 Transmit Data O AC7
pr2_mii1_txd2 MII1 Transmit Data O AC4
pr2_mii1_txd3 MII1 Transmit Data O AD4
pr2_mii1_txen MII1 Transmit Enable O AB4
pr2_mii_mr1_clk MII1 Receive Clock I AC9
pr2_mii_mt1_clk MII1 Transmit Clock I AC5
pr2_uart0_cts_n UART Clear-To-Send I D8
pr2_uart0_rts_n UART Ready-To-Send O A5
pr2_uart0_rxd UART Receive Data I C6
pr2_uart0_txd UART Transmit Data O C8
pr2_ecap0_ecap_capin_apwm_o Capture Input / PWM output IO C7

NOTE

PRU-ICSS has an internal wrapper multiplexing that allows MII_RT, EnDAT, and Sigma Delta functionality to be muxed with the PRU GPIO signals. See PRU-ICSS IO Interface in device TRM. Additionally, the EGPIO module can also be configured to export additional functions to EGPIO pins in place of simple GPIO. See Enhanced General-Purpose Module/Serial Capture Unit in device TRM.

4.4.25 Test Interfaces

CAUTION

The I/O timing provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 7-176.

NOTE

For more information, see the On-Chip Debug Support / Debug Ports section of the device TRM.

Table 4-28 Debug Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
tms JTAG test port mode select. An external pullup resistor should be used on this ball. IO F18
tdi JTAG test data I D23
tdo JTAG test port data O F19
tclk JTAG test clock I E20
trstn JTAG test reset I D20
rtck JTAG return clock O E18
emu0 Emulator pin 0 IO G21
emu1 Emulator pin 1 IO D24
emu2 Emulator pin 2 O F10
emu3 Emulator pin 3 O D7
emu4 Emulator pin 4 O A7
emu5 Emulator pin 5 O E1 / G11
emu6 Emulator pin 6 O G2 / E9
emu7 Emulator pin 7 O H7 / F9
emu8 Emulator pin 8 O G1 / F8
emu9 Emulator pin 9 O G6 / E7
emu10 Emulator pin 10 O F2 / D8
emu11 Emulator pin 11 O F3 / A5
emu12 Emulator pin 12 O D1 / C6
emu13 Emulator pin 13 O E2 / C8
emu14 Emulator pin 14 O D2 / C7
emu15 Emulator pin 15 O F4 / A8
emu16 Emulator pin 16 O C1 / C9
emu17 Emulator pin 17 O E4 / A9
emu18 Emulator pin 18 O F5 / B9
emu19 Emulator pin 19 O E6 / A10

4.4.26 System and Miscellaneous

4.4.26.1 Sysboot

NOTE

For more information, see the Initialization (ROM Code) section of the device TRM.

Table 4-29 Sysboot Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
sysboot0 Boot Mode Configuration 0. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I M6
sysboot1 Boot Mode Configuration 1. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I M2
sysboot2 Boot Mode Configuration 2. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L5
sysboot3 Boot Mode Configuration 3. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I M1
sysboot4 Boot Mode Configuration 4. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L6
sysboot5 Boot Mode Configuration 5. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L4
sysboot6 Boot Mode Configuration 6. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L3
sysboot7 Boot Mode Configuration 7. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L2
sysboot8 Boot Mode Configuration 8. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I L1
sysboot9 Boot Mode Configuration 9. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I K2
sysboot10 Boot Mode Configuration 10. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I J1
sysboot11 Boot Mode Configuration 11. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I J2
sysboot12 Boot Mode Configuration 12. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I H1
sysboot13 Boot Mode Configuration 13. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I J3
sysboot14 Boot Mode Configuration 14. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I H2
sysboot15 Boot Mode Configuration 15. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I H3

4.4.26.2 Power, Reset, and Clock Management (PRCM)

NOTE

For more information, see PRCM section of the device TRM.

Table 4-30 PRCM Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
clkout1 Device Clock output 1. Can be used externally for devices with non-critical timing requirements, or for debug, or as a reference clock on GPMC as described in Table 7-23 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-25 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate. O F21 / P7
clkout2 Device Clock output 2. Can be used externally for devices with non-critical timing requirements, or for debug. O D18 / N1
clkout3 Device Clock output 3. Can be used externally for devices with non-critical timing requirements, or for debug. O C23
rstoutn Reset out (Active low).This pin asserts low in response to any global reset condition on the device.(2) O F23
resetn Device Reset Input I E23
porz Power on Reset (active low).This pin must be asserted low until all device supplies are valid (see reset sequence/requirements) I F22
xref_clk0 External Reference Clock 0. For Audio and other Peripherals. I D18
xref_clk1 External Reference Clock 1. For Audio and other Peripherals. I E17
xref_clk2 External Reference Clock 2. For Audio and other Peripherals. I B26
xref_clk3 External Reference Clock 3. For Audio and other Peripherals. I C23
xi_osc0 System Oscillator OSC0 Crystal input / LVCMOS clock input.Functions as the input connection to a crystal when the internal oscillator OSC0 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used. I AE15
xo_osc0 System Oscillator OSC0 Crystal output O AD15
xi_osc1 Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.Functions as the input connection to a crystal when the internal oscillator OSC1 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used I AC15
xo_osc1 Auxiliary Oscillator OSC1 Crystal output O AC13
RMII_MHZ_50_CLK(1) RMII Reference Clock (50MHz).This pin is an input when external reference is used or output when internal reference is used. IO U3
  1. This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
  2. Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.

4.4.26.3 Real-Time Clock (RTC) Interface

NOTE

For more information, see the Real-Time Clock (RTC) chapter of the device TRM.

NOTE

RTC only mode is not supported feature.

Table 4-31 RTC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Wakeup0 RTC External Wakeup Input 0 I AD17
Wakeup3 RTC External Wakeup Input 3 I AC16
rtc_porz RTC Power Domain Power-On Reset Input I AB17
rtc_osc_xi_clkin32 RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as an RTC clock input when an external oscillator is used. I AE14
rtc_osc_xo RTC Oscillator Output O AD14
rtc_iso(1) RTC Domain Isolation Signal I AF14
on_off RTC Power Enable output pin O Y11
  1. This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) with appropriate voltage level translation if necessary.

4.4.26.4 System Direct Memory Access (SDMA)

NOTE

For more information, see the DMA Controllers / System DMA section of the device TRM.

Table 4-32 SDMA Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
dma_evt1 System DMA Event Input 1 I P7 / P4
dma_evt2 System DMA Event Input 2 I N1 / R3
dma_evt3 System DMA Event Input 3 I N6
dma_evt4 System DMA Event Input 4 I M4

4.4.26.5 Interrupt Controllers (INTC)

NOTE

For more information, see the Interrupt Controllers section of the device TRM.

Table 4-33 INTC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
nmin_dsp Non maskable interrupt input, active-low. This pin can be optionally routed to the DSP NMI input or as generic input to the ARM cores. Note that by default this pin has an internal pulldown resistor enabled. This internal pulldown should be disabled or countered by a stronger external pullup resistor before routing to the DSP or ARM processors. I D21
sys_nirq2 External interrupt event to any device INTC I AD17
sys_nirq1 External interrupt event to any device INTC I AC16

4.4.26.6 Observability

NOTE

For more information, see the Control Module section of the device TRM.

Table 4-34 Observability Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
obs0 Observation Output 0 O F10
obs1 Observation Output 1 O G11
obs2 Observation Output 2 O E9
obs3 Observation Output 3 O F9
obs4 Observation Output 4 O F8
obs5 Observation Output 5 O D7
obs6 Observation Output 6 O D8
obs7 Observation Output 7 O A5
obs8 Observation Output 8 O C6
obs9 Observation Output 9 O C8
obs10 Observation Output 10 O C7
obs11 Observation Output 11 O A7
obs12 Observation Output 12 O A8
obs13 Observation Output 13 O C9
obs14 Observation Output 14 O A9
obs15 Observation Output 15 O B9
obs16 Observation Output 16 O F10
obs17 Observation Output 17 O G11
obs18 Observation Output 18 O E9
obs19 Observation Output 19 O F9
obs20 Observation Output 20 O F8
obs21 Observation Output 21 O D7
obs22 Observation Output 22 O D8
obs23 Observation Output 23 O A5
obs24 Observation Output 24 O C6
obs25 Observation Output 25 O C8
obs26 Observation Output 26 O C7
obs27 Observation Output 27 O A7
obs28 Observation Output 28 O A8
obs29 Observation Output 29 O C9
obs30 Observation Output 30 O A9
obs31 Observation Output 31 O B9
obs_dmarq1 DMA Request External Observation Output 1 O G11
obs_dmarq2 DMA Request External Observation Output 2 O D8
obs_irq1 IRQ External Observation Output 1 O F10
obs_irq2 IRQ External Observation Output 2 O D7

4.4.27 Power Supplies

NOTE

For more information, see Power, Reset and Clock Management / PRCM Subsystem Environment / External Voltage Inputs section of the device TRM.

Table 4-35 Power Supply Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
vdd Core voltage domain supply PWR H13 / H14 / J17 / J18 / L7 / L8 / N10 / N13 / P11 / P12 / P13 / R11 / R16 / R19 / T13 / T16 / T19 / U13 / U16 / U8 / U9 / V16 / V8
vss Ground GND A1 / A14 / A2 / A23 / A28 / A6 / AA14 / AA15 / AA20 / AA8 / AA9 / AB14 / AB20 / AD1 / AD24 / AG1 / AH1 / AH2 / AH20 / AH28 / B1 / D13 / D19 / E13 / E19 / F1 / F7 / G7 / G8 / G9 / H12 / J12 / J15 / J28 / K1 / K15 / K24 / K25 / K4 / K5 / L13 / L14 / M19 / N14 / N15 / N19 / N24 / N25 / P28 / R1 / R12 / R13 / R21 / T10 / T11 / T12 / T14 / T15 / T17 / T18 / T21 / U14 / U15 / U17 / U20 / U21 / V15 / V17 / W1 / W15 / W24 / W25 / W28
cap_vbbldo_gpu(1) External capacitor connection for the GPU vbb ldo output CAP Y14
cap_vbbldo_iva(1) External capacitor connection for the IVA vbb ldo output CAP J10
cap_vbbldo_mpu(1) External capacitor connection for the MPU vbb ldo output CAP J16
cap_vbbldo_dsp(1) External capacitor connection for the DSP vbb ldo output CAP K9
cap_vddram_core1(1) External capacitor connection for the Core SRAM array ldo1 output CAP T20
cap_vddram_core3(1) External capacitor connection for the Core SRAM array ldo3 output CAP L9
cap_vddram_core4(1) External capacitor connection for the Core SRAM array ldo4 output CAP J19
cap_vddram_mpu(1) External capacitor connection for the MPU SRAM array ldo output CAP K19
cap_vddram_gpu(1) External capacitor connection for the GPU SRAM array ldo output CAP Y13
cap_vddram_iva(1) External capacitor connection for the IVA SRAM array ldo output CAP K16
cap_vddram_dsp(1) External capacitor connection for the DSP CAP J9
vdda_dsp_iva DSP PLL and IVA PLL analog power supply PWR N12
vdda_core_gmac DPLL_CORE and CORE HSDIVIDER analog power supply PWR P14
vdda_pll_spare DPLL_SPARE analog power supply PWR P15
vdda_per DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply PWR M14
vdda_mpu_abe MPU_ABE PLL analog power supply PWR N16
vdda33v_usb1 HS USB1 3.3V analog power supply. If USB1 is not used, this pin can alternatively be connected to VSS if the following requirements are met:
- The usb1_dm/usb1_dp pins are left unconnected
- The USB1 PHY is kept powered down		 PWR AA12
vdda33v_usb2 HS USB2 3.3V analog power supply. If USB2 is not used, this pin can alternatively be connected to VSS if the following requirements are met:
- The usb2_dm/usb2_dp pins are left unconnected
- The USB2 PHY is kept powered down		 PWR Y12
vdda_ddr DPLL_DDR and DDR HSDIVIDER analog power supply PWR R17
vdda_debug DPLL_DEBUG analog power supply PWR N11
vdda_gpu DPLL_GPU analog power supply PWR R14
vdda_hdmi PLL_HDMI and HDMI analog power supply PWR Y17
vdda_osc HFOSC analog power supply PWR AD16 / AE16
vdda_pcie DPLL_PCIe_REF and PCIe analog power supply PWR AA17
vdda_pcie0 PCIe ch0 RX/TX analog power supply PWR AA16
vdda_rtc RTC bias and RTC LFOSC analog power supply PWR AB13
vdda_sata DPLL_SATA and SATA RX/TX analog power supply PWR V13
vdda_usb1 DPLL_USB and HS USB1 1.8V analog power supply PWR AA13
vdda_usb2 HS USB2 1.8V analog power supply PWR AB12
vdda_usb3 DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply PWR W14
vdda_csi CSI Interface 1.8V supply PWR W12
vdda_video VIDEO1 and VIDEO2 PLL analog power supply PWR P16
vdds18v 1.8V power supply PWR G18 / H17 / M8 / M9 / N8 / P8 / R8 / T8 / V21 / V22 / W17 / W18
vdds18v_ddr1 EMIF1 bias power supply PWR AA18 / AA19 / N21 / P20 / P21 / W21 / Y21
vddshv1 Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group pins PWR E3 / E5 / G4 / G5 / H8 / H9
vddshv2 Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group pins PWR B6 / D10 / E10 / H10 / H11
vddshv3 Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power Group pins PWR B23 / D16 / D22 / E16 / E22 / G15 / H15 / H16 / H18 / H19
vddshv4 Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group pins PWR C24
vddshv5 Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group pins PWR V12
vddshv6 Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group pins PWR AD5 / AD7 / AE7 / AF5
vddshv7 Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group pins PWR AB6 / AB7
vddshv8 Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group pins PWR W8 / Y8
vddshv9 Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group pins PWR U10 / W4 / W5
vddshv10 Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group pins PWR N4 / N5 / P10 / R10 / R7 / T4 / T5
vddshv11 Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group pins PWR J8 / K8
vdds_ddr1 EMIF1 power supply (1.5V for DDR3 mode / 1.35V DDR3L mode) PWR AA21 / AA22 / AB21 / AB22 / AB24 / AB25 / AC22 / AD26 / AG20 / AG28 / AH27 / T24 / T25 / W16 / W27
vdds_mlbp MLBP IO power supply PWR AA7 / Y7
vdd_dsp DSP voltage domain supply PWR K10 / K11 / L10 / L11 / M10 / M11
vdd_gpu GPU voltage domain supply PWR U11 / U12 / V10 / V11 / V14 / W10 / W11 / W13
vdd_iva IVA voltage domain supply PWR J13 / K12 / K13 / L12 / M12 / M13
vdd_mpu MPU voltage domain supply PWR K17 / K18 / L15 / L16 / L17 / L18 / L19 / M15 / M16 / M17 / M18 / N17 / N18 / P17 / P18 / R18
vdd_rtc RTC voltage domain supply PWR AB15
vssa_hdmi DPLL_HDMI and HDMI PHY analog ground GND AD19 / AE19
vssa_osc0 OSC0 analog ground GND AF15
vssa_osc1 OSC1 analog ground GND AC14
vssa_pcie PCIe analog ground GND AD13 / AE13
vssa_sata SATA analog ground GND AE10
vssa_usb HS USB1 and HS USB2 analog ground GND AA11 / AB11
vssa_usb3 DPLL_USB and USB3.0 RX/TX analog ground GND AD10
vssa_csi CSI Interface 0v Supply GND AA10 / AH8
vssa_video DPLL_VIDEO1 analog ground GND R15
  1. This pin must always be connected via a 1-µF capacitor to vss.