For more information, see Power, Reset, and Clock Management chapter in the device TRM.
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is still present in some clock or DPLL names.
The device operation requires the following clocks:
- The 32 kHz frequency is used for low frequency operation. It supplies the wake-up domain for operation in lowest power mode. This is an optional clock and will be supplied by on chip divider + mux (FUNC_32K_CLK) incase it is not available on external pin.
- The system clocks, SYS_CLK1 (Mandatory) and SYS_CLK2 (Optional) are the main clock sources of the device. They supply the reference clock to the DPLLs as well as functional clock to several modules.
The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the wake-up (WKUP) domain is supplied.
Figure 6-1 shows the external input clock sources and the output clocks to peripherals.
Figure 6-1 Clock Interface