Refer to the PDF data sheet for device specific package drawings
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe subsystem controller has support for PCIe Gen-II mode (5 Gbps per lane) and Gen-I mode (2.5 Gbps per lane) (Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and the PCI Local Bus Specification, revision 3.0.
For more information, see the PCIe Controller section of the Device TRM.