Refer to the PDF data sheet for device specific package drawings
TPS659037 is the Power Management IC (PMIC) that should be used for the Device designs. TI requires use of this PMIC for the following reasons:
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the most stringent of the rails combined should be implemented for the particular supply rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to ensure device reliability, it is still required that the supply pins for the specific voltage domains are connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain, thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
Table 8-1 illustrates the approved and validated power supply connections to the Device for the SMPS outputs of the TPS659037 PMIC.
|TPS659037 Power Supply||Valid Combination 1||Valid Combination 2|
|SMPS3||vdds_ddr1, vdds_ddr2||vdds_ddr1, vdds_ddr2|
|SMPS4/5||vdd_dspeve, vdd_gpu, vdd_iva||vdd_dspeve|
|SMPS7||SW configuration after boot||vdd|
|SMPS9||SW configuration after boot 3.3V||vddshvx|
|LDO3||vdda_usb1, vdda_usb2, vdda_usb3, vdda_sata||vdda_usb1, vdda_usb2, vdda_usb3, vdda_sata|
|LDO4||vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1||vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1|
|LDOLN||1.8V PLLs||1.8V PLLs|