SPRSP77D March   2023  – June 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  DSS
        1. 5.3.5.1 MAIN Domain
          1.        32
      7. 5.3.6  ECAP
        1. 5.3.6.1 MAIN Domain
          1.        35
          2.        36
          3.        37
      8. 5.3.7  Emulation and Debug
        1. 5.3.7.1 MAIN Domain
          1.        40
        2. 5.3.7.2 MCU Domain
          1.        42
      9. 5.3.8  EPWM
        1. 5.3.8.1 MAIN Domain
          1.        45
          2.        46
          3.        47
          4.        48
      10. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
          1.        51
          2.        52
          3.        53
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
        2. 5.3.10.2 MCU Domain
          1.        59
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        62
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        65
          2.        66
          3.        67
          4.        68
        2. 5.3.12.2 MCU Domain
          1.        70
        3. 5.3.12.3 WKUP Domain
          1.        72
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        75
        2. 5.3.13.2 MCU Domain
          1.        77
          2.        78
      15. 5.3.14 MCASP
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
          3.        83
      16. 5.3.15 MCSPI
        1. 5.3.15.1 MAIN Domain
          1.        86
          2.        87
          3.        88
        2. 5.3.15.2 MCU Domain
          1.        90
          2.        91
      17. 5.3.16 MDIO
        1. 5.3.16.1 MAIN Domain
          1.        94
      18. 5.3.17 MMC
        1. 5.3.17.1 MAIN Domain
          1.        97
          2.        98
          3.        99
      19. 5.3.18 OSPI
        1. 5.3.18.1 MAIN Domain
          1.        102
      20. 5.3.19 Power Supply
        1.       104
      21. 5.3.20 Reserved
        1.       106
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1. 5.3.21.1.1 MAIN Domain
            1.         110
        2. 5.3.21.2 Clock
          1. 5.3.21.2.1 MCU Domain
            1.         113
          2. 5.3.21.2.2 WKUP Domain
            1.         115
        3. 5.3.21.3 System
          1. 5.3.21.3.1 MAIN Domain
            1.         118
          2. 5.3.21.3.2 MCU Domain
            1.         120
          3. 5.3.21.3.3 WKUP Domain
            1.         122
        4. 5.3.21.4 VMON
          1.        124
      23. 5.3.22 TIMER
        1. 5.3.22.1 MAIN Domain
          1.        127
        2. 5.3.22.2 MCU Domain
          1.        129
        3. 5.3.22.3 WKUP Domain
          1.        131
      24. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
          1.        134
          2.        135
          3.        136
          4.        137
          5.        138
          6.        139
          7.        140
        2. 5.3.23.2 MCU Domain
          1.        142
        3. 5.3.23.3 WKUP Domain
          1.        144
      25. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
          1.        147
          2.        148
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5 SDIO Electrical Characteristics
      6. 6.8.6 LVCMOS Electrical Characteristics
      7. 6.8.7 CSI-2 (D-PHY) Electrical Characteristics
      8. 6.8.8 USB2PHY Electrical Characteristics
      9. 6.8.9 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for AMB and ANF Packages
    11. 6.11 Temperature Sensor Characteristics
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Timing Parameters and Information
      2. 6.12.2 Power Supply Requirements
        1. 6.12.2.1 Power Supply Slew Rate Requirement
        2. 6.12.2.2 Power Supply Sequencing
          1. 6.12.2.2.1 Power-Up Sequencing
          2. 6.12.2.2.2 Power-Down Sequencing
          3. 6.12.2.2.3 Partial IO Power Sequencing
      3. 6.12.3 System Timing
        1. 6.12.3.1 Reset Timing
        2. 6.12.3.2 Error Signal Timing
        3. 6.12.3.3 Clock Timing
      4. 6.12.4 Clock Specifications
        1. 6.12.4.1 Input Clocks / Oscillators
          1. 6.12.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.12.4.1.1.1 Load Capacitance
            2. 6.12.4.1.1.2 Shunt Capacitance
          2. 6.12.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.12.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.12.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.12.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.12.4.2 Output Clocks
        3. 6.12.4.3 PLLs
        4. 6.12.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.12.5 Peripherals
        1. 6.12.5.1  CPSW3G
          1. 6.12.5.1.1 CPSW3G MDIO Timing
          2. 6.12.5.1.2 CPSW3G RMII Timing
          3. 6.12.5.1.3 CPSW3G RGMII Timing
        2. 6.12.5.2  CPTS
        3. 6.12.5.3  CSI-2
        4. 6.12.5.4  DDRSS
        5. 6.12.5.5  DSS
        6. 6.12.5.6  ECAP
        7. 6.12.5.7  Emulation and Debug
          1. 6.12.5.7.1 Trace
          2. 6.12.5.7.2 JTAG
        8. 6.12.5.8  EPWM
        9. 6.12.5.9  EQEP
        10. 6.12.5.10 GPIO
        11. 6.12.5.11 GPMC
          1. 6.12.5.11.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.12.5.11.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.12.5.11.3 GPMC and NAND Flash — Asynchronous Mode
        12. 6.12.5.12 I2C
        13. 6.12.5.13 MCAN
        14. 6.12.5.14 MCASP
        15. 6.12.5.15 MCSPI
          1. 6.12.5.15.1 MCSPI — Controller Mode
          2. 6.12.5.15.2 MCSPI — Peripheral Mode
        16. 6.12.5.16 MMCSD
          1. 6.12.5.16.1 MMC0 - eMMC/SD/SDIO Interface
            1. 6.12.5.16.1.1  Legacy SDR Mode
            2. 6.12.5.16.1.2  High Speed SDR Mode
            3. 6.12.5.16.1.3  High Speed DDR Mode
            4. 6.12.5.16.1.4  HS200 Mode
            5. 6.12.5.16.1.5  Default Speed Mode
            6. 6.12.5.16.1.6  High Speed Mode
            7. 6.12.5.16.1.7  UHS–I SDR12 Mode
            8. 6.12.5.16.1.8  UHS–I SDR25 Mode
            9. 6.12.5.16.1.9  UHS–I SDR50 Mode
            10. 6.12.5.16.1.10 UHS–I DDR50 Mode
            11. 6.12.5.16.1.11 UHS–I SDR104 Mode
          2. 6.12.5.16.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.12.5.16.2.1 Default Speed Mode
            2. 6.12.5.16.2.2 High Speed Mode
            3. 6.12.5.16.2.3 UHS–I SDR12 Mode
            4. 6.12.5.16.2.4 UHS–I SDR25 Mode
            5. 6.12.5.16.2.5 UHS–I SDR50 Mode
            6. 6.12.5.16.2.6 UHS–I DDR50 Mode
            7. 6.12.5.16.2.7 UHS–I SDR104 Mode
        17. 6.12.5.17 OSPI
          1. 6.12.5.17.1 OSPI0 PHY Mode
            1. 6.12.5.17.1.1 OSPI0 With PHY Data Training
            2. 6.12.5.17.1.2 OSPI0 Without Data Training
              1. 6.12.5.17.1.2.1 OSPI0 PHY SDR Timing
              2. 6.12.5.17.1.2.2 OSPI0 PHY DDR Timing
          2. 6.12.5.17.2 OSPI0 Tap Mode
            1. 6.12.5.17.2.1 OSPI0 Tap SDR Timing
            2. 6.12.5.17.2.2 OSPI0 Tap DDR Timing
        18. 6.12.5.18 Timers
        19. 6.12.5.19 UART
        20. 6.12.5.20 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 MCU Arm Cortex-R5F Subsystem
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 C7xV-256 Deep Learning Accelerator
      2. 7.3.2 Vision Pre-processing Accelerator
      3. 7.3.3 JPEG Encoder
      4. 7.3.4 Video Accelerator
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  Display Subsystem (DSS)
      4. 7.5.4  Enhanced Capture (ECAP)
      5. 7.5.5  Error Location Module (ELM)
      6. 7.5.6  Enhanced Pulse Width Modulation (EPWM)
      7. 7.5.7  Error Signaling Module (ESM)
      8. 7.5.8  Enhanced Quadrature Encoder Pulse (EQEP)
      9. 7.5.9  General-Purpose Interface (GPIO)
      10. 7.5.10 General-Purpose Memory Controller (GPMC)
      11. 7.5.11 Global Timebase Counter (GTC)
      12. 7.5.12 Inter-Integrated Circuit (I2C)
      13. 7.5.13 Modular Controller Area Network (MCAN)
      14. 7.5.14 Multichannel Audio Serial Port (MCASP)
      15. 7.5.15 Multichannel Serial Peripheral Interface (MCSPI)
      16. 7.5.16 Multi-Media Card Secure Digital (MMCSD)
      17. 7.5.17 Octal Serial Peripheral Interface (OSPI)
      18. 7.5.18 Timers
      19. 7.5.19 Universal Asynchronous Receiver/Transmitter (UART)
      20. 7.5.20 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ANF|484
  • AMB|484
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-48 Power Supply Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]AMB PIN [4]ANF PIN [4]
CAP_VDDS0 (1)CAPExternal capacitor connection for IO group 0G13G13
CAP_VDDS1 (1)CAPExternal capacitor connection for IO group 1K16K16
CAP_VDDS2 (1)CAPExternal capacitor connection for IO group 2T14T14
CAP_VDDS3 (1)CAPExternal capacitor connection for IO group 3M16M16
CAP_VDDS4 (1)CAPExternal capacitor connection for IO group 4R8R8
CAP_VDDS5 (1)CAPExternal capacitor connection for IO group 5G15G15
CAP_VDDS6 (1)CAPExternal capacitor connection for IO group 6J16J16
CAP_VDDS_CANUART (1)CAPExternal capacitor connection for IO CANUARTG8G8
CAP_VDDS_MCU (1)CAPExternal capacitor connection for IO MCUG10G10
VDDA_1P8_USBPWRUSB0 and USB1 1.8V analog supplyT10T10
VDDA_1P8_CSIRX0PWRCSIRX0 1.8V analog supplyT12T12
VDDA_3P3_USBPWRUSB0 and USB1 3.3V analog supplyU10U10
VDDA_CORE_CSIRX0PWRCSIRX0 core supplyT11T11
VDDA_CORE_USBPWRUSB0 and USB1 core supplyT9T9
VDDA_DDR_PLL0PWRDDR Deskew PLL supplyM9M9
VDDA_MCUPWRRCOSC, POR, POK, and MCU_PLL0 analog supplyJ10J10
VDDA_PLL0PWRMAIN_PLL0 and MAIN_PLL5 analog supplyN9N9
VDDA_PLL1PWRMAIN_PLL1 and MAIN_PLL2 analog supplyR11R11
VDDA_PLL2PWRMAIN_PLL7 and MAIN_PLL17 analog supplyM13M13
VDDA_PLL3PWRMAIN_PLL8 and MAIN_PLL15 analog supplyK13K13
VDDA_PLL4PWRMAIN_PLL12 analog supplyK10K10
VDDA_TEMP0PWRTEMP0 analog supplyP16P16
VDDA_TEMP1PWRTEMP1 analog supplyG18G18
VDDA_TEMP2PWRTEMP2 analog supplyL10L10
VDDR_COREPWRRAM supplyJ14, K12, M10, M14, P12, P9J14, K12, M10, M14, P12, P9
VDDSHV0PWRIO supply for IO group 0G14, H13G14, H13
VDDSHV1PWRIO supply for IO group 1K15, L16K15, L16
VDDSHV2PWRIO supply for IO group 2R13, T13, U13R13, T13, U13
VDDSHV3PWRIO supply for IO group 3L15, M15, N15L15, M15, N15
VDDSHV4PWRIO supply for IO group 4T8, U8T8, U8
VDDSHV5PWRIO supply for IO group 5G16, H15G16, H15
VDDSHV6PWRIO supply for IO group 6H16, H17H16, H17
VDDSHV_CANUARTPWRIO supply for IO CANUARTH8H8
VDDSHV_MCUPWRIO supply for IO MCUG11, H10G11, H10
VDDS_DDRPWRDDR PHY IO supplyA2, AA1, AB2, B1, J7, K8, L7, M8, N7, P8A2, AA1, AB2, B1, J7, K8, L7, M8, N7, P8
VDDS_DDR_CPWRDDR clock IO supplyL8L8
VDDS_OSC0PWRMCU_OSC0 supplyJ8J8
VDD_CANUARTPWRCANUART Core SupplyH9H9
VDD_COREPWRCore supplyJ11, J13, J15, J9, K14, L11, L13, L9, M12, N11, N13, P10, P14, R15, R9, T16, U15J11, J13, J15, J9, K14, L11, L13, L9, M12, N11, N13, P10, P14, R15, R9, T16, U15
VPPPWReFuse ROM programming supplyF7F7
VSSPWRGroundA1, A10, A13, A18, A22, A4, A6, AA11, AA14, AA2, AA4, AA8, AB1, AB12, AB15, AB18, AB22, AB3, AB5, AB9, B3, B5, B7, C4, D11, D2, D20, D4, E1, E3, E5, F11, F13, F16, F2, F4, G12, G17, G3, G5, G9, H1, H11, H14, H20, H4, J12, J17, J3, K1, K11, K4, K7, K9, L12, L14, L20, L3, M11, M17, M4, M7, N1, N10, N12, N14, N16, N8, P11, P13, P15, P17, P20, P7, R10, R12, R14, R16, R2, R4, R6, T1, T15, T17, T3, T5, T7, U12, U14, U16, U2, U4, U6, U9, V1, V20, V3, V5, V7, V9, W11, W14, W2, W4, W6, W8, Y12, Y15, Y3, Y5, Y9A1, A10, A13, A18, A22, A4, A6, AA11, AA14, AA2, AA4, AA8, AB1, AB12, AB15, AB18, AB22, AB3, AB5, AB9, B3, B5, B7, C4, D11, D2, D20, D4, E1, E3, E5, F11, F13, F16, F2, F4, G12, G17, G3, G5, G9, H1, H11, H14, H20, H4, J12, J17, J3, K1, K11, K4, K7, K9, L12, L14, L20, L3, M11, M17, M4, M7, N1, N10, N12, N14, N16, N8, P11, P13, P15, P17, P20, P7, R10, R12, R14, R16, R2, R4, R6, T1, T15, T17, T3, T5, T7, U12, U14, U16, U2, U4, U6, U9, V1, V20, V3, V5, V7, V9, W11, W14, W2, W4, W6, W8, Y12, Y15, Y3, Y5, Y9
(1) This pin must always be connected via a 6.3V or greater, 0.8uF to 1.5μF capacitor to VSS if the respective VDDSHVx pin is ever operated at 3.3V. The capacitor selected must provide a capacitance within the defined range after it has been derated for DC-bias, operating temperature, and aging effects. There are three connection options if the respective VDDSHVx pin is only operated at 1.8V. The pin can be connected to the same decoupling capacitor that is required for 3.3V operation, it can be left unconnected, or it can be connected to the same 1.8V power source as the respective VDDSHVx pin.