SPRSP77D March   2023  – June 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  DSS
        1. 5.3.5.1 MAIN Domain
          1.        32
      7. 5.3.6  ECAP
        1. 5.3.6.1 MAIN Domain
          1.        35
          2.        36
          3.        37
      8. 5.3.7  Emulation and Debug
        1. 5.3.7.1 MAIN Domain
          1.        40
        2. 5.3.7.2 MCU Domain
          1.        42
      9. 5.3.8  EPWM
        1. 5.3.8.1 MAIN Domain
          1.        45
          2.        46
          3.        47
          4.        48
      10. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
          1.        51
          2.        52
          3.        53
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
        2. 5.3.10.2 MCU Domain
          1.        59
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        62
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        65
          2.        66
          3.        67
          4.        68
        2. 5.3.12.2 MCU Domain
          1.        70
        3. 5.3.12.3 WKUP Domain
          1.        72
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        75
        2. 5.3.13.2 MCU Domain
          1.        77
          2.        78
      15. 5.3.14 MCASP
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
          3.        83
      16. 5.3.15 MCSPI
        1. 5.3.15.1 MAIN Domain
          1.        86
          2.        87
          3.        88
        2. 5.3.15.2 MCU Domain
          1.        90
          2.        91
      17. 5.3.16 MDIO
        1. 5.3.16.1 MAIN Domain
          1.        94
      18. 5.3.17 MMC
        1. 5.3.17.1 MAIN Domain
          1.        97
          2.        98
          3.        99
      19. 5.3.18 OSPI
        1. 5.3.18.1 MAIN Domain
          1.        102
      20. 5.3.19 Power Supply
        1.       104
      21. 5.3.20 Reserved
        1.       106
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1. 5.3.21.1.1 MAIN Domain
            1.         110
        2. 5.3.21.2 Clock
          1. 5.3.21.2.1 MCU Domain
            1.         113
          2. 5.3.21.2.2 WKUP Domain
            1.         115
        3. 5.3.21.3 System
          1. 5.3.21.3.1 MAIN Domain
            1.         118
          2. 5.3.21.3.2 MCU Domain
            1.         120
          3. 5.3.21.3.3 WKUP Domain
            1.         122
        4. 5.3.21.4 VMON
          1.        124
      23. 5.3.22 TIMER
        1. 5.3.22.1 MAIN Domain
          1.        127
        2. 5.3.22.2 MCU Domain
          1.        129
        3. 5.3.22.3 WKUP Domain
          1.        131
      24. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
          1.        134
          2.        135
          3.        136
          4.        137
          5.        138
          6.        139
          7.        140
        2. 5.3.23.2 MCU Domain
          1.        142
        3. 5.3.23.3 WKUP Domain
          1.        144
      25. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
          1.        147
          2.        148
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5 SDIO Electrical Characteristics
      6. 6.8.6 LVCMOS Electrical Characteristics
      7. 6.8.7 CSI-2 (D-PHY) Electrical Characteristics
      8. 6.8.8 USB2PHY Electrical Characteristics
      9. 6.8.9 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for AMB and ANF Packages
    11. 6.11 Temperature Sensor Characteristics
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Timing Parameters and Information
      2. 6.12.2 Power Supply Requirements
        1. 6.12.2.1 Power Supply Slew Rate Requirement
        2. 6.12.2.2 Power Supply Sequencing
          1. 6.12.2.2.1 Power-Up Sequencing
          2. 6.12.2.2.2 Power-Down Sequencing
          3. 6.12.2.2.3 Partial IO Power Sequencing
      3. 6.12.3 System Timing
        1. 6.12.3.1 Reset Timing
        2. 6.12.3.2 Error Signal Timing
        3. 6.12.3.3 Clock Timing
      4. 6.12.4 Clock Specifications
        1. 6.12.4.1 Input Clocks / Oscillators
          1. 6.12.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.12.4.1.1.1 Load Capacitance
            2. 6.12.4.1.1.2 Shunt Capacitance
          2. 6.12.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.12.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.12.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.12.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.12.4.2 Output Clocks
        3. 6.12.4.3 PLLs
        4. 6.12.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.12.5 Peripherals
        1. 6.12.5.1  CPSW3G
          1. 6.12.5.1.1 CPSW3G MDIO Timing
          2. 6.12.5.1.2 CPSW3G RMII Timing
          3. 6.12.5.1.3 CPSW3G RGMII Timing
        2. 6.12.5.2  CPTS
        3. 6.12.5.3  CSI-2
        4. 6.12.5.4  DDRSS
        5. 6.12.5.5  DSS
        6. 6.12.5.6  ECAP
        7. 6.12.5.7  Emulation and Debug
          1. 6.12.5.7.1 Trace
          2. 6.12.5.7.2 JTAG
        8. 6.12.5.8  EPWM
        9. 6.12.5.9  EQEP
        10. 6.12.5.10 GPIO
        11. 6.12.5.11 GPMC
          1. 6.12.5.11.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.12.5.11.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.12.5.11.3 GPMC and NAND Flash — Asynchronous Mode
        12. 6.12.5.12 I2C
        13. 6.12.5.13 MCAN
        14. 6.12.5.14 MCASP
        15. 6.12.5.15 MCSPI
          1. 6.12.5.15.1 MCSPI — Controller Mode
          2. 6.12.5.15.2 MCSPI — Peripheral Mode
        16. 6.12.5.16 MMCSD
          1. 6.12.5.16.1 MMC0 - eMMC/SD/SDIO Interface
            1. 6.12.5.16.1.1  Legacy SDR Mode
            2. 6.12.5.16.1.2  High Speed SDR Mode
            3. 6.12.5.16.1.3  High Speed DDR Mode
            4. 6.12.5.16.1.4  HS200 Mode
            5. 6.12.5.16.1.5  Default Speed Mode
            6. 6.12.5.16.1.6  High Speed Mode
            7. 6.12.5.16.1.7  UHS–I SDR12 Mode
            8. 6.12.5.16.1.8  UHS–I SDR25 Mode
            9. 6.12.5.16.1.9  UHS–I SDR50 Mode
            10. 6.12.5.16.1.10 UHS–I DDR50 Mode
            11. 6.12.5.16.1.11 UHS–I SDR104 Mode
          2. 6.12.5.16.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.12.5.16.2.1 Default Speed Mode
            2. 6.12.5.16.2.2 High Speed Mode
            3. 6.12.5.16.2.3 UHS–I SDR12 Mode
            4. 6.12.5.16.2.4 UHS–I SDR25 Mode
            5. 6.12.5.16.2.5 UHS–I SDR50 Mode
            6. 6.12.5.16.2.6 UHS–I DDR50 Mode
            7. 6.12.5.16.2.7 UHS–I SDR104 Mode
        17. 6.12.5.17 OSPI
          1. 6.12.5.17.1 OSPI0 PHY Mode
            1. 6.12.5.17.1.1 OSPI0 With PHY Data Training
            2. 6.12.5.17.1.2 OSPI0 Without Data Training
              1. 6.12.5.17.1.2.1 OSPI0 PHY SDR Timing
              2. 6.12.5.17.1.2.2 OSPI0 PHY DDR Timing
          2. 6.12.5.17.2 OSPI0 Tap Mode
            1. 6.12.5.17.2.1 OSPI0 Tap SDR Timing
            2. 6.12.5.17.2.2 OSPI0 Tap DDR Timing
        18. 6.12.5.18 Timers
        19. 6.12.5.19 UART
        20. 6.12.5.20 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 MCU Arm Cortex-R5F Subsystem
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 C7xV-256 Deep Learning Accelerator
      2. 7.3.2 Vision Pre-processing Accelerator
      3. 7.3.3 JPEG Encoder
      4. 7.3.4 Video Accelerator
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  Display Subsystem (DSS)
      4. 7.5.4  Enhanced Capture (ECAP)
      5. 7.5.5  Error Location Module (ELM)
      6. 7.5.6  Enhanced Pulse Width Modulation (EPWM)
      7. 7.5.7  Error Signaling Module (ESM)
      8. 7.5.8  Enhanced Quadrature Encoder Pulse (EQEP)
      9. 7.5.9  General-Purpose Interface (GPIO)
      10. 7.5.10 General-Purpose Memory Controller (GPMC)
      11. 7.5.11 Global Timebase Counter (GTC)
      12. 7.5.12 Inter-Integrated Circuit (I2C)
      13. 7.5.13 Modular Controller Area Network (MCAN)
      14. 7.5.14 Multichannel Audio Serial Port (MCASP)
      15. 7.5.15 Multichannel Serial Peripheral Interface (MCSPI)
      16. 7.5.16 Multi-Media Card Secure Digital (MMCSD)
      17. 7.5.17 Octal Serial Peripheral Interface (OSPI)
      18. 7.5.18 Timers
      19. 7.5.19 Universal Asynchronous Receiver/Transmitter (UART)
      20. 7.5.20 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ANF|484
  • AMB|484
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Table 5-23 GPIO1 Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]AMB PIN [4]ANF PIN [4]
GPIO1_0IOGeneral Purpose Input/OutputW17W17
GPIO1_1IOGeneral Purpose Input/OutputW18W18
GPIO1_2IOGeneral Purpose Input/OutputAA20AA20
GPIO1_3IOGeneral Purpose Input/OutputAA21AA21
GPIO1_4IOGeneral Purpose Input/OutputY20Y20
GPIO1_5IOGeneral Purpose Input/OutputAB21AB21
GPIO1_6IOGeneral Purpose Input/OutputAB20AB20
GPIO1_7IOGeneral Purpose Input/OutputC19C19
GPIO1_8IOGeneral Purpose Input/OutputB19B19
GPIO1_9IOGeneral Purpose Input/OutputB18B18
GPIO1_10IOGeneral Purpose Input/OutputB20B20
GPIO1_11IOGeneral Purpose Input/OutputA19A19
GPIO1_12IOGeneral Purpose Input/OutputA20A20
GPIO1_13IOGeneral Purpose Input/OutputB21B21
GPIO1_14IOGeneral Purpose Input/OutputA21A21
GPIO1_15IOGeneral Purpose Input/OutputD16D16
GPIO1_16 (1)IOGeneral Purpose Input/OutputC16C16
GPIO1_17IOGeneral Purpose Input/OutputA17A17
GPIO1_18IOGeneral Purpose Input/OutputB15B15
GPIO1_19IOGeneral Purpose Input/OutputE15E15
GPIO1_20IOGeneral Purpose Input/OutputE14E14
GPIO1_21IOGeneral Purpose Input/OutputD15D15
GPIO1_22IOGeneral Purpose Input/OutputF14F14
GPIO1_23IOGeneral Purpose Input/OutputC15C15
GPIO1_24IOGeneral Purpose Input/OutputB17B17
GPIO1_25IOGeneral Purpose Input/OutputC18C18
GPIO1_26IOGeneral Purpose Input/OutputD17D17
GPIO1_27IOGeneral Purpose Input/OutputE16E16
GPIO1_28IOGeneral Purpose Input/OutputC17C17
GPIO1_29IOGeneral Purpose Input/OutputE17E17
GPIO1_30IOGeneral Purpose Input/OutputB16B16
GPIO1_31 (1)IODGeneral Purpose Input/OutputF17F17
GPIO1_32 (1)IOGeneral Purpose Input/OutputAB8AB8
GPIO1_33 (1)IOGeneral Purpose Input/OutputW9W9
GPIO1_34 (1)IOGeneral Purpose Input/OutputW7W7
GPIO1_35 (1)IOGeneral Purpose Input/OutputY8Y8
GPIO1_36 (1)IOGeneral Purpose Input/OutputAA7AA7
GPIO1_37 (1)IOGeneral Purpose Input/OutputY7Y7
GPIO1_38 (1)IOGeneral Purpose Input/OutputAB6AB6
GPIO1_39 (1)IOGeneral Purpose Input/OutputAA6AA6
GPIO1_40 (1)IOGeneral Purpose Input/OutputAB7AB7
GPIO1_41 (1)IOGeneral Purpose Input/OutputY6Y6
GPIO1_42 (1)IOGeneral Purpose Input/OutputD22D22
GPIO1_43 (1)IOGeneral Purpose Input/OutputC22C22
GPIO1_44 (1)IOGeneral Purpose Input/OutputD21D21
GPIO1_45 (1)IOGeneral Purpose Input/OutputB22B22
GPIO1_46 (1)IOGeneral Purpose Input/OutputE22E22
GPIO1_47 (1)IOGeneral Purpose Input/OutputC21C21
GPIO1_48 (1)IOGeneral Purpose Input/OutputE18E18
GPIO1_49 (1)IOGeneral Purpose Input/OutputD18D18
GPIO1_50IOGeneral Purpose Input/OutputC20C20
GPIO1_51IOGeneral Purpose Input/OutputD19D19
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.