SBAS771D June   2017  – October 2024 AMC1303E0510 , AMC1303E0520 , AMC1303E2510 , AMC1303E2520 , AMC1303M0510 , AMC1303M0520 , AMC1303M2510 , AMC1303M2520

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: AMC1303x05x
    10. 6.10 Electrical Characteristics: AMC1303x25x
    11. 6.11 Switching Characteristics
    12. 6.12 Timing Diagrams
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
      5. 7.3.5 Manchester Coding Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Output
      2. 7.4.2 Output Behavior in Case of a Full-Scale Input
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Frequency Inverter Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Isolated Voltage Sensing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Best Design Practices
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
        1. 9.1.1.1 Isolation Glossary
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation
(2 × 0.0105mm)		 ≥ 0.021 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category
per IEC 60664-1		 Rated mains voltage ≤ 300VRMS I-IV
Rated mains voltage ≤ 600VRMS I-IV
Rated mains voltage ≤ 1000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage At ac voltage (bipolar) 2121 VPK
VIOWM Maximum-rated isolation working voltage At ac voltage (sine wave) 1500 VRMS
At dc voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification test)
VTEST = 1.2 × VIOTM, t = 1s (100% production test)		 7000 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50μs waveform per IEC 62368-1 9800 VPK
VIOSM Maximum surge isolation voltage(4) Tested in oil (qualification test), 1.2/50μs waveform per IEC 62368-1 12800 VPK
qpd Apparent charge(5) Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM = 2545VPK, tm = 10s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60s, Vpd(m) = 1.6 × VIORM = 3394VPK, tm = 10s		 ≤ 5
Method b1, at routine test (100% production) and type test,
Vini = VIOTM, tini = 1s, Vpd(m) = 1.875 × VIORM = 3977VPK, tm = 1s		 ≤ 5
CIO Barrier capacitance,
input to output(6)		 VIO = 0.5VPP at 1MHz ~1 pF
RIO Insulation resistance,
input to output(6)		 VIO = 500V at TA = 25°C > 1012 Ω
VIO = 500V at 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500V at TS = 150°C > 109 Ω
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification),
VTEST = 1.2 × VISO, t = 1s (100% production test)		 5000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Maintain the creepage and clearance distance of a board design and make sure the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings is specified by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.