SWRS296A July   2023  – February 2024 AWRL1432

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
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      14.      24
      15.      25
      16.      26
      17.      27
    3.     28
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
      1. 7.5.1 Power Optimized 3.3V I/O Topology
      2. 7.5.2 BOM Optimized 3.3V I/O Topology
      3. 7.5.3 Power Optimized 1.8V I/O Topology
      4. 7.5.4 BOM Optimized 1.8V I/O Topology
      5. 7.5.5 System Topologies
        1. 7.5.5.1 Power Topologies
          1. 7.5.5.1.1 BOM Optimized Mode
          2. 7.5.5.1.2 Power Optimized Mode
      6. 7.5.6 Noise and Ripple Specifications
    6. 7.6  Power Save Modes
      1. 7.6.1 Typical Power Consumption Numbers
    7. 7.7  Peak Current Requirement per Voltage Rail
    8. 7.8  RF Specification
    9. 7.9  Supported DFE Features
    10. 7.10 CPU Specifications
    11. 7.11 Thermal Resistance Characteristics
    12. 7.12 Timing and Switching Characteristics
      1. 7.12.1  Power Supply Sequencing and Reset Timing
      2. 7.12.2  Synchronized Frame Triggering
      3. 7.12.3  Input Clocks and Oscillators
        1. 7.12.3.1 Clock Specifications
      4. 7.12.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.12.4.1 McSPI Features
        2. 7.12.4.2 SPI Timing Conditions
        3. 7.12.4.3 SPI—Controller Mode
          1. 7.12.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.12.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.12.4.4 SPI—Peripheral Mode
          1. 7.12.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.12.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.12.5  RDIF Interface Configuration
        1. 7.12.5.1 RDIF Interface Timings
        2. 7.12.5.2 RDIF Data Format
      6. 7.12.6  LIN
      7. 7.12.7  General-Purpose Input/Output
        1. 7.12.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.12.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 7.12.9  Serial Communication Interface (SCI)
        1. 7.12.9.1 SCI Timing Requirements
      10. 7.12.10 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.10.1 I2C Timing Requirements
      11. 7.12.11 Quad Serial Peripheral Interface (QSPI)
        1. 7.12.11.1 QSPI Timing Conditions
        2. 7.12.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.12.11.3 QSPI Switching Characteristics
      12. 7.12.12 JTAG Interface
        1. 7.12.12.1 JTAG Timing Conditions
        2. 7.12.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.12.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Automotive Interface
      7. 8.3.7 Host Interface
      8. 8.3.8 Main Subsystem Cortex-M4F
      9. 8.3.9 Hardware Accelerator (HWA1.2) Features
        1. 8.3.9.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 8.4 Other Subsystems
      1. 8.4.1 GPADC Channels (Service) for User Application
      2. 8.4.2 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • AMF|102
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.12.10.1 I2C Timing Requirements

STANDARD MODE(1)FAST MODEUNIT
MINMAXMINMAX
tc(SCL)Cycle time, SCL102.5μs
tsu(SCLH-SDAL)Setup time, SCL high before SDA low
(for a repeated START condition)		4.70.6μs
th(SCLL-SDAL)Hold time, SCL low after SDA low
(for a START and a repeated START condition)		40.6μs
tw(SCLL)Pulse duration, SCL low4.71.3μs
tw(SCLH)Pulse duration, SCL high40.6μs
tsu(SDA-SCLH)Setup time, SDA valid before SCL high250100μs
th(SCLL-SDA)Hold time, SDA valid after SCL low03.45(1)00.9μs
tw(SDAH)Pulse duration, SDA high between STOP and START conditions4.71.3μs
tsu(SCLH-SDAH)Setup time, SCL high before SDA high
(for STOP condition)		40.6μs
tw(SP)Pulse duration, spike (must be suppressed)050ns
Cb(2)(3)Capacitive load for each bus line400400pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
GUID-3653C253-8E5C-454D-BA01-0F324267D1DB-low.gifFigure 7-15 I2C Timing Diagram
Note:
  • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
  • The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).