SWRS296A
July 2023 – February 2024
AWRL1432
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Functional Block Diagram
5
Device Comparison
5.1
Related Products
6
Terminal Configurations and Functions
6.1
Pin Diagrams
6.2
Signal Descriptions
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Power-On Hours (POH)
7.4
Recommended Operating Conditions
7.5
Power Supply Specifications
7.5.1
Power Optimized 3.3V I/O Topology
7.5.2
BOM Optimized 3.3V I/O Topology
7.5.3
Power Optimized 1.8V I/O Topology
7.5.4
BOM Optimized 1.8V I/O Topology
7.5.5
System Topologies
7.5.5.1
Power Topologies
7.5.5.1.1
BOM Optimized Mode
7.5.5.1.2
Power Optimized Mode
7.5.6
Noise and Ripple Specifications
7.6
Power Save Modes
7.6.1
Typical Power Consumption Numbers
7.7
Peak Current Requirement per Voltage Rail
7.8
RF Specification
7.9
Supported DFE Features
7.10
CPU Specifications
7.11
Thermal Resistance Characteristics
7.12
Timing and Switching Characteristics
7.12.1
Power Supply Sequencing and Reset Timing
7.12.2
Synchronized Frame Triggering
7.12.3
Input Clocks and Oscillators
7.12.3.1
Clock Specifications
7.12.4
MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
7.12.4.1
McSPI Features
7.12.4.2
SPI Timing Conditions
7.12.4.3
SPI—Controller Mode
7.12.4.3.1
Timing and Switching Requirements for SPI - Controller Mode
7.12.4.3.2
Timing and Switching Characteristics for SPI Output Timings—Controller Mode
7.12.4.4
SPI—Peripheral Mode
7.12.4.4.1
Timing and Switching Requirements for SPI - Peripheral Mode
7.12.4.4.2
Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
7.12.5
RDIF Interface Configuration
7.12.5.1
RDIF Interface Timings
7.12.5.2
RDIF Data Format
7.12.6
LIN
7.12.7
General-Purpose Input/Output
7.12.7.1
Switching Characteristics for Output Timing versus Load Capacitance (CL)
7.12.8
Controller Area Network - Flexible Data-rate (CAN-FD)
7.12.8.1
Dynamic Characteristics for the CANx TX and RX Pins
7.12.9
Serial Communication Interface (SCI)
7.12.9.1
SCI Timing Requirements
7.12.10
Inter-Integrated Circuit Interface (I2C)
7.12.10.1
I2C Timing Requirements
7.12.11
Quad Serial Peripheral Interface (QSPI)
7.12.11.1
QSPI Timing Conditions
7.12.11.2
Timing Requirements for QSPI Input (Read) Timings
7.12.11.3
QSPI Switching Characteristics
7.12.12
JTAG Interface
7.12.12.1
JTAG Timing Conditions
7.12.12.2
Timing Requirements for IEEE 1149.1 JTAG
7.12.12.3
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Subsystems
8.3.1
RF and Analog Subsystem
8.3.2
Clock Subsystem
8.3.3
Transmit Subsystem
8.3.4
Receive Subsystem
8.3.5
Processor Subsystem
8.3.6
Automotive Interface
8.3.7
Host Interface
8.3.8
Main Subsystem Cortex-M4F
8.3.9
Hardware Accelerator (HWA1.2) Features
8.3.9.1
Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
8.4
Other Subsystems
8.4.1
GPADC Channels (Service) for User Application
8.4.2
GPADC Parameters
8.5
Memory Partitioning Options
8.6
Boot Modes
9
Applications, Implementation, and Layout
9.1
Application Information
9.2
Reference Schematic
10
Device and Documentation Support
10.1
Device Nomenclature
10.2
Tools and Software
10.3
Documentation Support
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
AMF|102
Thermal pad, mechanical data (Package|Pins)
Orderable Information
swrs296a_oa
1
Features
FMCW Transceiver
Integrated PLL, transmitter, receiver, baseband and ADC
76-81GHz coverage with 5GHz continuous bandwidth
3 receive channels and 2 transmit channels
Short range
11dBm typical output power per Tx
14.5dB typical noise figure
-89dBc/Hz typical phase noise at 1MHz
FMCW operation
5MHz IF bandwidth, real-only Rx channels
Ultra-accurate chirp engine based on fractional-N PLL
Per transmitter binary phase shifter
Processing elements
Arm®
M4F®
core with single precision FPU (160 MHz)
TI Radar Hardware Accelerator (HWA 1.2) for FFT, Log Magnitude, and CFAR operations (80MHz)
Supports multiple low-power modes
Idle mode and deep sleep mode
Power management
1.8V and 3.3V IO support
Built-in LDO network for enhanced PSRR
BOM-Optimized and Power-Optimized modes
One or two power rails for 1.8V IO mode, two or three power rails for 3.3V IO mode
Package size of FCCSP device: 6.45mm x 6.45mm
Built-in calibration and self-test
Built-in firmware (ROM)
Self-Contained on chip calibration system
Host Interface
UART
CAN-FD
SPI
LIN
RDIF (Radar Data Interface) for raw ADC sample capture
Other interfaces available to user application
QSPI
I2C
JTAG
GPIOs
PWM Interface
Internal Memory
1MB of On-Chip RAM
Configurable L3 shared memory for Radar Cube
Data and Code RAM of (512/640/768KB)
Functional Safety-Compliant Targeted
Developed for Functional Safety Applications
Hardware integrity up to ASIL B targeted
FCCSP package with 12 x 12, 102 BGA balls
AEC Q-100 Qualified
Clock source
40.0MHz Crystal for primary clock
Supports externally driven clock (Square/Sine) at 40.0MHz
32kHz internal oscillator for low power operations
Supports temperature operating range
Operating Junction Temperature Range: –40°C to 125°C