SLUSEG4B December   2022  – February 2024 BQ25628 , BQ25629

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 REGN LDO Power Up
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 D+/D– Detection Sets Input Current Limit (BQ25629)
        4. 8.3.3.4 ILIM Pin (BQ25628 Only)
        5. 8.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        6. 8.3.3.6 Converter Power-Up
      4. 8.3.4  Power Path Management
        1. 8.3.4.1 Narrow VDC Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 High Impedance Mode
      5. 8.3.5  Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.5.4.2 TS Pin Thermistor Configuration
          3. 8.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 8.3.5.4.4 JEITA Charge Rate Scaling
          5. 8.3.5.4.5 TS_BIAS Pin
        5. 8.3.5.5 Charging Safety Timers
      6. 8.3.6  USB On-The-Go (OTG)
        1. 8.3.6.1 Boost OTG Mode
        2. 8.3.6.2 Bypass OTG Mode
        3. 8.3.6.3 PMID Voltage Indicator (PMID_GD)
      7. 8.3.7  Integrated 12-Bit ADC for Monitoring
      8. 8.3.8  Status Outputs ( STAT, INT)
        1. 8.3.8.1 Interrupts and Status, Flag and Mask Bits
        2. 8.3.8.2 Charging Status Indicator (STAT)
        3. 8.3.8.3 Interrupt to Host ( INT)
      9. 8.3.9  BATFET Control
        1. 8.3.9.1 Shutdown Mode
        2. 8.3.9.2 Ship Mode
        3. 8.3.9.3 System Power Reset
      10. 8.3.10 Protections
        1. 8.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.10.1.1 Battery Undervoltage Lockout
          2. 8.3.10.1.2 Battery Overcurrent Protection
        2. 8.3.10.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.10.2.1 Input Overvoltage
          2. 8.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.10.2.4 System Short
          5. 8.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.10.2.6 Sleep and Poor Source Comparators
          7. 8.3.10.2.7 PMID OVP and VBUS Overcurrent
        3. 8.3.10.3 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.3.1 Boost Mode Overvoltage Protection
          2. 8.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 8.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 8.3.10.3.4 Boost Mode Battery Undervoltage
          5. 8.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 8.3.10.3.6 Boost Mode SYS Short
        4. 8.3.10.4 Voltage and Current Monitoring in Bypass Mode
          1. 8.3.10.4.1 Bypass Mode Overvoltage Protection
          2. 8.3.10.4.2 Bypass Mode Battery OCP
          3. 8.3.10.4.3 Bypass Mode Reverse-Current Protection
          4. 8.3.10.4.4 Bypass Mode Battery Undervoltage
          5. 8.3.10.4.5 Bypass Mode SYS Short
          6. 8.3.10.4.6 Bypass Mode REGN Fault
        5. 8.3.10.5 Thermal Regulation and Thermal Shutdown
          1. 8.3.10.5.1 Thermal Protection in Buck Mode
          2. 8.3.10.5.2 Thermal Protection in Boost Mode
          3. 8.3.10.5.3 Thermal Protection in Battery-Only Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25628 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RYK|18
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.2 BQ25628 Registers

Table 8-7 lists the memory-mapped registers for the BQ25628 registers. All register offset addresses not listed in Table 8-7 should be considered as reserved locations and the register contents should not be modified.

Table 8-7 BQ25628 Registers
AddressAcronymRegister NameSection
2hREG0x02_Charge_Current_LimitCharge Current LimitGo
4hREG0x04_Charge_Voltage_LimitCharge Voltage LimitGo
6hREG0x06_Input_Current_LimitInput Current LimitGo
8hREG0x08_Input_Voltage_LimitInput Voltage LimitGo
ChREG0x0C_VOTG_regulationVOTG regulationGo
EhREG0x0E_Minimal_System_VoltageMinimal System VoltageGo
10hREG0x10_Pre-charge_ControlPre-charge ControlGo
12hREG0x12_Termination_ControlTermination ControlGo
14hREG0x14_Charge_ControlCharge ControlGo
15hREG0x15_Charge_Timer_ControlCharge Timer ControlGo
16hREG0x16_Charger_Control_0Charger Control 0Go
17hREG0x17_Charger_Control_1Charger Control 1Go
18hREG0x18_Charger_Control_2Charger Control 2Go
19hREG0x19_Charger_Control_3Charger Control 3Go
1AhREG0x1A_NTC_Control_0NTC Control 0Go
1BhREG0x1B_NTC_Control_1NTC Control 1Go
1ChREG0x1C_NTC_Control_2NTC Control 2Go
1DhREG0x1D_Charger_Status_0Charger Status 0Go
1EhREG0x1E_Charger_Status_1Charger Status 1Go
1FhREG0x1F_FAULT_Status_0FAULT Status 0Go
20hREG0x20_Charger_Flag_0Charger Flag 0Go
21hREG0x21_Charger_Flag_1Charger Flag 1Go
22hREG0x22_FAULT_Flag_0FAULT Flag 0Go
23hREG0x23_Charger_Mask_0Charger Mask 0Go
24hREG0x24_Charger_Mask_1Charger Mask 1Go
25hREG0x25_FAULT_Mask_0FAULT Mask 0Go
26hREG0x26_ADC_ControlADC ControlGo
27hREG0x27_ADC_Function_Disable_0ADC Function Disable 0Go
28hREG0x28_IBUS_ADCIBUS ADCGo
2AhREG0x2A_IBAT_ADCIBAT ADCGo
2ChREG0x2C_VBUS_ADCVBUS ADCGo
2EhREG0x2E_VPMID_ADCVPMID ADCGo
30hREG0x30_VBAT_ADCVBAT ADCGo
32hREG0x32_VSYS_ADCVSYS ADCGo
34hREG0x34_TS_ADCTS ADCGo
36hREG0x36_TDIE_ADCTDIE ADCGo
38hREG0x38_Part_InformationPart InformationGo

Complex bit access types are encoded to fit into small table cells. Table 8-8 shows the codes that are used for access types in this section.

Table 8-8 BQ25628 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.6.2.1 REG0x02_Charge_Current_Limit Register (Address = 2h) [Reset = 0100h]

REG0x02_Charge_Current_Limit is shown in Figure 8-17 and described in Table 8-9.

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Charge Current Limit

Figure 8-17 REG0x02_Charge_Current_Limit Register
15141312111098
RESERVEDICHG
R-0hR/W-8h
76543210
ICHGRESERVED
R/W-8hR-0h
Table 8-9 REG0x02_Charge_Current_Limit Register Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR0h Reserved
10:5ICHGR/W8h Charge Current Regulation Limit:
This 16-bit register follows the little-endian convention.
ICHG[5:3] falls in REG0x03[2:0], and ICHG[2:0] falls in REG0x02[7:5].
POR: 320mA (8h)
Range: 40mA-2000mA (1h-32h)
Clamped Low
Clamped High
Bit Step: 40mA (1h)
NOTE: When Q4_FULLON=1, this register has a minimum value of 80mA
4:0RESERVEDR0h Reserved

8.6.2.2 REG0x04_Charge_Voltage_Limit Register (Address = 4h) [Reset = 0D20h]

REG0x04_Charge_Voltage_Limit is shown in Figure 8-18 and described in Table 8-10.

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Charge Voltage Limit

Figure 8-18 REG0x04_Charge_Voltage_Limit Register
15141312111098
RESERVEDVREG
R-0hR/W-1A4h
76543210
VREGRESERVED
R/W-1A4hR-0h
Table 8-10 REG0x04_Charge_Voltage_Limit Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0h Reserved
11:3VREGR/W1A4h Battery Voltage Regulation Limit:
This 16-bit register follows the little-endian convention. VREG[8:5] falls in REG0x05[3:0], and VREG[4:0] falls in REG0x04[7:3].
POR: 4200mV (1A4h)
Range: 3500mV-4800mV (15Eh-1E0h)
Clamped Low
Clamped High
Bit Step: 10mV
2:0RESERVEDR0h Reserved

8.6.2.3 REG0x06_Input_Current_Limit Register (Address = 6h) [Reset = 0A00h]

REG0x06_Input_Current_Limit is shown in Figure 8-19 and described in Table 8-11.

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Input Current Limit

Figure 8-19 REG0x06_Input_Current_Limit Register
15141312111098
RESERVEDIINDPM
R-0hR/W-A0h
76543210
IINDPMRESERVED
R/W-A0hR-0h
Table 8-11 REG0x06_Input_Current_Limit Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0h Reserved
11:4IINDPMR/WA0h Input Current Regulation Limit:
This 16-bit register follows the little-endian convention. IINDPM[7:4] falls in REG0x07[3:0], and IINDPM[3:0] falls in REG0x06[7:4]. Based on D+/D- detection results:
USB SDP = 500mA
USB CDP = 1.5A
USB DCP = 1.5A
Unknown Adapter = 500mA
Non-Standard Adapter = 1A/2.1A/2.4A
POR: 3200mA (A0h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
When the adapter is removed, IINDPM is reset to its POR value of 3.2 A.
3:0RESERVEDR0h Reserved

8.6.2.4 REG0x08_Input_Voltage_Limit Register (Address = 8h) [Reset = 0E60h]

REG0x08_Input_Voltage_Limit is shown in Figure 8-20 and described in Table 8-12.

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Input Voltage Limit

Figure 8-20 REG0x08_Input_Voltage_Limit Register
15141312111098
RESERVEDVINDPM
R-0hR/W-73h
76543210
VINDPMRESERVED
R/W-73hR-0h
Table 8-12 REG0x08_Input_Voltage_Limit Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR0h Reserved
13:5VINDPMR/W73h Absolute Input Voltage Regulation Limit:
This 16-bit register follows the little-endian convention.
VINDPM[8:3] falls in REG0x09[5:0], and VINDPM[2:0] falls in REG0x08[7:5].

POR: 4600mV (73h)
Range: 3800mV-16800mV (5Fh-1A4h)
Clamped Low
Clamped High
Bit Step: 40mV
4:0RESERVEDR0h Reserved

8.6.2.5 REG0x0C_VOTG_regulation Register (Address = Ch) [Reset = 0FC0h]

REG0x0C_VOTG_regulation is shown in Figure 8-21 and described in Table 8-13.

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VOTG regulation

Figure 8-21 REG0x0C_VOTG_regulation Register
15141312111098
RESERVEDVOTG
R-0hR/W-3Fh
76543210
VOTGRESERVED
R/W-3FhR-0h
Table 8-13 REG0x0C_VOTG_regulation Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR0h Reserved
12:6VOTGR/W3Fh Boost mode regulation voltage:
This 16-bit register follows the little-endian convention. VOTG[6:2] falls in REG0x0D[4:0], and VOTG[1:0] falls in REG0x0C[7:6].
POR: 5040mV (3Fh)
Range: 3840mV-5200mV (30h-41h)
Clamped Low
Clamped High
Bit Step: 80mV
5:0RESERVEDR0h Reserved

8.6.2.6 REG0x0E_Minimal_System_Voltage Register (Address = Eh) [Reset = 0B00h]

REG0x0E_Minimal_System_Voltage is shown in Figure 8-22 and described in Table 8-14.

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Minimal System Voltage

Figure 8-22 REG0x0E_Minimal_System_Voltage Register
15141312111098
RESERVEDVSYSMIN
R-0hR/W-2Ch
76543210
VSYSMINRESERVED
R/W-2ChR-0h
Table 8-14 REG0x0E_Minimal_System_Voltage Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0h Reserved
11:6VSYSMINR/W2Ch Minimal System Voltage:
This 16-bit register follows the little-endian convention. VSYSMIN[5:2] falls in REG0x0F[3:0], and VSYSMIN[1:0] falls in REG0x0E[7:6].

POR: 3520mV (2Ch)
Range: 2560mV-3840mV (20h-30h)
Clamped Low
Clamped High
Bit Step: 80mV
5:0RESERVEDR0h Reserved

8.6.2.7 REG0x10_Pre-charge_Control Register (Address = 10h) [Reset = 0018h]

REG0x10_Pre-charge_Control is shown in Figure 8-23 and described in Table 8-15.

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Pre-charge Control

Figure 8-23 REG0x10_Pre-charge_Control Register
15141312111098
RESERVED
R-0h
76543210
IPRECHGRESERVED
R/W-3hR-0h
Table 8-15 REG0x10_Pre-charge_Control Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR0h Reserved
7:3IPRECHGR/W3h Pre-charge current regulation limit:
This 16-bit register follows the little-endian convention.

IPRECHG[4:0] falls in REG0x10[7:3]
POR: 30mA (3h)
Range: 10mA-310mA (1h-1Fh)
Clamped Low
Bit Step: 10mA (1h)
NOTE: When Q4_FULLON=1, this register has a minimum value of 80mA, so Reset value becomes 80mA in this case
2:0RESERVEDR0h Reserved

8.6.2.8 REG0x12_Termination_Control Register (Address = 12h) [Reset = 0010h]

REG0x12_Termination_Control is shown in Figure 8-24 and described in Table 8-16.

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Termination Control

Figure 8-24 REG0x12_Termination_Control Register
15141312111098
RESERVED
R-0h
76543210
ITERMRESERVED
R/W-4hR-0h
Table 8-16 REG0x12_Termination_Control Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR0h Reserved
7:2ITERMR/W4h Termination Current Threshold:
This 16-bit register follows the little-endian convention.
ITERM[5:0] falls in REG0x12[7:2].
POR: 20mA (4h)
Range: 5mA-310mA (1h-3Eh)
Clamped Low
Bit Step: 5mA (1h)
NOTE: When Q4_FULLON=1, this register has a minimum value of 60mA, so Reset value becomes 60mA in this case
1:0RESERVEDR0h Reserved

8.6.2.9 REG0x14_Charge_Control Register (Address = 14h) [Reset = 06h]

REG0x14_Charge_Control is shown in Figure 8-25 and described in Table 8-17.

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Charge Control

Figure 8-25 REG0x14_Charge_Control Register
76543210
Q1_FULLONQ4_FULLONITRICKLETOPOFF_TMREN_TERMVINDPM_BAT_TRACKVRECHG
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-0h
Table 8-17 REG0x14_Charge_Control Register Field Descriptions
BitFieldTypeResetDescription
7Q1_FULLONR/W0h Forces RBFET (Q1) into low resistance state (26 mΩ) , regardless of IINDPM setting.

0h = RBFET RDSON determined by IINDPM setting (default)
1h = RBFET RDSON is always 26 mΩ
6Q4_FULLONR/W0h Forces BATFET (Q4) into low resistance state (15 mΩ), regardless of ICHG setting (Only applies when VBAT > VSYSMIN).

0h = BATFET RDSON determined by charge current (default)
1h = BATFET RDSON is always 15 mΩ
5ITRICKLER/W0h Trickle charging current setting:
0b = 10mA (default)
1b = 40mA
4:3TOPOFF_TMRR/W0h Top-off timer control:

0h = Disabled (default)
1h = 17 mins
2h = 35 mins
3h = 52 mins
2EN_TERMR/W1h Enable termination:

0h = Disable
1h = Enable (default)
1VINDPM_BAT_TRACKR/W1h Sets VINDPM to track BAT voltage. Actual VINDPM is higher of the VINDPM register value and VBAT + VINDPM_BAT_TRACK.

0h = Disable function (VINDPM set by register)
1h = VBAT + 400 mV (default)
0VRECHGR/W0h Battery Recharge Threshold Offset (Below VREG)

0h = 100mV (default)
1h = 200mV

8.6.2.10 REG0x15_Charge_Timer_Control Register (Address = 15h) [Reset = 5Ch]

REG0x15_Charge_Timer_Control is shown in Figure 8-26 and described in Table 8-18.

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Charge Timer Control

Figure 8-26 REG0x15_Charge_Timer_Control Register
76543210
DIS_STATEN_AUTO_INDETFORCE_INDETEN_DCP_BIASTMR2X_ENEN_SAFETY_TMRSPRECHG_TMRCHG_TMR
R/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-1hR/W-0hR/W-0h
Table 8-18 REG0x15_Charge_Timer_Control Register Field Descriptions
BitFieldTypeResetDescription
7DIS_STATR/W0h Disable the STAT pin output

0h = Enable (default)
1h = Disable
6EN_AUTO_INDETR/W1h Automatic D+/D- Detection Enable

0h = Disable DPDM detection when VBUS is plugged-in
1h = Enable DPDM detection when VBUS is plugged-in (default)
5FORCE_INDETR/W0h Force D+/D- detection

0h = Do not force DPDM detection (default)
1h = Force DPDM algorithm, when DPDM detection is done, this bit is reset to 0
4EN_DCP_BIASR/W1h Enable 600 mV bias on D+ pin whenever DCP is detected by BC1.2 detection algorithm (VBUS_STAT = 011b.)
0h = Disable 600 mV bias on D+ pin
1h = Enable 600 mV bias on D+ pin if DCP detected
3TMR2X_ENR/W1h 2X charging timer control

0h = Trickle charge, pre-charge and fast charge timer not slowed by 2X during input DPM or thermal regulation.
1h = Trickle charge, pre-charge and fast charge timer slowed by 2X during input DPM or thermal regulation (default)
2EN_SAFETY_TMRSR/W1h Enable fast charge, pre-charge and trickle charge timers

0h = Disable
1h = Enable (default)
1PRECHG_TMRR/W0h Pre-charge safety timer setting

0h = 2.5 hrs (default)
1h = 0.62 hrs
0CHG_TMRR/W0h Fast charge safety timer setting

0h = 14.5 hrs (default)
1h = 28 hrs

8.6.2.11 REG0x16_Charger_Control_0 Register (Address = 16h) [Reset = A1h]

REG0x16_Charger_Control_0 is shown in Figure 8-27 and described in Table 8-19.

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Charger Control 0

Figure 8-27 REG0x16_Charger_Control_0 Register
76543210
EN_AUTO_IBATDISFORCE_IBATDISEN_CHGEN_HIZFORCE_PMID_DISWD_RSTWATCHDOG
R/W-1hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
Table 8-19 REG0x16_Charger_Control_0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_AUTO_IBATDISR/W1h Enable the auto battery discharging during the battery OVP fault

0h = The charger does NOT apply a discharging current on BAT during battery OVP triggered
1h = The charger does apply a discharging current on BAT during battery OVP triggered (default)
6FORCE_IBATDISR/W0h Force a battery discharging current (~30mA)

0h = IDLE (default)
1h = Force the charger to apply a discharging current on BAT
5EN_CHGR/W1h Charger enable configuration

0h = Charge Disable
1h = Charge Enable (default)
4EN_HIZR/W0h Enable HIZ mode.

0h = Disable (default)
1h = Enable
3FORCE_PMID_DISR/W0h Force a PMID discharge current (~30mA.)

0h = Disable (default)
1h = Enable
2WD_RSTR/W0h I2C watch dog timer reset

0h = Normal (default)
1h = Reset (this bit goes back to 0 after timer reset)
1:0WATCHDOGR/W1h Watchdog timer setting

0h = Disable
1h = 50s (default)
2h = 100s
3h = 200s

8.6.2.12 REG0x17_Charger_Control_1 Register (Address = 17h) [Reset = 4Fh]

REG0x17_Charger_Control_1 is shown in Figure 8-28 and described in Table 8-20.

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Charger Control 1

Figure 8-28 REG0x17_Charger_Control_1 Register
76543210
REG_RSTTREGSET_CONV_FREQSET_CONV_STRNRESERVEDVBUS_OVP
R/W-0hR/W-1hR/W-0hR/W-3hR-0hR/W-1h
Table 8-20 REG0x17_Charger_Control_1 Register Field Descriptions
BitFieldTypeResetDescription
7REG_RSTR/W0h Reset registers to default values and reset timer
Value resets to 0 after reset completes.
0h = Not reset (default)
1h = Reset
6TREGR/W1h Thermal regulation thresholds.

0h = 60C
1h = 120C (default)
5:4SET_CONV_FREQR/W0h Adjust switching frequency of the converter
0h = Nominal, 1.5 MHz (default)
1h = -10%, 1.35 MHz
2h = +10%, 1.65 MHz
3h = RESERVED
3:2SET_CONV_STRNR/W3h Adjust the high side and low side drive strength of the converter to adjust efficiency versus EMI.

0h = weak
1h = normal
2h = RESERVED
3h = strong
1RESERVEDR0h Reserved
0VBUS_OVPR/W1h Sets VBUS overvoltage protection threshold

0h = 6.3 V
1h = 18.5 V (default)

8.6.2.13 REG0x18_Charger_Control_2 Register (Address = 18h) [Reset = 04h]

REG0x18_Charger_Control_2 is shown in Figure 8-29 and described in Table 8-21.

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Charger Control 2

Figure 8-29 REG0x18_Charger_Control_2 Register
76543210
EN_BYPASS_OTGEN_OTGPFM_OTG_DISPFM_FWD_DISBATFET_CTRL_WVBUSBATFET_DLYBATFET_CTRL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
Table 8-21 REG0x18_Charger_Control_2 Register Field Descriptions
BitFieldTypeResetDescription
7EN_BYPASS_OTGR/W0h Enable the Boost bypass mode

0h = Disable (default)
1h = Enable
6EN_OTGR/W0h Boost mode control
0b = OTG Disable (default)
1b = OTG Enable
5PFM_OTG_DISR/W0h Disable PFM in boost mode

0h = Enable (Default)
1h = Disable
4PFM_FWD_DISR/W0h Disable PFM in forward buck mode

0h = Enable (Default)
1h = Disable
3BATFET_CTRL_WVBUSR/W0h Optionally allows BATFET off or system power reset with adapter present.

0h = 0x0
1h = 0x1
2BATFET_DLYR/W1h Delay time added to the taking action in bits [1:0] of the BATFET_CTRL

0h = Add 20 ms delay time
1h = Add 10s delay time (default)
1:0BATFET_CTRLR/W0h BATFET control
The control logic of the BATFET to force the device enter different modes.

0h = Normal (default)
1h = Shutdown Mode
2h = Ship Mode
3h = System Power Reset

8.6.2.14 REG0x19_Charger_Control_3 Register (Address = 19h) [Reset = C4h]

REG0x19_Charger_Control_3 is shown in Figure 8-30 and described in Table 8-22.

Return to the Summary Table.

Charger Control 3

Figure 8-30 REG0x19_Charger_Control_3 Register
76543210
IBAT_PKVBAT_UVLOVBAT_OTG_MINRESERVEDEN_EXTILIMCHG_RATE
R/W-3hR/W-0hR/W-0hR-0hR/W-1hR/W-0h
Table 8-22 REG0x19_Charger_Control_3 Register Field Descriptions
BitFieldTypeResetDescription
7:6IBAT_PKR/W3h Battery discharging peak current protection threshold setting

0h = 1.5A
1h = 3A
2h = 6A
3h = 12A (default)
5VBAT_UVLOR/W0h Select the VBAT_UVLO falling threshold and VBAT_SHORT threshold

0h = VBAT_UVLO 2.2V, VBAT_SHORT 2.05V (default)
1h = VBAT_UVLO 1.8V, VBAT_SHORT 1.85V
4VBAT_OTG_MINR/W0h Select the minimal battery voltage to start the boost mode

0h = 3V rising / 2.8 falling (default)
1h = 2.6V rising / 2.4 falling
3RESERVEDR0h Reserved
2EN_EXTILIMR/W1h BQ25628:
Enable the external ILIM pin input current regulation
0b = Disabled
1b = Enabled (default)
BQ25629: Reserved with default 0
1:0CHG_RATER/W0h The charge rate definition for the fast charge stage. The charging current fold back value is equal to ICHG register setting times the fold back ratio, then divided by the charge rate.

0h = 1C (default)
1h = 2C
2h = 4C
3h = 6C

8.6.2.15 REG0x1A_NTC_Control_0 Register (Address = 1Ah) [Reset = 3Dh]

REG0x1A_NTC_Control_0 is shown in Figure 8-31 and described in Table 8-23.

Return to the Summary Table.

NTC Control 0

Figure 8-31 REG0x1A_NTC_Control_0 Register
76543210
TS_IGNORETS_TH_OTG_HOTTS_TH_OTG_COLDTS_ISET_WARMTS_ISET_COOL
R/W-0hR/W-1hR/W-1hR/W-3hR/W-1h
Table 8-23 REG0x1A_NTC_Control_0 Register Field Descriptions
BitFieldTypeResetDescription
7TS_IGNORER/W0h Ignore the TS feedback: the charger considers the TS is always good to allow charging and OTG modes, TS_STAT reports TS_NORMAL condition.

0h = Not ignore (Default)
1h = Ignore
6:5TS_TH_OTG_HOTR/W1h OTG Mode TS_HOT rising temperature threshold to transition from normal operation into suspended OTG mode when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.

0h = 55°C
1h = 60°C (default)
2h = 65°C
3h = Disable
4TS_TH_OTG_COLDR/W1h OTG Mode TS_COLD falling temperature threshold to transition from normal operation into suspended OTG mode when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.

0h = -20°C
1h = -10°C (default)
3:2TS_ISET_WARMR/W3h TS_WARM Current Setting

0h = Charge Suspend
1h = Set ICHG to 20%
2h = Set ICHG to 40%
3h = ICHG unchanged (default)
1:0TS_ISET_COOLR/W1h TS_COOL Current Setting

0h = Charge Suspend
1h = Set ICHG to 20% (default)
2h = Set ICHG to 40%
3h = ICHG unchanged

8.6.2.16 REG0x1B_NTC_Control_1 Register (Address = 1Bh) [Reset = 25h]

REG0x1B_NTC_Control_1 is shown in Figure 8-32 and described in Table 8-24.

Return to the Summary Table.

NTC Control 1

Figure 8-32 REG0x1B_NTC_Control_1 Register
76543210
TS_TH1_TH2_TH3TS_TH4_TH5_TH6TS_VSET_WARM
R/W-1hR/W-1hR/W-1h
Table 8-24 REG0x1B_NTC_Control_1 Register Field Descriptions
BitFieldTypeResetDescription
7:5TS_TH1_TH2_TH3R/W1h TH1, TH2 and TH3 comparator falling temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.

0h = TH1 is 0°C, TH2 is 5°C, TH3 is 15°C
1h = TH1 is 0°C, TH2 is 10°C, TH3 is 15°C (default)
2h = TH1 is 0°C, TH2 is 15°C, TH3 is 20°C
3h = TH1 is 0°C, TH2 is 20°C, TH3 20°C
4h = TH1 is -5°C, TH2 is 5°C, TH3 is 15°C
5h = TH1 is -5°C, TH2 is 10°C, TH3 is 15°C
6h = TH1 is -5°C, TH2 is 10°C, TH3 is 20°C
7h = TH1 is 0°C, TH2 is 10°C, TH3 is 20°C
4:2TS_TH4_TH5_TH6R/W1h TH4, TH5 and TH6 comparator rising temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.

0h = TH4 is 35°C, TH5 is 40°C, TH6 is 60°C
1h = TH4 is 35°C, TH5 is 45°C, TH6 is 60°C (default)
2h = TH4 is 35°C, TH5 is 50°C, TH6 is 60°C
3h = TH4 is 40°C, TH5 is 55°C, TH6 is 60°C
4h = TH4 is 35°C, TH5 is 40°C, TH6 is 50°C
5h = TH4 is 35°C, TH5 is 45°C, TH6 is 50°C
6h = TH4 is 40°C, TH5 is 45°C, TH6 is 60°C
7h = TH4 is 40°C, TH5 is 50°C, TH6 is 60°C
1:0TS_VSET_WARMR/W1h TS_WARM Voltage Setting

0h = Set VREG to VREG-300mV
1h = Set VREG to VREG-200mV (default)
2h = Set VREG to VREG-100mV
3h = VREG unchanged

8.6.2.17 REG0x1C_NTC_Control_2 Register (Address = 1Ch) [Reset = 3Fh]

REG0x1C_NTC_Control_2 is shown in Figure 8-33 and described in Table 8-25.

Return to the Summary Table.

NTC Control 2

Figure 8-33 REG0x1C_NTC_Control_2 Register
76543210
RESERVEDTS_VSET_SYMTS_VSET_PREWARMTS_ISET_PREWARMTS_ISET_PRECOOL
R-0hR/W-0hR/W-3hR/W-3hR/W-3h
Table 8-25 REG0x1C_NTC_Control_2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h RESERVED
6TS_VSET_SYMR/W0h When this bit is set to 0, the voltage regulation for TS_PRECOOL and TS_COOL is unchanged. When this bit is set to 1, TS_PRECOOL uses the TS_VSET_PREWARM setting of TS_PREWARM and TS_COOL uses the TS_VSET_WARM setting of TS_WARM .

0h = VREG unchanged (default)
1h = TS_COOLx matches TS_WARMx
5:4TS_VSET_PREWARMR/W3h Advanced temperature profile voltage setting for TS_PREWARM (TH4 - TH5)

0h = Set VREG to VREG-300mV
1h = Set VREG to VREG-200mV
2h = Set VREG to VREG-100mV
3h = VREG unchanged (default)
3:2TS_ISET_PREWARMR/W3h Advanced temperature profile current setting for TS_PREWARM zone(TH4 - TH5)

0h = Charge Suspend
1h = Set ICHG to 20%
2h = Set ICHG to 40%
3h = ICHG unchanged (default)
1:0TS_ISET_PRECOOLR/W3h Advanced temperature profile current setting for TS_PRECOOL zone (TH2 - TH3)

0h = Charge Suspend
1h = Set ICHG to 20%
2h = Set ICHG to 40%
3h = ICHG unchanged (default)

8.6.2.18 REG0x1D_Charger_Status_0 Register (Address = 1Dh) [Reset = 00h]

REG0x1D_Charger_Status_0 is shown in Figure 8-34 and described in Table 8-26.

Return to the Summary Table.

Charger Status 0

Figure 8-34 REG0x1D_Charger_Status_0 Register
76543210
RESERVEDADC_DONE_STATTREG_STATVSYS_STATIINDPM_STATVINDPM_STATSAFETY_TMR_STATWD_STAT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-26 REG0x1D_Charger_Status_0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ADC_DONE_STATR0h ADC Conversion Status (in one-shot mode only)
Note: Always reads 0 in continuous mode

0h = Conversion not complete
1h = Conversion complete
5TREG_STATR0h IC Thermal regulation status

0h = Normal
1h = Device in thermal regulation
4VSYS_STATR0h VSYS Regulation Status (forward mode)

0h = Not in VSYSMIN regulation (BAT>VSYSMIN)
1h = In VSYSMIN regulation (BAT<VSYSMIN)
3IINDPM_STATR0h In forward mode, indicates that either IINDPM regulation is active or ILIM pin regulation is active
In OTG mode, indicates that IOTG regulation is active

0h = Normal
1h = In IINDPM/ILIM regulation or IOTG regulation
2VINDPM_STATR0h VINDPM status (forward mode) or VOTG status (OTG mode, backup mode)

0h = Normal
1h = In VINDPM regulation or VOTG regulation
1SAFETY_TMR_STATR0h Fast charge, trickle charge and pre-charge timer status

0h = Normal
1h = Safety timer expired
0WD_STATR0h I2C watch dog timer status

0h = Normal
1h = WD timer expired

8.6.2.19 REG0x1E_Charger_Status_1 Register (Address = 1Eh) [Reset = 00h]

REG0x1E_Charger_Status_1 is shown in Figure 8-35 and described in Table 8-27.

Return to the Summary Table.

Charger Status 1

Figure 8-35 REG0x1E_Charger_Status_1 Register
76543210
RESERVEDCHG_STATVBUS_STAT
R-0hR-0hR-0h
Table 8-27 REG0x1E_Charger_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4:3CHG_STATR0h Charge Status bits

0h = Not Charging or Charge Terminated
1h = Trickle Charge, Pre-charge or Fast charge (CC mode)
2h = Taper Charge (CV mode)
3h = Top-off Timer Active Charging
2:0VBUS_STATR0h VBUS status bits
BQ25629:
000b = No qualified adapter, or EN_AUTO_INDET = 0.
001b = USB SDP Adapter (500mA)
010b = USB CDP Adapter (1.5A)
011b = USB DCP Adapter (1.5A)
100b = Unknown Adapter (500mA)
101b = Non-Standard Adapter (1A/2.1A/2.4A)
110b = Reserved
111b = In boost OTG mode
BQ25628:
100b = Unknown Adapter (default IINDPM setting)

8.6.2.20 REG0x1F_FAULT_Status_0 Register (Address = 1Fh) [Reset = 00h]

REG0x1F_FAULT_Status_0 is shown in Figure 8-36 and described in Table 8-28.

Return to the Summary Table.

FAULT Status 0

Figure 8-36 REG0x1F_FAULT_Status_0 Register
76543210
VBUS_FAULT_STATBAT_FAULT_STATSYS_FAULT_STATOTG_FAULT_STATTSHUT_STATTS_STAT
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-28 REG0x1F_FAULT_Status_0 Register Field Descriptions
BitFieldTypeResetDescription
7VBUS_FAULT_STATR0h VBUS fault status, VBUS OVP and sleep comparator

0h = Normal
1h = Device not switching due to over voltage protection or sleep comparator
6BAT_FAULT_STATR0h BAT fault status, IBAT OCP and VBAT OVP

0h = Normal
1h = Device in battery over current protection or battery overvoltage protection
5SYS_FAULT_STATR0h VSYS under voltage and over voltage status

0h = Normal
1h = SYS in SYS short circuit or over voltage
4OTG_FAULT_STATR0h Forward mode: IBUS overcurrent or PMID overvoltage
Boost mode: PMID and VBUS reverse-current, under voltage and over voltage status

0h = Normal
1h = Fault detected
3TSHUT_STATR0h IC temperature shutdown status

0h = Normal
1h = Device in thermal shutdown protection
2:0TS_STATR0h The TS temperature zone.

0h = TS_NORMAL
1h = TS_COLD or TS_OTG_COLD or TS resistor string power rail is not available.
2h = TS_HOT or TS_OTG_HOT
3h = TS_COOL
4h = TS_WARM
5h = TS_PRECOOL
6h = TS_PREWARM
7h = TS pin bias reference fault

8.6.2.21 REG0x20_Charger_Flag_0 Register (Address = 20h) [Reset = 00h]

REG0x20_Charger_Flag_0 is shown in Figure 8-37 and described in Table 8-29.

Return to the Summary Table.

Charger Flag 0

Figure 8-37 REG0x20_Charger_Flag_0 Register
76543210
RESERVEDADC_DONE_FLAGTREG_FLAGVSYS_FLAGIINDPM_FLAGVINDPM_FLAGSAFETY_TMR_FLAGWD_FLAG
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-29 REG0x20_Charger_Flag_0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ADC_DONE_FLAGR0h ADC conversion flag (only in one-shot mode)

0h = Conversion not completed
1h = Conversion completed
5TREG_FLAGR0h IC Thermal regulation flag

0h = Normal
1h = TREG signal rising threshold detected
4VSYS_FLAGR0h VSYS min regulation flag

0h = Normal
1h = Entered or existed VSYS min regulation
3IINDPM_FLAGR0h Indicates that either the IINDPM regulation loop, ILIM pin regulation or IOTG regulation loop has been entered.

0h = Normal
1h = IINDPM, ILIM or IOTG regulation signal rising edge detected
2VINDPM_FLAGR0h VINDPM or VOTG flag

0h = Normal
1h = VINDPM or VOTG regulation signal rising edge detected
1SAFETY_TMR_FLAGR0h Fast charge, trickle charge and pre-charge timer flag

0h = Normal
1h = Fast charge timer expired rising edge detected
0WD_FLAGR0h I2C watchdog timer flag

0h = Normal
1h = WD timer signal rising edge detected

8.6.2.22 REG0x21_Charger_Flag_1 Register (Address = 21h) [Reset = 00h]

REG0x21_Charger_Flag_1 is shown in Figure 8-38 and described in Table 8-30.

Return to the Summary Table.

Charger Flag 1

Figure 8-38 REG0x21_Charger_Flag_1 Register
76543210
RESERVEDCHG_FLAGRESERVEDVBUS_FLAG
R-0hR-0hR-0hR-0h
Table 8-30 REG0x21_Charger_Flag_1 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0h Reserved
3CHG_FLAGR0h Charge status flag

0h = Normal
1h = Charge status changed
2:1RESERVEDR0h Reserved
0VBUS_FLAGR0h VBUS status flag

0h = Normal
1h = VBUS status changed

8.6.2.23 REG0x22_FAULT_Flag_0 Register (Address = 22h) [Reset = 00h]

REG0x22_FAULT_Flag_0 is shown in Figure 8-39 and described in Table 8-31.

Return to the Summary Table.

FAULT Flag 0

Figure 8-39 REG0x22_FAULT_Flag_0 Register
76543210
VBUS_FAULT_FLAGBAT_FAULT_FLAGSYS_FAULT_FLAGOTG_FAULT_FLAGTSHUT_FLAGRESERVEDTS_FLAG
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-31 REG0x22_FAULT_Flag_0 Register Field Descriptions
BitFieldTypeResetDescription
7VBUS_FAULT_FLAGR0h VBUS over-voltage or sleep flag

0h = Normal
1h = Entered VBUS OVP or sleep
6BAT_FAULT_FLAGR0h IBAT over-current and VBAT over-voltage flag

0h = Normal
1h = Entered battery discharged OCP or VBAT OVP
5SYS_FAULT_FLAGR0h VSYS over voltage and SYS short flag

0h = Normal
1h = Stopped switching due to system over-voltage or SYS short fault
4OTG_FAULT_FLAGR0h Forward mode: IBUS overcurrent or PMID overvoltage
Boost mode: PMID and VBUS reverse-current, under voltage and over voltage flag

0h = Normal
1h = Turned off PMID_GD or stopped boost mode due to forward over-current, over-voltage or boost mode reverse-current, under-voltage or over-voltage faults
3TSHUT_FLAGR0h IC thermal shutdown flag

0h = Normal
1h = TS shutdown signal rising threshold detected
2:1RESERVEDR0h Reserved
0TS_FLAGR0h TS status flag

0h = Normal
1h = A change to TS status was detected

8.6.2.24 REG0x23_Charger_Mask_0 Register (Address = 23h) [Reset = 00h]

REG0x23_Charger_Mask_0 is shown in Figure 8-40 and described in Table 8-32.

Return to the Summary Table.

Charger Mask 0

Figure 8-40 REG0x23_Charger_Mask_0 Register
76543210
RESERVEDADC_DONE_MASKTREG_MASKVSYS_MASKIINDPM_MASKVINDPM_MASKSAFETY_TMR_MASKWD_MASK
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-32 REG0x23_Charger_Mask_0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ADC_DONE_MASKR/W0h ADC conversion mask flag (only in one-shot mode)

0h = ADC conversion done does produce INT pulse
1h = ADC conversion done does not produce INT pulse
5TREG_MASKR/W0h IC thermal regulation mask flag

0h = Entering TREG does produce INT
1h = Entering TREG does not produce INT
4VSYS_MASKR/W0h VSYS min regulation mask flag

0h = Enter or exit VSYSMIN regulation does produce INT pulse
1h = Enter or exit VSYSMIN regulation does not produce INT pulse
3IINDPM_MASKR/W0h IINDPM, ILIM or IOTG mask

0h = Enter IINDPM, ILIM or IOTG does produce INT pulse
1h = Enter IINDPM, ILIM or IOTG does not produce INT pulse
2VINDPM_MASKR/W0h VINDPM or VOTG mask

0h = Enter VINDPM or VOTG does produce INT pulse
1h = Enter VINDPM or VOTG does not produce INT pulse
1SAFETY_TMR_MASKR/W0h Fast charge, trickle charge and pre-charge timer mask flag

0h = Fast charge, trickle charge or pre-charge timer expiration does produce INT
1h = Fast charge, trickle charge or pre-charge timer expiration does not produce INT
0WD_MASKR/W0h I2C watch dog timer mask

0h = I2C watch dog timer expired does produce INT pulse
1h = I2C watch dog timer expired does not produce INT pulse

8.6.2.25 REG0x24_Charger_Mask_1 Register (Address = 24h) [Reset = 00h]

REG0x24_Charger_Mask_1 is shown in Figure 8-41 and described in Table 8-33.

Return to the Summary Table.

Charger Mask 1

Figure 8-41 REG0x24_Charger_Mask_1 Register
76543210
RESERVEDCHG_MASKRESERVEDVBUS_MASK
R-0hR/W-0hR-0hR/W-0h
Table 8-33 REG0x24_Charger_Mask_1 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0h Reserved
3CHG_MASKR/W0h Charge status mask flag

0h = Charging status change does produce INT
1h = Charging status change does not produce INT
2:1RESERVEDR0h Reserved
0VBUS_MASKR/W0h VBUS status mask flag

0h = VBUS status change does produce INT
1h = VBUS status change does not produce INT

8.6.2.26 REG0x25_FAULT_Mask_0 Register (Address = 25h) [Reset = 00h]

REG0x25_FAULT_Mask_0 is shown in Figure 8-42 and described in Table 8-34.

Return to the Summary Table.

FAULT Mask 0

Figure 8-42 REG0x25_FAULT_Mask_0 Register
76543210
VBUS_FAULT_MASKBAT_FAULT_MASKSYS_FAULT_MASKOTG_FAULT_MASKTSHUT_MASKRESERVEDTS_MASK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 8-34 REG0x25_FAULT_Mask_0 Register Field Descriptions
BitFieldTypeResetDescription
7VBUS_FAULT_MASKR/W0h VBUS over-voltage and sleep comparator mask flag

0h = Entering VBUS OVP or sleep does produce INT
1h = Entering VBUS OVP or sleep does not produce INT
6BAT_FAULT_MASKR/W0h IBAT over current and VBAT overvoltage mask flag

0h = IBAT OCP fault or VBAT OVP fault does produce INT
1h = Neither IBAT OCP fault nor VBAT OVP fault produces INT
5SYS_FAULT_MASKR/W0h SYS over voltage and SYS short mask

0h = System over-voltage or SYS short fault does produce INT
1h = Neither system over voltage nor SYS short fault produces INT
4OTG_FAULT_MASKR/W0h Forward mode: IBUS overcurrent or PMID overvoltage
Boost mode: PMID and VBUS reverse-current, under voltage and over voltage mask

0h = OTG VBUS or PMID reverse-current, under voltage fault or over voltage fault does produce INT
1h = Neither reverse-current fault, OTG PMID or VBUS under voltage nor over voltage fault produces INT
3TSHUT_MASKR/W0h IC thermal shutdown mask flag

0h = TSHUT does produce INT
1h = TSHUT does not produce INT
2:1RESERVEDR0h Reserved
0TS_MASKR/W0h Temperature charging profile interrupt mask

0h = A change to TS temperature zone does produce INT
1h = A change to the TS temperature zone does not produce INT

8.6.2.27 REG0x26_ADC_Control Register (Address = 26h) [Reset = 30h]

REG0x26_ADC_Control is shown in Figure 8-43 and described in Table 8-35.

Return to the Summary Table.

ADC Control

Figure 8-43 REG0x26_ADC_Control Register
76543210
ADC_ENADC_RATEADC_SAMPLEADC_AVGADC_AVG_INITRESERVED
R/W-0hR/W-0hR/W-3hR/W-0hR/W-0hR-0h
Table 8-35 REG0x26_ADC_Control Register Field Descriptions
BitFieldTypeResetDescription
7ADC_ENR/W0h ADC Control
The registers POR to all 0 's, then after that always retain the last measurement, and never clear.

0h = Disable (default)
1h = Enable
6ADC_RATER/W0h ADC conversion rate control

0h = Continuous conversion (default)
1h = One shot conversion
5:4ADC_SAMPLER/W3h ADC sample speed

0h = 12 bit effective resolution
1h = 11 bit effective resolution
2h = 10 bit effective resolution
3h = 9 bit effective resolution (default)
3ADC_AVGR/W0h ADC average control

0h = Single value (default)
1h = Running average
2ADC_AVG_INITR/W0h ADC average initial value control

0h = Start average using the existing register value (default)
1h = Start average using a new ADC conversion
1:0RESERVEDR0h Reserved

8.6.2.28 REG0x27_ADC_Function_Disable_0 Register (Address = 27h) [Reset = 00h]

REG0x27_ADC_Function_Disable_0 is shown in Figure 8-44 and described in Table 8-36.

Return to the Summary Table.

ADC Function Disable 0

Figure 8-44 REG0x27_ADC_Function_Disable_0 Register
76543210
IBUS_ADC_DISIBAT_ADC_DISVBUS_ADC_DISVBAT_ADC_DISVSYS_ADC_DISTS_ADC_DISTDIE_ADC_DISVPMID_ADC_DIS
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-36 REG0x27_ADC_Function_Disable_0 Register Field Descriptions
BitFieldTypeResetDescription
7IBUS_ADC_DISR/W0h IBUS ADC control

0h = Enable (Default)
1h = Disable
6IBAT_ADC_DISR/W0h IBAT ADC control

0h = Enable (Default)
1h = Disable
5VBUS_ADC_DISR/W0h VBUS ADC control

0h = Enable (Default)
1h = Disable
4VBAT_ADC_DISR/W0h VBAT ADC control

0h = Enable (Default)
1h = Disable
3VSYS_ADC_DISR/W0h VSYS ADC control

0h = Enable (Default)
1h = Disable
2TS_ADC_DISR/W0h TS ADC control

0h = Enable (Default)
1h = Disable
1TDIE_ADC_DISR/W0h TDIE ADC control

0h = Enable (Default)
1h = Disable
0VPMID_ADC_DISR/W0h VPMID ADC control

0h = Enable (Default)
1h = Disable

8.6.2.29 REG0x28_IBUS_ADC Register (Address = 28h) [Reset = 0000h]

REG0x28_IBUS_ADC is shown in Figure 8-45 and described in Table 8-37.

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IBUS ADC

Figure 8-45 REG0x28_IBUS_ADC Register
15141312111098
IBUS_ADC
R-0h
76543210
IBUS_ADCRESERVED
R-0hR-0h
Table 8-37 REG0x28_IBUS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:1IBUS_ADCR0h IBUS ADC reading
Reported in 2 's Complement.
When the current is flowing from VBUS to PMID, IBUS ADC reports positive value, and when the current is flowing from PMID to VBUS, IBUS ADC reports negative value.
POR: 0mA (0h)
Format: 2s Complement
Range: -4000mA-4000mA (7830h-7FFFh), (0h-7D0h)
Clamped Low
Clamped High
Bit Step: 2mA
0RESERVEDR0h Reserved

8.6.2.30 REG0x2A_IBAT_ADC Register (Address = 2Ah) [Reset = 0000h]

REG0x2A_IBAT_ADC is shown in Figure 8-46 and described in Table 8-38.

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IBAT ADC

Figure 8-46 REG0x2A_IBAT_ADC Register
15141312111098
IBAT_ADC
R-0h
76543210
IBAT_ADCRESERVED
R-0hR-0h
Table 8-38 REG0x2A_IBAT_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:2IBAT_ADCR0h IBAT ADC reading
Reported in 2 's Complement.
The IBAT ADC reports positive value for the battery charging current, and negative value for the battery discharging current.
The IBAT ADC resets to zero when EN_CHG=0.
POR: 0mA (0h)
Format: 2s Complement
Range: -7500mA-4000mA (38ADh-3FFFh), (0h-3E8h)
Clamped Low
Clamped High
Bit Step: 4mA
The IBAT ADC current can only be positive or zero in forward mode, and negative or zero in battery-only mode. If polarity of battery current changes from charging to discharging or vice-versa during the ADC measurement, the conversion is aborted and the register reports code 0x8000 (which is code 0x2000 for IBAT_ADC field)
1:0RESERVEDR0h Reserved

8.6.2.31 REG0x2C_VBUS_ADC Register (Address = 2Ch) [Reset = 0000h]

REG0x2C_VBUS_ADC is shown in Figure 8-47 and described in Table 8-39.

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VBUS ADC

Figure 8-47 REG0x2C_VBUS_ADC Register
15141312111098
RESERVEDVBUS_ADC
R-0hR-0h
76543210
VBUS_ADCRESERVED
R-0hR-0h
Table 8-39 REG0x2C_VBUS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14:2VBUS_ADCR0h VBUS ADC reading
POR: 0mV (0h)
Range: 0mV-18000mV (0h-11B6h)
Clamped High
Bit Step: 3.97mV
1:0RESERVEDR0h Reserved

8.6.2.32 REG0x2E_VPMID_ADC Register (Address = 2Eh) [Reset = 0000h]

REG0x2E_VPMID_ADC is shown in Figure 8-48 and described in Table 8-40.

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VPMID ADC

Figure 8-48 REG0x2E_VPMID_ADC Register
15141312111098
RESERVEDVPMID_ADC
R-0hR-0h
76543210
VPMID_ADCRESERVED
R-0hR-0h
Table 8-40 REG0x2E_VPMID_ADC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14:2VPMID_ADCR0h VPMID ADC reading
POR: 0mV (0h)
Range: 0mV-18000mV (0h-11B6h)
Clamped High
Bit Step: 3.97mV
1:0RESERVEDR0h Reserved

8.6.2.33 REG0x30_VBAT_ADC Register (Address = 30h) [Reset = 0000h]

REG0x30_VBAT_ADC is shown in Figure 8-49 and described in Table 8-41.

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VBAT ADC

Figure 8-49 REG0x30_VBAT_ADC Register
15141312111098
RESERVEDVBAT_ADC
R-0hR-0h
76543210
VBAT_ADCRESERVED
R-0hR-0h
Table 8-41 REG0x30_VBAT_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR0h Reserved
12:1VBAT_ADCR0h VBAT ADC reading
POR: 0mV (0h)
Range: 0mV-5572mV (0h-AF0h)
Clamped High
Bit Step: 1.99mV
0RESERVEDR0h Reserved

8.6.2.34 REG0x32_VSYS_ADC Register (Address = 32h) [Reset = 0000h]

REG0x32_VSYS_ADC is shown in Figure 8-50 and described in Table 8-42.

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VSYS ADC

Figure 8-50 REG0x32_VSYS_ADC Register
15141312111098
RESERVEDVSYS_ADC
R-0hR-0h
76543210
VSYS_ADCRESERVED
R-0hR-0h
Table 8-42 REG0x32_VSYS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR0h Reserved
12:1VSYS_ADCR0h VSYS ADC reading
POR: 0mV (0h)
Range: 0mV-5572mV (0h-AF0h)
Clamped High
Bit Step: 1.99mV
0RESERVEDR0h Reserved

8.6.2.35 REG0x34_TS_ADC Register (Address = 34h) [Reset = 0000h]

REG0x34_TS_ADC is shown in Figure 8-51 and described in Table 8-43.

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TS ADC

Figure 8-51 REG0x34_TS_ADC Register
15141312111098
RESERVEDTS_ADC
R-0hR-0h
76543210
TS_ADC
R-0h
Table 8-43 REG0x34_TS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0h Reserved
11:0TS_ADCR0h TS ADC reading as TS pin voltage in percentage of bias reference. Valid with TS pin bias reference active.
POR: 0%(0h)
Range: 0% - 98.3103% (0h-3FFh)
Clamped High
Bit Step: 0.0961%

8.6.2.36 REG0x36_TDIE_ADC Register (Address = 36h) [Reset = 0000h]

REG0x36_TDIE_ADC is shown in Figure 8-52 and described in Table 8-44.

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TDIE ADC

Figure 8-52 REG0x36_TDIE_ADC Register
15141312111098
RESERVEDTDIE_ADC
R-0hR-0h
76543210
TDIE_ADC
R-0h
Table 8-44 REG0x36_TDIE_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0h Reserved
11:0TDIE_ADCR0h TDIE ADC reading
Reported in 2 's Complement.
POR: 0°C(0h)
Format: 2s Complement
Range: -40°C - 140°C (FB0h-118h)
Clamped Low
Clamped High
Bit Step: 0.5°C

8.6.2.37 REG0x38_Part_Information Register (Address = 38h) [Reset = 02h]

REG0x38_Part_Information is shown in Figure 8-53 and described in Table 8-45.

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Part Information

Figure 8-53 REG0x38_Part_Information Register
76543210
RESERVEDPNDEV_REV
R-0hR-0hR-2h
Table 8-45 REG0x38_Part_Information Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:3PNR0h Device Part number
2h = BQ25628
6h = BQ25629
2:0DEV_REVR2h Device Revision