SCAS891A February   2010  – May 2025 CDCE949-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Resistance Characteristics
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Recommended Crystal/VCXO Specifications
    6. 5.6  EEPROM Specification
    7. 5.7  Electrical Characteristics
    8. 5.8  Timing Requirements
      1. 5.8.1 CLK_IN Timing Requirements
      2. 5.8.2 SDA/SCL Timing Requirements
    9. 5.9  Timing Diagrams
      1. 5.9.1 Timing Diagram for the SDA/SCL Serial Control Interface
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
      5. 7.3.5 PLL Multiplier/Divider Definition
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
      1. 7.5.1 Generic Programming Sequence
      2. 7.5.2 Byte Write Programming Sequence
      3. 7.5.3 Byte Read Programming Sequence
      4. 7.5.4 Block Write Programming Sequence
      5. 7.5.5 Block Read Programming Sequence
  9. 8 Register Maps
    1. 8.1 SDA and SCL Registers
    2. 8.2 Configuration Registers
      1. 8.2.1 Generic Configuration Register
      2. 8.2.2 PLL1 Configuration Register
      3. 8.2.3 PLL2 Configuration Register
      4. 8.2.4 PLL3 Configuration Register
      5. 8.2.5 PLL4 Configuration Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Generic Configuration Register

Table 8-3 Generic Configuration Register
OFFSET(1) Bit(2) Acronym Default(3) DESCRIPTION
00h 7 E_EL xb Device Identification (read only): 1 is CDCE949 (3.3V), 0 is CDCEL949 (1.8V)
6:4 RID Xb Revision Identification Number (read only)
3:0 VID 1h Vendor Identification Number (read only)
01h 7 – 0b Reserved - always write 0
6 EEPIP 0b EEPROM Programming Status(4): (read only) 0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5 EELOCK 0b Permanently Lock EEPROM Data(5): 0 – EEPROM is not locked
1 – EEPROM is permanently locked
4 PWDN 0b Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-State)
3:2 INCLK 00b Input clock selection: 00 – X-tal
01 – VCXO		 10 – LVCMOS
11 – reserved
1:0 I2C_ADR 00b Programmable Address Bits A0 and A1 of the Target Receiver Address
02h 7 M1 1b Clock source selection for output Y1: 0 – input clock
1 – PLL1 clock
6 SPICON 0b Operation mode selection for pin 22/23(6)
0 – serial programming interface SDA (pin 23) and SCL (pin 22)
1 – control pins S1 (pin 23) and S2 (pin 22)
5:4 Y1_ST1 11b Y1-State0/1 Definition (applies to Y1_ST1 and Y1_ST0)
3:2 Y1_ST0 01b 00 – device power down (all PLLs in power down and all outputs in 3-state)
01 – Y1 disabled to 3-state
10 – Y1 disabled to low
11 – Y1 enabled (normal operation)
1:0 Pdiv1 [9:8] 001h 10-Bit Y1-Output-Divider Pdiv1: 0 – divider reset and stand-by
1-to-1023 – divider value
03h 7:0 Pdiv1 [7:0]
04h 7 Y1_7 0b Y1_x State Selection(7)
6 Y1_6 0b 0 – State0 (predefined by Y1-State0 Definition [Y1_ST0])
1 – State1 (predefined by Y1-State1 Definition [Y1_ST1])
5 Y1_5 0b
4 Y1_4 0b
3 Y1_3 0b
2 Y1_2 0b
1 Y1_1 1b
0 Y1_0 0b
05h 7:3 XCSEL 0Ah Crystal load capacitor selection(8): 00h → 0pF
01h → 1pF
02h → 2pF
14h-to-1Fh → 20pF		 CDCE949-Q1
2:0 — 0b Reserved - do not write others than 0
06h 7:1 BCOUNT 50h 7-Bit Byte Count (Defines the number of Bytes which is sent from this device at the next Block Read transfer; all bytes must be read out to correctly finish the read cycle.)
0 EEWRITE 0b Initiate EEPROM Write Cycle(4)(9)
0 – no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
07h-0Fh — — 0h Reserved – do not write others than 0
(1) Writing data beyond ‘50h’ can adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless custom setting is used.
(4) During EEPROM programming, no data is allowed to be sent to the device using the SDA/SCL bus until the programming sequence is completed. Data, however, can be read during the programming sequence (Byte Read or Block Read).
(5) If this bit is set high in the EEPROM, the actual data in the EEPROM is permanently locked, and no further programming is possible. Data, however can still be written using SDA/SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM
(6) Selection of control-pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporarily act as serial programming pins (SDA/SCL), and the two target receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. These settings can then be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors are used only to do a fine adjustment of CL by few pF. The value of CL can be programmed with a resolution of 1pF for a total crystal load range of 0pF to 20pF. For CL > 20pF use additional external capacitors. Also, the device input capacitance must be considered; this adds 1.5pF (6pF//2pF) to the selected CL. For more information about VCXO configuration and crystal recommendations, see application note SCAA085
(9) NOTE: The EEPROM WRITE bit must be sent last. This verifies that the content of all internal registers are written into the EEPROM. The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP. If EELOCK is set high, no EEPROM programming is possible.