Product details

Function Clock generator, Spread-spectrum clock generator Number of outputs 9 Output frequency (Max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type XTAL, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 125 Features I2C, Integrated EEPROM, Pin programmable, Spread-spectrum clocking (SSC) Rating Automotive
Function Clock generator, Spread-spectrum clock generator Number of outputs 9 Output frequency (Max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type XTAL, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 125 Features I2C, Integrated EEPROM, Pin programmable, Spread-spectrum clocking (SSC) Rating Automotive
TSSOP (PW) 24 34 mm² 7.7 x 4.4
  • Qualified for Automotive Applications
  • Member of Programmable Clock Generator Family
    • CDCE913/CDCEL913: 1 PLLs, 3 Outputs
    • CDCE925/CDCEL925: 2 PLLs, 5 Outputs
    • CDCE937/CDCEL937: 3 PLLs, 7 Outputs
    • CDCE949: 4 PLLs, 9 Outputs
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Non-Volatile EEPROM to Store Customer Settings
  • Highly Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; e.g,. SSC-Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly-Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Generates Common Clock Frequencies Used with TI DaVinci™, OMAP™, DSPs
    • BlueTooth™, WLAN, Ethernet and GPS
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • Selectable Output Frequency up to 230 MHz
  • Flexible Input Clocking Concept
    • External Crystal: 8 to 32 MHz
    • On-Chip VCXO: Pull-Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Very Low Period Jitter (typ 60 ps)
  • Separate Output Supply Pins
    • 3.3 V and 2.5 V
  • 1.8 V Device Power Supply
  • Latch-Up Performace Meets 100 mA
    Per JESD 78, Class I
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Ease PLL Design and Programming
    (TI-Pro Clock)
  • APPLICATIONS
    • D-TV, HD-TV, STB, IP-STB, DVD-Player, DVD-Recorder, Printer
    • General Purpose Frequency Synthesizing

  • Qualified for Automotive Applications
  • Member of Programmable Clock Generator Family
    • CDCE913/CDCEL913: 1 PLLs, 3 Outputs
    • CDCE925/CDCEL925: 2 PLLs, 5 Outputs
    • CDCE937/CDCEL937: 3 PLLs, 7 Outputs
    • CDCE949: 4 PLLs, 9 Outputs
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Non-Volatile EEPROM to Store Customer Settings
  • Highly Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; e.g,. SSC-Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly-Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Generates Common Clock Frequencies Used with TI DaVinci™, OMAP™, DSPs
    • BlueTooth™, WLAN, Ethernet and GPS
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • Selectable Output Frequency up to 230 MHz
  • Flexible Input Clocking Concept
    • External Crystal: 8 to 32 MHz
    • On-Chip VCXO: Pull-Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Very Low Period Jitter (typ 60 ps)
  • Separate Output Supply Pins
    • 3.3 V and 2.5 V
  • 1.8 V Device Power Supply
  • Latch-Up Performace Meets 100 mA
    Per JESD 78, Class I
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Ease PLL Design and Programming
    (TI-Pro Clock)
  • APPLICATIONS
    • D-TV, HD-TV, STB, IP-STB, DVD-Player, DVD-Recorder, Printer
    • General Purpose Frequency Synthesizing

The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.

The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration (see the Default device Configuration section). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C.

The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.

The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration (see the Default device Configuration section). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C.

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Technical documentation

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Type Title Date
* Data sheet CDCE949-Q1 Programmable 4-PLL VCXO Clock Synthesizer datasheet 03 Feb 2010
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Application note Crystal or Crystal Oscillator Replacement with Silicon Devices 18 Jun 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 23 Apr 2012
Application note General I2C / EEPROM usage for the CDCE(L)9xx family 26 Jan 2010
Application note Troubleshooting I2C Bus Protocol 19 Oct 2009
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 23 Sep 2009
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 31 Mar 2008

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