SCAS891A February   2010  – May 2025 CDCE949-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Resistance Characteristics
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Recommended Crystal/VCXO Specifications
    6. 5.6  EEPROM Specification
    7. 5.7  Electrical Characteristics
    8. 5.8  Timing Requirements
      1. 5.8.1 CLK_IN Timing Requirements
      2. 5.8.2 SDA/SCL Timing Requirements
    9. 5.9  Timing Diagrams
      1. 5.9.1 Timing Diagram for the SDA/SCL Serial Control Interface
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
      5. 7.3.5 PLL Multiplier/Divider Definition
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
      1. 7.5.1 Generic Programming Sequence
      2. 7.5.2 Byte Write Programming Sequence
      3. 7.5.3 Byte Read Programming Sequence
      4. 7.5.4 Block Write Programming Sequence
      5. 7.5.5 Block Read Programming Sequence
  9. 8 Register Maps
    1. 8.1 SDA and SCL Registers
    2. 8.2 Configuration Registers
      1. 8.2.1 Generic Configuration Register
      2. 8.2.2 PLL1 Configuration Register
      3. 8.2.3 PLL2 Configuration Register
      4. 8.2.4 PLL3 Configuration Register
      5. 8.2.5 PLL4 Configuration Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • Member of Programmable Clock Generator Family
    • CDCE913/CDCEL913: 1 PLLs, 3 Outputs
    • CDCE925/CDCEL925: 2 PLLs, 5 Outputs
    • CDCE937/CDCEL937: 3 PLLs, 7 Outputs
    • CDCE949: 4 PLLs, 9 Outputs
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Non-Volatile EEPROM to Store Customer Settings
  • Highly Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; such as SSC-Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly-Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Generates Common Clock Frequencies Used with TI DaVinci™, OMAP™, DSPs
    • BlueTooth™, WLAN, Ethernet and GPS
    • Programmable SSC Modulation
    • Enables 0ppm Clock Generation
  • Selectable Output Frequency up to 230MHz
  • Flexible Input Clocking Concept
    • External Crystal: 8MHz to 32MHz
    • On-Chip VCXO: Pull-Range ±150ppm
    • Single-Ended LVCMOS up to 160MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Very Low Period Jitter (typical 60ps)
  • Separate Output Supply Pins
    • 3.3V and 2.5V
  • 1.8V Device Power Supply
  • Latch-Up Performance Meets 100mA
    Per JESD 78, Class I
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Ease PLL Design and Programming (TI ClockPro)