SCAS891A February   2010  – May 2025 CDCE949-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Resistance Characteristics
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Recommended Crystal/VCXO Specifications
    6. 5.6  EEPROM Specification
    7. 5.7  Electrical Characteristics
    8. 5.8  Timing Requirements
      1. 5.8.1 CLK_IN Timing Requirements
      2. 5.8.2 SDA/SCL Timing Requirements
    9. 5.9  Timing Diagrams
      1. 5.9.1 Timing Diagram for the SDA/SCL Serial Control Interface
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
      5. 7.3.5 PLL Multiplier/Divider Definition
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
      1. 7.5.1 Generic Programming Sequence
      2. 7.5.2 Byte Write Programming Sequence
      3. 7.5.3 Byte Read Programming Sequence
      4. 7.5.4 Block Write Programming Sequence
      5. 7.5.5 Block Read Programming Sequence
  9. 8 Register Maps
    1. 8.1 SDA and SCL Registers
    2. 8.2 Configuration Registers
      1. 8.2.1 Generic Configuration Register
      2. 8.2.2 PLL1 Configuration Register
      3. 8.2.3 PLL2 Configuration Register
      4. 8.2.4 PLL3 Configuration Register
      5. 8.2.5 PLL4 Configuration Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

over recommended operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
OVERALL PARAMETER
IDD Supply current (see Figure 5-2) All outputs off, fCLK = 27MHz, fVCO= 135MHz All PLLs on 38 mA
Per PLL 9
IDD(OUT) Supply current (see Figure 5-3) No load, all outputs on, fout = 27MHz,
VDDOUT = 3.3V		 4 mA
IDD(PD) Power down current. Every circuit powered down except SDA/SCL. fIN = 0MHz, VDD = 1.9V 50 μA
V(PUC) Supply voltage VDD threshold for power up control circuit 0.85 1.45 V
fVCO VCO frequency range of PLL 80 230 MHz
fOUT LVCMOS output frequency 230 MHz
LVCMOS PARAMETER
VIK LVCMOS input voltage VDD = 1.7V; II = –18mA –1.2 V
II LVCMOS input current VI = 0V or VDD; VDD = 1.9V ±5 μA
IIH LVCMOS input current for S0/S1/S2 VI = VDD; VDD = 1.9V 5 μA
IIL LVCMOS input current for S0/S1/S2 VI = 0V; VDD = 1.9V –4 μA
CI Input capacitance at Xin/Clk VICLK = 0V or VDD 6 pF
Input capacitance at Xout VIXout = 0V or VDD 2
Input capacitance at S0/S1/S2 VIS = 0V or VDD 3
LVCMOS PARAMETER FOR VDDOUT = 3.3V – MODE
VOH LVCMOS high-level output voltage VDDOUT = 3V, IOH = –0.1mA 2.9 V
VDDOUT = 3V, IOH = –8mA 2.4
VDDOUT = 3V, IOH = –12mA 2.2
VOL LVCMOS low-level output voltage VDDOUT = 3V, IOL = 0.1mA 0.1 V
VDDOUT = 3V, IOL = 8mA 0.5
VDDOUT = 3V, IOL = 12mA 0.8
tPLH, tPHL Propagation delay PLL bypass 3.2 ns
tr/tf Rise and fall time VDDOUT = 3.3V (20%–80%) 0.6 ns
tjit(cc) Cycle-to-cycle jitter(2)(3) 1 PLL switching, Y2-to-Y3 60 90 ps
4 PLLs switching, Y2-to-Y9 120 170
tjit(per) Peak-to-peak period jitter (2)(3) 1 PLL switching, Y2-to-Y3 70 100 ps
4 PLLs switching, Y2-to-Y9 130 180
tsk(o) Output skew(4) fOUT = 50MHz; Y1-to-Y3 60 ps
fOUT = 50MHz; Y2-to-Y5 or Y6-to-Y9 160
odc Output duty cycle(5) fVCO = 100MHz; Pdiv = 1 45 55 %
LVCMOS PARAMETER FOR VDDOUT = 2.5V – MODE
VOH LVCMOS high-level output voltage VDDOUT = 2.3V, IOH = –0.1mA 2.2 V
VDDOUT = 2.3V, IOH = –6mA 1.7
VDDOUT = 2.3V, IOH = –10mA 1.6
VOL LVCMOS low-level output voltage VDDOUT = 2.3V, IOL = 0.1mA 0.1 V
VDDOUT = 2.3V, IOL = 6mA 0.5
VDDOUT = 2.3V, IOL = 10mA 0.7
tPLH, tPHL Propagation delay PLL bypass 3.4 ns
tr/tf Rise and fall time VDDOUT = 2.5V (20%–80%) 0.8 ns
tjit(cc) Cycle-to-cycle jitter (2)(3) 1 PLL switching, Y2-to-Y3 60 90 ps
4 PLLs switching, Y2-to-Y9 120 170
tjit(per) Peak-to-peak period jitter (2)(3) 1 PLL switching, Y2-to-Y3 70 100 ps
4 PLLs switching, Y2-to-Y9 130 180
tsk(o) Output skew(4) fOUT = 50MHz; Y1-to-Y3 60 ps
fOUT = 50MHz; Y2-to-Y5 or Y6-to-Y9 160
odc Output duty cycle(5) fVCO = 100MHz; Pdiv = 1 45 55 %
SDA/SCL PARAMETER
VIK SCL and SDA input clamp voltage VDD = 1.7V; II = –18mA –1.2 V
IIH SCL and SDA input current VI = VDD; VDD = 1.9V ±10 μA
VIH SDA/SCL input high voltage(6) 0.7VDD V
VIL SDA/SCL input low voltage(6) 0.3VDD V
VOL SDA low-level output voltage IOL = 3mA, VDD = 1.7V 0.2VDD V
CI SCL/SDA input capacitance VI = 0V or VDD 3 10 pF
(1) All typical values are at respective nominal VDD.
(2) 10000 cycles.
(3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27MHz, Y2/3 = 27MHz, (measured at Y2), 4-PLL: fIN = 27MHz, Y2/3 = 27MHz, (manured at Y2), Y4/5 = 16.384MHz, Y6/7 = 74.25MHz, Y8/9 = 48MHz.
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data sampled on rising edge (tr).
(5) odc depends on output rise- and fall-time (tr/tf).
(6) SDA and SCL pins are 3.3V tolerant.