SNAS734F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
An ultra-low power clock generator is designed to drive clocks in industrial, portable and data center applications. The device is flexible in its configuration and be pre-preprogramed with two separate configuration. For example a production test and an application configuration, or two different configurations for two flavors of a product. The internal EEPROM is protected by a CRC hash which is available as a status bit. The two EEPROM pages are selected using a control pin. As each major block of the device is powered by its own supply pin, the device can easily be used for signal translation and to accommodate various supply voltages which may be available in a system. Up to five different frequencies can be generated from a single device and feed different parts of an application. Each of the four differential outputs supports various signal standards. The general purpose pin functionality can provide status information to other parts of the system and can add modularity and flexibility to an application. Clock outputs can be muted individually or globally, the division ratio updated, the output dividers synchronized and a spread spectrum function enabled or disabled. The clock generator PLL can also be used in a zero delay mode which will compensate most of the seen phase delay between an external reference clock and the output clocks. Together with an external feedback option this allows to compensate traces on top of the digital delay steps provided inside the device. All these features make the ultra-low power clock generator for design library integration and re-use in modular projects.