SCAS666D June 2001 – October 2015 CDCVF2310
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The CDCVF2310 is a LVCMOS buffer solution that can operate up to 200 MHz. Low output skew as well as the ability for glitchless output enable and disable is featured to simultaneously enable or disable buffered clock outputs as necessary in the application.
The CDCVF2310 shown in Figure 7 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator. The CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following properties:
Refer to Electrical Characteristics table to determine the appropriate series resistance needed for matching the output impedance of the CDCVF2310 to that of the characteristic impedance of the transmission line.
The low-additive jitter of the CDCVF2310 can be seen in the previous application plots. The low-noise, 125-MHz input source drives the CDCVF2310, resulting in 45-fs RMS additive jitter when integrated from 12 kHz to 20 MHz for this configuration. The low-noise 30.72-MHz input source drives the CDCVF2310, resulting in 52-fs RMS additive jitter when integrated from 12 kHz to 5 MHz for this configuration.
The CDCVF2310 can be configured to generate a gated clock using the GN Please refer to Output Enable Glitch Suppression Circuit for required timings.