SLPS350A February   2014  – January 2017 CSD87333Q3D

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6 Applications
    1. 6.1 Power Loss Curves
    2. 6.2 Safe Operating Area (SOA) Curves
    3. 6.3 Normalized Curves
    4. 6.4 Calculating Power Loss and SOA
      1. 6.4.1 Design Example
      2. 6.4.2 Calculating Power Loss
      3. 6.4.3 Calculating SOA Adjustments
  7. 7 Recommended PCB Design Overview
    1. 7.1 Electrical Performance
  8. 8 Thermal Performance
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Q3D Package Dimensions
    2. 10.2 Pinout Configuration
    3. 10.3 Land Pattern Recommendation
    4. 10.4 Stencil Recommendation
    5. 10.5 Q3D Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Thermal Performance

The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 21 uses vias with a 10-mil drill hole and a 16-mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

CSD87333Q3D Fig34.png Figure 21. Recommended PCB Layout (Top Down)